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- #include "nrf24L01.h"
- #include "printf.h"
- #include "delay.h"
-
- const u8 TX_ADDRESS[5]={0x34,0x43,0x10,0x10,0x01}; //͵ַ
- const u8 RX_ADDRESS[5]={0x34,0x43,0x10,0x10,0x01};
-
- const u8 addr[5]={0x33,0x20,0x0D,0x54,0x79};
- const u8 Jiang_Xi[5]={0x33,0x20,0x0D,0x54,0x79};
-
- const u8 TEL_PO[5]={0x34,0x43,0x10,0x10,0x01};
- const u8 YUN_NAN[5]={0x01,0x10,0x10,0x43,0x34};
- const u8 GUI_ZHOU[5]={0x32,0x23,0xAB,0xBA,0x01};
- const u8 SI_CHUAN[5]={0x34,0x12,0xBB,0xAA,0x01};
- const u8 NEI_MENG_GU[5]={0x34,0x12,0x86,0x75,0x01};
- const u8 AN_HUI[5]={0x46,0x56,0x43,0x10,0x00};
- const u8 SHAN_XI_XIN_NUO[5]={0x34,0x6E,0x46,0x10,0x01};
- const u8 VCM[5]={0x34,0x43,0x10,0x10,0x01};
- const u8 LIAO_NING[5]={0x86,0x2c,0x95,0x01,0x01};
- const u8 NEW_LIAO_NING[5] = {0x36,0xE4,0xA7,0xBC,0x01};
- const u8 TP[5] = {0x42,0x18,0xba,0xe8,0x01};
- const u8 NEI_MENG_GU_YI_DONG[5]={0x34,0x12,0x86,0x75,0x01};
- const u8 GUANG_XI_YI_DONG[5]={0x33,0x20,0x0D,0x54,0x00};
-
- const u8 LIAO_NING_DIAN_XI[5]={0x86,0x2C,0x95,0x00,0x00};
- const u8 FU_JIAN_ZHEN_ZHUO[5]={0x5A,0x45,0x4E,0x4B,0x00};
- const u8 SU_ZHOU_MU_LANG[5]={0xAA,0xBB,0x12,0x34,0x00};
- const u8 CHONG_QIN_YI_DONG[5]={0x34,0x12,0xBB,0xAA,0x00};
- const u8 SHAN_XI_YI_DONG[5]={0x25,0x43,0x10,0x12,0x00};
- const u8 QUAN_TONG[5]={0xe7,0x7e,0xe3,0x00,0x00};
- const u8 GAN_SU_YI_DONG[5]={0x42,0x22,0xB6,0xE9,0x00};
- const u8 XDF[5]={0xC0,0x13,0xE3,0x00,0x00};
- const u8 DH[5] = {0x83,0x21,0x95,0x15,0x00};
- const u8 ANHUI_DIANXIN[5] = {0x41,0x15,0x43,0x12,0x00};
- //ʼ24L01IO
- void NRF24L01_Init(void)
- {
- GPIO_InitTypeDef GPIO_InitStructure;
-
-
- //ʹPA,B,C˿ʱ
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE);
-
-
- GPIO_InitStructure.GPIO_Pin = SPI1_CE_Pin; // SPI1--CE
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPI1_CE_Port, &GPIO_InitStructure); //ʼָIO
- GPIO_SetBits(SPI1_CE_Port,SPI1_CE_Pin);//
-
- GPIO_InitStructure.GPIO_Pin = SPI1_CS_Pin; // SPI1--CS
- GPIO_Init(SPI1_CS_Port, &GPIO_InitStructure); //ʼָIO
- GPIO_SetBits(SPI1_CS_Port,SPI1_CS_Pin);//
-
- GPIO_InitStructure.GPIO_Pin = SPI1_IRQ_Pin; // SPI1--IRQ
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; //
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPI1_IRQ_Port, &GPIO_InitStructure); //ʼָIO
-
- GPIO_InitStructure.GPIO_Pin = SPI2_CE_Pin;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPI2_CE_Port, &GPIO_InitStructure); //ʼָIO
- GPIO_SetBits(SPI2_CE_Port,SPI2_CE_Pin);//
-
- GPIO_InitStructure.GPIO_Pin = SPI2_CS_Pin;
- GPIO_Init(SPI2_CS_Port, &GPIO_InitStructure); //ʼָIO
- GPIO_SetBits(SPI2_CS_Port,SPI2_CS_Pin);//
-
- GPIO_InitStructure.GPIO_Pin = SPI2_IRQ_Pin; //SPI2--IQR
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; //
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPI2_IRQ_Port, &GPIO_InitStructure); //ʼָIO
-
-
- SPI2_Init(); //ʼSPI
- SPI1_Init();
-
- SPI1_CE =0; //ʹ24L01
- SPI1_CSN=1; //SPIƬѡȡ
-
- SPI2_CE =0; //ʹ24L01
- SPI2_CSN=1; //SPIƬѡȡ
-
- SPI_SetSpeed(SPI_REV,SPI_BaudRatePrescaler_4);
-
- }
-
- void NRF24L01_Config(SPIType spiNum)
- {
- if(spiNum == SPI_PORT1)
- {
- SPI1_CE = 0; //chip enable
- SPI1_CSN = 1; //SPI disable
- }
- else
- {
- SPI2_CE = 0; //chip enable
- SPI2_CSN = 1; //SPI disable
- }
-
- }
-
- //SPIдĴ
- //reg:ָĴַ
- //value:дֵ
- u8 NRF24L01_Write_Reg(SPIType spiNum,u8 reg,u8 value)
- {
- u8 status;
- if(spiNum == SPI_PORT1){
- SPI1_CSN=0; //ʹSPI
- status =SPI_ReadWriteByte(spiNum,reg);//ͼĴ
- SPI_ReadWriteByte(spiNum,value); //дĴֵ
- SPI1_CSN=1; //ֹSPI
- }else{
- SPI2_CSN=0; //ʹSPI
- status =SPI_ReadWriteByte(spiNum,reg);//ͼĴ
- SPI_ReadWriteByte(spiNum,value); //дĴֵ
- SPI2_CSN=1; //ֹSPI
- }
- return(status); //״ֵ̬
- }
- //ȡSPIĴֵ
- //reg:ҪļĴ
- u8 NRF24L01_Read_Reg(SPIType spiNum,u8 reg)
- {
- u8 reg_val;
- if(spiNum == SPI_PORT1){
- SPI1_CSN = 0; //ʹSPI
- SPI_ReadWriteByte(spiNum,reg); //ͼĴ
- reg_val=SPI_ReadWriteByte(spiNum,0XFF);//ȡĴ
- SPI1_CSN = 1; //ֹSPI
- }else{
- SPI2_CSN = 0; //ʹSPI
- SPI_ReadWriteByte(spiNum,reg); //ͼĴ
- reg_val=SPI_ReadWriteByte(spiNum,0XFF);//ȡĴ
- SPI2_CSN = 1; //ֹSPI
- }
- return(reg_val); //״ֵ̬
- }
-
- //ָλöָȵ
- //reg:Ĵ(λ)
- //*pBuf:ָ
- //len:ݳ
- //ֵ,˴ζ״̬Ĵֵ
- u8 NRF24L01_Read_Buf(SPIType spiNum,u8 reg,u8 *pBuf,u8 len)
- {
- u8 status,u8_ctr;
- if(spiNum == SPI_PORT1){
- SPI1_CSN = 0; //ʹSPI
- status=SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
- for(u8_ctr=0;u8_ctr<len;u8_ctr++)pBuf[u8_ctr]=SPI_ReadWriteByte(spiNum,0XFF);//
- SPI1_CSN=1; //رSPI
- }else{
- SPI2_CSN = 0; //ʹSPI
- status=SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
- for(u8_ctr=0;u8_ctr<len;u8_ctr++)pBuf[u8_ctr]=SPI_ReadWriteByte(spiNum,0XFF);//
- SPI2_CSN=1; //رSPI
-
- }
- return status; //ض״ֵ̬
- }
-
- //ָλдָȵ
- //reg:Ĵ(λ)
- //*pBuf:ָ
- //len:ݳ
- //ֵ,˴ζ״̬Ĵֵ
- u8 NRF24L01_Write_Buf(SPIType spiNum,u8 reg, u8 *pBuf, u8 len)
- {
- u8 status,u8_ctr;
- if(spiNum == SPI_PORT1){
- SPI1_CSN = 0; //ʹSPI
- status = SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
- for(u8_ctr=0; u8_ctr<len; u8_ctr++)SPI_ReadWriteByte(spiNum,*pBuf++); //д
- SPI1_CSN = 1; //رSPI
- }else{
- SPI2_CSN = 0; //ʹSPI
- status = SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
- for(u8_ctr=0; u8_ctr<len; u8_ctr++)SPI_ReadWriteByte(spiNum,*pBuf++); //д
- SPI2_CSN = 1; //رSPI
- }
- return status; //ض״ֵ̬m
- }
-
- //******************************************************
- //
- //24L01Ƿ
- // spiNum: SPI_PORT1--SPI1, SPI_PORT2----SPI2
- //ֵ:0ɹ;1ʧ
- u8 NRF24L01_Check(SPIType spiNum)
- {
- u8 buf[5]={0XA5,0XA5,0XA5,0XA5,0XA5};
- u8 i;
-
- SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_4); //spiٶΪ9Mhz24L01SPIʱΪ10Mhz
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,buf,5);//д5ֽڵĵַ.
- NRF24L01_Read_Buf(spiNum,TX_ADDR,buf,5); //дĵַ
- for(i=0;i<5;i++)if(buf[i]!=0XA5)break;
- if(i!=5)return 1;//24L01
- return 0; //24L01
- }
-
- //*********************************************************
- //NRF24L01һ
- // spiNum: SPI_PORT1--SPI1, SPI_PORT2----SPI2
- //txbuf:ַ
- //ֵ:״
- u8 NRF24L01_TxPacket(SPIType spiNum,u8 *txbuf)
- {
- u8 sta;
- SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_4);//spiٶΪ9Mhz24L01SPIʱΪ10Mhz
- if(spiNum == SPI_PORT1){
- SPI1_CE = 0;
- }else{
- SPI2_CE=0;
- }
- NRF24L01_Write_Buf(spiNum,WR_TX_PLOAD,txbuf,TX_PLOAD_WIDTH);//дݵTX BUF 32ֽ
- if(spiNum == SPI_PORT1){ //
- SPI1_CE = 1;
- }else{
- SPI2_CE=1;
- }
- if(spiNum == SPI_PORT1){
- while(SPI1_IRQ!=0);//ȴ
- }else{
- while(SPI2_IRQ!=0);//ȴ
- }
- sta=NRF24L01_Read_Reg(spiNum,STATUS); //ȡ״̬Ĵֵ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,sta); //TX_DSMAX_RTжϱ־
- if(sta&MAX_TX)//ﵽط
- {
- NRF24L01_Write_Reg(spiNum,FLUSH_TX,0xff);//TX FIFOĴ
- return MAX_TX;
- }
- if(sta&TX_OK)//
- {
- return TX_OK;
- }
- return 0xff;//ԭʧ
- }
-
- //NRF24L01һ
- //txbuf:ַ
- //ֵ:0ɣ
- //u8 NRF24L01_RxPacket(SPIType spiNum,u8 *rxbuf)
- //{
- // u8 sta;
- // SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_8); //spiٶΪ9Mhz24L01SPIʱΪ10Mhz
- // sta=NRF24L01_Read_Reg(spiNum,STATUS); //ȡ״̬Ĵֵ
- // NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,sta); //TX_DSMAX_RTжϱ־
- // if(sta&RX_OK)//յ
- // {
- // NRF24L01_Read_Buf(spiNum,RD_RX_PLOAD,rxbuf,RX_PLOAD_WIDTH); //ȡ
- // NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- // return 0;
- // }
- // return 1;//ûյκ
- //}
- u8 NRF24L01_RxPacket(SPIType spiNum,u8 *rxbuf)
- {
- u8 sta;
- SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_8); //spiٶΪ9Mhz24L01SPIʱΪ10Mhz
- sta=NRF24L01_Read_Reg(spiNum,STATUS); //ȡ״̬Ĵֵ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,sta); //TX_DSMAX_RTжϱ־
- if(sta&RX_OK)//յ
- {
- NRF24L01_Read_Buf(spiNum,RD_RX_PLOAD,rxbuf,RX_PLOAD_WIDTH); //ȡ
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- //return 0;
- }
- //return 1;//ûյκ
- return sta;
- }
-
- //úʼNRF24L01RXģʽ
- //RXַ,дRXݿ,ѡRFƵ,ʺLNA HCURR
- //CEߺ,RXģʽ,Խ
- void NRF24L01_RX_Mode(SPIType spiNum)
- {
- if(spiNum == SPI_PORT1){
- SPI1_CE =0;
- }else{
- SPI2_CE=0;
- }
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)RX_ADDRESS,RX_ADR_WIDTH);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TX_ADDRESS,TX_ADR_WIDTH);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x01); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- // NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,RX_PLOAD_WIDTH);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x06);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
- SPI1_CE =1;
- }else{
- SPI2_CE=1;
- }
- }
-
- void NRF24L01_RX_Mode_NOACK_VCOM(SPIType spiNum) //VCOMڽ
- {
- if(spiNum == SPI_PORT1){
- SPI1_CE =0;
- }else{
- SPI2_CE=0;
- }
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)RX_ADDRESS,RX_ADR_WIDTH);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TX_ADDRESS,TX_ADR_WIDTH);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,RX_PLOAD_WIDTH);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
- SPI1_CE =1;
- }else{
- SPI2_CE=1;
- }
- }
-
- #if APP
- void NRF24L01_RX_JiangXi_CONFIG(SPIType spiNum)
- {
- #if 1
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)Jiang_Xi,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)Jiang_Xi,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x21);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- #else
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)QUAN_TONG,3);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)QUAN_TONG,3);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,6); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x0f);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- #endif
- }
- void NRF24L01_RX_TelPo_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x03);//ַ --5ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)TEL_PO,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TEL_PO,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3f); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x3f);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,40); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0b);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
-
- void NRF24L01_RX_YunNan_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x03);//ַ --5ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)YUN_NAN,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)YUN_NAN,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,16); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
- void NRF24L01_RX_GuiZhou_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)GUI_ZHOU,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)GUI_ZHOU,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3f); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
- void NRF24L01_RX_SiChuan_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SI_CHUAN,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SI_CHUAN,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
- void NRF24L01_RX_NeiMengGu_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)NEI_MENG_GU,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEI_MENG_GU,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
- void NRF24L01_RX_AnHui_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)AN_HUI,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)AN_HUI,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3F); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,26); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
-
- void NRF24L01_RX_ShanXiXinNuo_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SHAN_XI_XIN_NUO,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SHAN_XI_XIN_NUO,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,16); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,6);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
-
- void NRF24L01_RX_VCM_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)VCM,3);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)VCM,3);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,7);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
- void NRF24L01_RX_LIAO_NING_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)LIAO_NING,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)LIAO_NING,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,25); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,6);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- }
- void NRF24L01_RX_NEW_LIAO_NING_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)NEW_LIAO_NING,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEW_LIAO_NING,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,32); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x20);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
-
- void NRF24L01_RX_TP_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)TP,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TP,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,28); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_NMGYD_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)NEI_MENG_GU_YI_DONG,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEI_MENG_GU_YI_DONG,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,250Kbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x0A);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_GXYD_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)GUANG_XI_YI_DONG,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)GUANG_XI_YI_DONG,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,51); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,9);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_FJZZ_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)FU_JIAN_ZHEN_ZHUO,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)FU_JIAN_ZHEN_ZHUO,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,40); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x0c);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,6);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_SZML_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SU_ZHOU_MU_LANG,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SU_ZHOU_MU_LANG,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_CQYD_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)CHONG_QIN_YI_DONG,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)CHONG_QIN_YI_DONG,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x08);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_SXYD_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SHAN_XI_YI_DONG,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SHAN_XI_YI_DONG,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,20); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x0A);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_GSYD_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)GAN_SU_YI_DONG,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)GAN_SU_YI_DONG,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,22); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x08);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
-
- void NRF24L01_RX_XDF_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)XDF,3);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)XDF,3);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,50); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0F);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,16);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- void NRF24L01_RX_DH_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)DH,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)DH,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,51); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x07);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0F);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,5);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
-
- void NRF24L01_RX_AHDX_CONFIG(SPIType spiNum)
- {
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)ANHUI_DIANXIN,4);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)ANHUI_DIANXIN,4);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3f); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x3f);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,28); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0F);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
- }
- #endif
- #if APP
- void NRF24L01_RX_Mode_NOACK(SPIType spiNum,u8 num)
- {
- if(spiNum == SPI_PORT1){
- SPI1_CE =0;
- }else{
- SPI2_CE=0;
- }
- switch(num)
- {
- case 0:
- NRF24L01_RX_JiangXi_CONFIG(spiNum); //Э
- break;
- case 1:
- NRF24L01_RX_TelPo_CONFIG(spiNum); //첨Э
- break;
- case 2:
- NRF24L01_RX_YunNan_CONFIG(spiNum); //Э
- break;
- case 3:
- NRF24L01_RX_GuiZhou_CONFIG(spiNum); //Э
- break;
- case 4:
- NRF24L01_RX_SiChuan_CONFIG(spiNum); //ĴЭ
- break;
- case 5:
- NRF24L01_RX_NeiMengGu_CONFIG(spiNum); //ɹЭ
- break;
- case 6:
- NRF24L01_RX_AnHui_CONFIG(spiNum); //Э
- break;
- case 7:
- NRF24L01_RX_ShanXiXinNuo_CONFIG(spiNum); //ɽЭ
- break;
- case 8:
- NRF24L01_RX_VCM_CONFIG(spiNum); //ķЭ
- break;
- case 9:
- NRF24L01_RX_LIAO_NING_CONFIG(spiNum); //Э
- break;
- case 10:
- NRF24L01_RX_NEW_LIAO_NING_CONFIG(spiNum); //ƶЭ
- break;
- case 11:
- NRF24L01_RX_TP_CONFIG(spiNum); //TPרЭ
- break;
- case 12:
- NRF24L01_RX_NMGYD_CONFIG(spiNum); //ɹƶרЭ
- break;
- case 13:
- NRF24L01_RX_GXYD_CONFIG(spiNum); //ƶרЭ
- break;
- case 14:
- NRF24L01_RX_LIAO_NING_CONFIG(spiNum); //-ĴרЭ
- break;
- case 15:
- NRF24L01_RX_FJZZ_CONFIG(spiNum); //רЭ
- break;
- case 16:
- NRF24L01_RX_SZML_CONFIG(spiNum); //ľרЭ
- break;
- case 17:
- NRF24L01_RX_CQYD_CONFIG(spiNum); //ƶרЭ
- break;
- case 18:
- NRF24L01_RX_SXYD_CONFIG(spiNum); //ɽƶרЭ
- break;
- case 19:
- NRF24L01_RX_GSYD_CONFIG(spiNum); //ɽƶרЭ
- break;
- case 20:
- NRF24L01_RX_XDF_CONFIG(spiNum); //ŴרЭ
- break;
- case 21:
- NRF24L01_RX_DH_CONFIG(spiNum); //ºרЭ
- break;
- case 22:
- NRF24L01_RX_AHDX_CONFIG(spiNum); //յЭ
- break;
-
- }
- if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
- SPI1_CE =1;
- }else{
- SPI2_CE=1;
- }
- }
- #else
- void NRF24L01_RX_Mode_NOACK(SPIType spiNum)
- {
- if(spiNum == SPI_PORT1){
- SPI1_CE =0;
- }else{
- SPI2_CE=0;
- }
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)addr,5);//дRXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)addr,5);//дTXڵַ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
- NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
-
- if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
- SPI1_CE =1;
- }else{
- SPI2_CE=1;
- }
- }
- #endif
- //úʼNRF24L01TXģʽ
- //TXַ,дTXݿ,RXԶӦĵַ,TX,ѡRFƵ,ʺLNA HCURR
- //PWR_UP,CRCʹ
- //CEߺ,RXģʽ,Խ
- //CEΪߴ10us,.
- void NRF24L01_TX_Mode(SPIType spiNum)
- {
- if(spiNum == SPI_PORT1){
- SPI1_CE =0;
- }else{
- SPI2_CE=0;
- }
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TX_ADDRESS,TX_ADR_WIDTH);//дTXڵַ
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)RX_ADDRESS,RX_ADR_WIDTH); //TXڵַ,ҪΪʹACK
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x01); //ʹͨ0ԶӦ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01); //ʹͨ0Ľյַ
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_RETR,0x1a);//Զطʱ:500us + 86us;Զط:10
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨΪ40
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x00); //TX,0db,1Mbps,濪
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG,0x0e); //ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ,ж
- //CEΪ,10us
- if(spiNum == SPI_PORT1){
- SPI1_CE =1;
- }else{
- SPI2_CE=1;
- }
- }
-
- void RF24_CarrierTest(SPIType spiNum,unsigned char rf_channel)
- {
- unsigned char txAddr[32];
- unsigned char cnt;
-
- for(cnt=0;cnt<32;cnt++) txAddr[cnt] = 0xff;
-
- if(spiNum == SPI_PORT1){
- SPI1_CE =0;
- }else{
- SPI2_CE=0;
- }
-
-
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+ STATUS, 0x70);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+ CONFIG, 0x72); // RF????????¡???????12?y?TX_DS ?a, power up? CRC16?騦???
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_RETR,0);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG +RF_SETUP,0x90+00); // ??22a????騦?1|?:1dBm, ??:1Mbps
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x03);
- NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEW_LIAO_NING,5);
- NRF24L01_Write_Buf(spiNum,WR_TX_PLOAD,txAddr,32);
- NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG + RF_CH, rf_channel); // ???????騦??̨̦
-
- if(spiNum == SPI_PORT1){
- SPI1_CE =1;
- }else{
- SPI2_CE=1;
- }
- delay_5us(60); // ?a??300us
- }
-
-
-
-
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