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nrf24L01.c 43KB

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  1. #include "nrf24L01.h"
  2. #include "printf.h"
  3. #include "delay.h"
  4. const u8 TX_ADDRESS[5]={0x34,0x43,0x10,0x10,0x01}; //͵ַ
  5. const u8 RX_ADDRESS[5]={0x34,0x43,0x10,0x10,0x01};
  6. const u8 addr[5]={0x33,0x20,0x0D,0x54,0x79};
  7. const u8 Jiang_Xi[5]={0x33,0x20,0x0D,0x54,0x79};
  8. const u8 TEL_PO[5]={0x34,0x43,0x10,0x10,0x01};
  9. const u8 YUN_NAN[5]={0x01,0x10,0x10,0x43,0x34};
  10. const u8 GUI_ZHOU[5]={0x32,0x23,0xAB,0xBA,0x01};
  11. const u8 SI_CHUAN[5]={0x34,0x12,0xBB,0xAA,0x01};
  12. const u8 NEI_MENG_GU[5]={0x34,0x12,0x86,0x75,0x01};
  13. const u8 AN_HUI[5]={0x46,0x56,0x43,0x10,0x00};
  14. const u8 SHAN_XI_XIN_NUO[5]={0x34,0x6E,0x46,0x10,0x01};
  15. const u8 VCM[5]={0x34,0x43,0x10,0x10,0x01};
  16. const u8 LIAO_NING[5]={0x86,0x2c,0x95,0x01,0x01};
  17. const u8 NEW_LIAO_NING[5] = {0x36,0xE4,0xA7,0xBC,0x01};
  18. const u8 TP[5] = {0x42,0x18,0xba,0xe8,0x01};
  19. const u8 NEI_MENG_GU_YI_DONG[5]={0x34,0x12,0x86,0x75,0x01};
  20. const u8 GUANG_XI_YI_DONG[5]={0x33,0x20,0x0D,0x54,0x00};
  21. const u8 LIAO_NING_DIAN_XI[5]={0x86,0x2C,0x95,0x00,0x00};
  22. const u8 FU_JIAN_ZHEN_ZHUO[5]={0x5A,0x45,0x4E,0x4B,0x00};
  23. const u8 SU_ZHOU_MU_LANG[5]={0xAA,0xBB,0x12,0x34,0x00};
  24. const u8 CHONG_QIN_YI_DONG[5]={0x34,0x12,0xBB,0xAA,0x00};
  25. const u8 SHAN_XI_YI_DONG[5]={0x25,0x43,0x10,0x12,0x00};
  26. const u8 QUAN_TONG[5]={0xe7,0x7e,0xe3,0x00,0x00};
  27. const u8 GAN_SU_YI_DONG[5]={0x42,0x22,0xB6,0xE9,0x00};
  28. const u8 XDF[5]={0xC0,0x13,0xE3,0x00,0x00};
  29. const u8 DH[5] = {0x83,0x21,0x95,0x15,0x00};
  30. const u8 ANHUI_DIANXIN[5] = {0x41,0x15,0x43,0x12,0x00};
  31. //ʼ24L01IO
  32. void NRF24L01_Init(void)
  33. {
  34. GPIO_InitTypeDef GPIO_InitStructure;
  35. //ʹPA,B,C˿ʱ
  36. RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE);
  37. GPIO_InitStructure.GPIO_Pin = SPI1_CE_Pin; // SPI1--CE
  38. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //
  39. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  40. GPIO_Init(SPI1_CE_Port, &GPIO_InitStructure); //ʼָIO
  41. GPIO_SetBits(SPI1_CE_Port,SPI1_CE_Pin);//
  42. GPIO_InitStructure.GPIO_Pin = SPI1_CS_Pin; // SPI1--CS
  43. GPIO_Init(SPI1_CS_Port, &GPIO_InitStructure); //ʼָIO
  44. GPIO_SetBits(SPI1_CS_Port,SPI1_CS_Pin);//
  45. GPIO_InitStructure.GPIO_Pin = SPI1_IRQ_Pin; // SPI1--IRQ
  46. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; //
  47. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  48. GPIO_Init(SPI1_IRQ_Port, &GPIO_InitStructure); //ʼָIO
  49. GPIO_InitStructure.GPIO_Pin = SPI2_CE_Pin;
  50. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //
  51. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  52. GPIO_Init(SPI2_CE_Port, &GPIO_InitStructure); //ʼָIO
  53. GPIO_SetBits(SPI2_CE_Port,SPI2_CE_Pin);//
  54. GPIO_InitStructure.GPIO_Pin = SPI2_CS_Pin;
  55. GPIO_Init(SPI2_CS_Port, &GPIO_InitStructure); //ʼָIO
  56. GPIO_SetBits(SPI2_CS_Port,SPI2_CS_Pin);//
  57. GPIO_InitStructure.GPIO_Pin = SPI2_IRQ_Pin; //SPI2--IQR
  58. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; //
  59. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  60. GPIO_Init(SPI2_IRQ_Port, &GPIO_InitStructure); //ʼָIO
  61. SPI2_Init(); //ʼSPI
  62. SPI1_Init();
  63. SPI1_CE =0; //ʹ24L01
  64. SPI1_CSN=1; //SPIƬѡȡ
  65. SPI2_CE =0; //ʹ24L01
  66. SPI2_CSN=1; //SPIƬѡȡ
  67. SPI_SetSpeed(SPI_REV,SPI_BaudRatePrescaler_4);
  68. }
  69. void NRF24L01_Config(SPIType spiNum)
  70. {
  71. if(spiNum == SPI_PORT1)
  72. {
  73. SPI1_CE = 0; //chip enable
  74. SPI1_CSN = 1; //SPI disable
  75. }
  76. else
  77. {
  78. SPI2_CE = 0; //chip enable
  79. SPI2_CSN = 1; //SPI disable
  80. }
  81. }
  82. //SPIдĴ
  83. //reg:ָĴַ
  84. //value:дֵ
  85. u8 NRF24L01_Write_Reg(SPIType spiNum,u8 reg,u8 value)
  86. {
  87. u8 status;
  88. if(spiNum == SPI_PORT1){
  89. SPI1_CSN=0; //ʹSPI
  90. status =SPI_ReadWriteByte(spiNum,reg);//ͼĴ
  91. SPI_ReadWriteByte(spiNum,value); //дĴֵ
  92. SPI1_CSN=1; //ֹSPI
  93. }else{
  94. SPI2_CSN=0; //ʹSPI
  95. status =SPI_ReadWriteByte(spiNum,reg);//ͼĴ
  96. SPI_ReadWriteByte(spiNum,value); //дĴֵ
  97. SPI2_CSN=1; //ֹSPI
  98. }
  99. return(status); //״ֵ̬
  100. }
  101. //ȡSPIĴֵ
  102. //reg:ҪļĴ
  103. u8 NRF24L01_Read_Reg(SPIType spiNum,u8 reg)
  104. {
  105. u8 reg_val;
  106. if(spiNum == SPI_PORT1){
  107. SPI1_CSN = 0; //ʹSPI
  108. SPI_ReadWriteByte(spiNum,reg); //ͼĴ
  109. reg_val=SPI_ReadWriteByte(spiNum,0XFF);//ȡĴ
  110. SPI1_CSN = 1; //ֹSPI
  111. }else{
  112. SPI2_CSN = 0; //ʹSPI
  113. SPI_ReadWriteByte(spiNum,reg); //ͼĴ
  114. reg_val=SPI_ReadWriteByte(spiNum,0XFF);//ȡĴ
  115. SPI2_CSN = 1; //ֹSPI
  116. }
  117. return(reg_val); //״ֵ̬
  118. }
  119. //ָλöָȵ
  120. //reg:Ĵ(λ)
  121. //*pBuf:ָ
  122. //len:ݳ
  123. //ֵ,˴ζ״̬Ĵֵ
  124. u8 NRF24L01_Read_Buf(SPIType spiNum,u8 reg,u8 *pBuf,u8 len)
  125. {
  126. u8 status,u8_ctr;
  127. if(spiNum == SPI_PORT1){
  128. SPI1_CSN = 0; //ʹSPI
  129. status=SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
  130. for(u8_ctr=0;u8_ctr<len;u8_ctr++)pBuf[u8_ctr]=SPI_ReadWriteByte(spiNum,0XFF);//
  131. SPI1_CSN=1; //رSPI
  132. }else{
  133. SPI2_CSN = 0; //ʹSPI
  134. status=SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
  135. for(u8_ctr=0;u8_ctr<len;u8_ctr++)pBuf[u8_ctr]=SPI_ReadWriteByte(spiNum,0XFF);//
  136. SPI2_CSN=1; //رSPI
  137. }
  138. return status; //ض״ֵ̬
  139. }
  140. //ָλдָȵ
  141. //reg:Ĵ(λ)
  142. //*pBuf:ָ
  143. //len:ݳ
  144. //ֵ,˴ζ״̬Ĵֵ
  145. u8 NRF24L01_Write_Buf(SPIType spiNum,u8 reg, u8 *pBuf, u8 len)
  146. {
  147. u8 status,u8_ctr;
  148. if(spiNum == SPI_PORT1){
  149. SPI1_CSN = 0; //ʹSPI
  150. status = SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
  151. for(u8_ctr=0; u8_ctr<len; u8_ctr++)SPI_ReadWriteByte(spiNum,*pBuf++); //д
  152. SPI1_CSN = 1; //رSPI
  153. }else{
  154. SPI2_CSN = 0; //ʹSPI
  155. status = SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬
  156. for(u8_ctr=0; u8_ctr<len; u8_ctr++)SPI_ReadWriteByte(spiNum,*pBuf++); //д
  157. SPI2_CSN = 1; //رSPI
  158. }
  159. return status; //ض״ֵ̬m
  160. }
  161. //******************************************************
  162. //
  163. //24L01Ƿ
  164. // spiNum: SPI_PORT1--SPI1, SPI_PORT2----SPI2
  165. //ֵ:0ɹ;1ʧ
  166. u8 NRF24L01_Check(SPIType spiNum)
  167. {
  168. u8 buf[5]={0XA5,0XA5,0XA5,0XA5,0XA5};
  169. u8 i;
  170. SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_4); //spiٶΪ9Mhz24L01SPIʱΪ10Mhz
  171. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,buf,5);//д5ֽڵĵַ.
  172. NRF24L01_Read_Buf(spiNum,TX_ADDR,buf,5); //дĵַ
  173. for(i=0;i<5;i++)if(buf[i]!=0XA5)break;
  174. if(i!=5)return 1;//24L01
  175. return 0; //⵽24L01
  176. }
  177. //*********************************************************
  178. //NRF24L01һ
  179. // spiNum: SPI_PORT1--SPI1, SPI_PORT2----SPI2
  180. //txbuf:׵ַ
  181. //ֵ:״
  182. u8 NRF24L01_TxPacket(SPIType spiNum,u8 *txbuf)
  183. {
  184. u8 sta;
  185. SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_4);//spiٶΪ9Mhz24L01SPIʱΪ10Mhz
  186. if(spiNum == SPI_PORT1){
  187. SPI1_CE = 0;
  188. }else{
  189. SPI2_CE=0;
  190. }
  191. NRF24L01_Write_Buf(spiNum,WR_TX_PLOAD,txbuf,TX_PLOAD_WIDTH);//дݵTX BUF 32ֽ
  192. if(spiNum == SPI_PORT1){ //
  193. SPI1_CE = 1;
  194. }else{
  195. SPI2_CE=1;
  196. }
  197. if(spiNum == SPI_PORT1){
  198. while(SPI1_IRQ!=0);//ȴ
  199. }else{
  200. while(SPI2_IRQ!=0);//ȴ
  201. }
  202. sta=NRF24L01_Read_Reg(spiNum,STATUS); //ȡ״̬Ĵֵ
  203. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,sta); //TX_DSMAX_RTжϱ־
  204. if(sta&MAX_TX)//ﵽط
  205. {
  206. NRF24L01_Write_Reg(spiNum,FLUSH_TX,0xff);//TX FIFOĴ
  207. return MAX_TX;
  208. }
  209. if(sta&TX_OK)//
  210. {
  211. return TX_OK;
  212. }
  213. return 0xff;//ԭʧ
  214. }
  215. //NRF24L01һ
  216. //txbuf:׵ַ
  217. //ֵ:0ɣ
  218. //u8 NRF24L01_RxPacket(SPIType spiNum,u8 *rxbuf)
  219. //{
  220. // u8 sta;
  221. // SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_8); //spiٶΪ9Mhz24L01SPIʱΪ10Mhz
  222. // sta=NRF24L01_Read_Reg(spiNum,STATUS); //ȡ״̬Ĵֵ
  223. // NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,sta); //TX_DSMAX_RTжϱ־
  224. // if(sta&RX_OK)//յ
  225. // {
  226. // NRF24L01_Read_Buf(spiNum,RD_RX_PLOAD,rxbuf,RX_PLOAD_WIDTH); //ȡ
  227. // NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  228. // return 0;
  229. // }
  230. // return 1;//ûյκ
  231. //}
  232. u8 NRF24L01_RxPacket(SPIType spiNum,u8 *rxbuf)
  233. {
  234. u8 sta;
  235. SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_8); //spiٶΪ9Mhz24L01SPIʱΪ10Mhz
  236. sta=NRF24L01_Read_Reg(spiNum,STATUS); //ȡ״̬Ĵֵ
  237. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,sta); //TX_DSMAX_RTжϱ־
  238. if(sta&RX_OK)//յ
  239. {
  240. NRF24L01_Read_Buf(spiNum,RD_RX_PLOAD,rxbuf,RX_PLOAD_WIDTH); //ȡ
  241. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  242. //return 0;
  243. }
  244. //return 1;//ûյκ
  245. return sta;
  246. }
  247. //úʼNRF24L01RXģʽ
  248. //RXַ,дRXݿ,ѡRFƵ,ʺLNA HCURR
  249. //CEߺ,RXģʽ,Խ
  250. void NRF24L01_RX_Mode(SPIType spiNum)
  251. {
  252. if(spiNum == SPI_PORT1){
  253. SPI1_CE =0;
  254. }else{
  255. SPI2_CE=0;
  256. }
  257. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
  258. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)RX_ADDRESS,RX_ADR_WIDTH);//дRXڵַ
  259. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TX_ADDRESS,TX_ADR_WIDTH);//дTXڵַ
  260. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x01); //ʹͨ0ԶӦ
  261. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  262. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨƵ
  263. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  264. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  265. // NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,RX_PLOAD_WIDTH);//ѡͨ0Чݿ
  266. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x06);
  267. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
  268. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  269. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  270. if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
  271. SPI1_CE =1;
  272. }else{
  273. SPI2_CE=1;
  274. }
  275. }
  276. void NRF24L01_RX_Mode_NOACK_VCOM(SPIType spiNum) //VCOMڽ
  277. {
  278. if(spiNum == SPI_PORT1){
  279. SPI1_CE =0;
  280. }else{
  281. SPI2_CE=0;
  282. }
  283. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
  284. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)RX_ADDRESS,RX_ADR_WIDTH);//дRXڵַ
  285. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TX_ADDRESS,TX_ADR_WIDTH);//дTXڵַ
  286. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  287. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  288. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨƵ
  289. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  290. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  291. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,RX_PLOAD_WIDTH);//ѡͨ0Чݿ
  292. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
  293. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
  294. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  295. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  296. if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
  297. SPI1_CE =1;
  298. }else{
  299. SPI2_CE=1;
  300. }
  301. }
  302. #if APP
  303. void NRF24L01_RX_JiangXi_CONFIG(SPIType spiNum)
  304. {
  305. #if 1
  306. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  307. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)Jiang_Xi,5);//дRXڵַ
  308. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)Jiang_Xi,5);//дTXڵַ
  309. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  310. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  311. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  312. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x21);//TX,0db,1Mbps,濪
  313. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  314. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  315. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
  316. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
  317. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  318. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  319. #else
  320. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
  321. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)QUAN_TONG,3);//дRXڵַ
  322. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)QUAN_TONG,3);//дTXڵַ
  323. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  324. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  325. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,6); //RFͨƵ
  326. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x0f);//TX,0db,1Mbps,濪
  327. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  328. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  329. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
  330. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
  331. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  332. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  333. #endif
  334. }
  335. void NRF24L01_RX_TelPo_CONFIG(SPIType spiNum)
  336. {
  337. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x03);//ַ --5ֽ
  338. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)TEL_PO,5);//дRXڵַ
  339. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TEL_PO,5);//дTXڵַ
  340. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3f); //ʹͨ0ԶӦ
  341. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x3f);//ʹͨ0Ľյַ
  342. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,40); //RFͨƵ
  343. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  344. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0b);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  345. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  346. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  347. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  348. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  349. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  350. }
  351. void NRF24L01_RX_YunNan_CONFIG(SPIType spiNum)
  352. {
  353. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x03);//ַ --5ֽ
  354. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)YUN_NAN,5);//дRXڵַ
  355. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)YUN_NAN,5);//дTXڵַ
  356. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  357. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  358. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,16); //RFͨƵ
  359. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  360. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  361. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  362. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  363. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  364. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  365. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  366. }
  367. void NRF24L01_RX_GuiZhou_CONFIG(SPIType spiNum)
  368. {
  369. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  370. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)GUI_ZHOU,5);//дRXڵַ
  371. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)GUI_ZHOU,5);//дTXڵַ
  372. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3f); //ʹͨ0ԶӦ
  373. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  374. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  375. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  376. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  377. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  378. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  379. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  380. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  381. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  382. }
  383. void NRF24L01_RX_SiChuan_CONFIG(SPIType spiNum)
  384. {
  385. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  386. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SI_CHUAN,5);//дRXڵַ
  387. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SI_CHUAN,5);//дTXڵַ
  388. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  389. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  390. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  391. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
  392. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  393. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
  394. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  395. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  396. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  397. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  398. }
  399. void NRF24L01_RX_NeiMengGu_CONFIG(SPIType spiNum)
  400. {
  401. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  402. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)NEI_MENG_GU,5);//дRXڵַ
  403. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEI_MENG_GU,5);//дTXڵַ
  404. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  405. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  406. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  407. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
  408. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  409. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  410. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  411. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  412. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  413. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  414. }
  415. void NRF24L01_RX_AnHui_CONFIG(SPIType spiNum)
  416. {
  417. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  418. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)AN_HUI,5);//дRXڵַ
  419. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)AN_HUI,5);//дTXڵַ
  420. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3F); //ʹͨ0ԶӦ
  421. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  422. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,26); //RFͨƵ
  423. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
  424. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  425. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  426. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  427. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  428. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  429. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  430. }
  431. void NRF24L01_RX_ShanXiXinNuo_CONFIG(SPIType spiNum)
  432. {
  433. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
  434. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SHAN_XI_XIN_NUO,5);//дRXڵַ
  435. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SHAN_XI_XIN_NUO,5);//дTXڵַ
  436. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  437. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  438. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,16); //RFͨƵ
  439. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  440. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  441. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,6);//ѡͨ0Чݿ
  442. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  443. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  444. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  445. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  446. }
  447. void NRF24L01_RX_VCM_CONFIG(SPIType spiNum)
  448. {
  449. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
  450. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)VCM,3);//дRXڵַ
  451. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)VCM,3);//дTXڵַ
  452. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  453. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  454. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨƵ
  455. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  456. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  457. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,7);//ѡͨ0Чݿ
  458. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
  459. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
  460. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  461. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  462. }
  463. void NRF24L01_RX_LIAO_NING_CONFIG(SPIType spiNum)
  464. {
  465. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
  466. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)LIAO_NING,5);//дRXڵַ
  467. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)LIAO_NING,5);//дTXڵַ
  468. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  469. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  470. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,25); //RFͨƵ
  471. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  472. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  473. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,6);//ѡͨ0Чݿ
  474. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  475. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  476. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  477. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  478. }
  479. void NRF24L01_RX_NEW_LIAO_NING_CONFIG(SPIType spiNum)
  480. {
  481. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  482. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)NEW_LIAO_NING,4);//дRXڵַ
  483. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEW_LIAO_NING,4);//дTXڵַ
  484. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  485. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  486. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,32); //RFͨƵ
  487. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x20);//TX,0db,1Mbps,濪
  488. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  489. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
  490. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  491. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  492. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  493. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  494. }
  495. void NRF24L01_RX_TP_CONFIG(SPIType spiNum)
  496. {
  497. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  498. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)TP,4);//дRXڵַ
  499. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TP,4);//дTXڵַ
  500. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  501. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  502. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,28); //RFͨƵ
  503. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
  504. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  505. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
  506. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  507. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  508. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  509. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  510. }
  511. void NRF24L01_RX_NMGYD_CONFIG(SPIType spiNum)
  512. {
  513. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  514. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)NEI_MENG_GU_YI_DONG,4);//дRXڵַ
  515. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEI_MENG_GU_YI_DONG,4);//дTXڵַ
  516. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  517. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  518. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  519. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,250Kbps,濪
  520. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  521. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x0A);//ѡͨ0Чݿ
  522. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  523. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  524. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  525. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  526. }
  527. void NRF24L01_RX_GXYD_CONFIG(SPIType spiNum)
  528. {
  529. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  530. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)GUANG_XI_YI_DONG,4);//дRXڵַ
  531. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)GUANG_XI_YI_DONG,4);//дTXڵַ
  532. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  533. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  534. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,51); //RFͨƵ
  535. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  536. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  537. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,9);//ѡͨ0Чݿ
  538. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  539. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  540. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  541. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  542. }
  543. void NRF24L01_RX_FJZZ_CONFIG(SPIType spiNum)
  544. {
  545. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  546. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)FU_JIAN_ZHEN_ZHUO,4);//дRXڵַ
  547. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)FU_JIAN_ZHEN_ZHUO,4);//дTXڵַ
  548. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  549. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  550. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,40); //RFͨƵ
  551. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x0c);//TX,0db,1Mbps,濪
  552. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  553. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,6);//ѡͨ0Чݿ
  554. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  555. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  556. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  557. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  558. }
  559. void NRF24L01_RX_SZML_CONFIG(SPIType spiNum)
  560. {
  561. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  562. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SU_ZHOU_MU_LANG,4);//дRXڵַ
  563. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SU_ZHOU_MU_LANG,4);//дTXڵַ
  564. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  565. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  566. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  567. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
  568. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  569. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,8);//ѡͨ0Чݿ
  570. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  571. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  572. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  573. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  574. }
  575. void NRF24L01_RX_CQYD_CONFIG(SPIType spiNum)
  576. {
  577. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  578. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)CHONG_QIN_YI_DONG,4);//дRXڵַ
  579. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)CHONG_QIN_YI_DONG,4);//дTXڵַ
  580. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  581. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  582. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  583. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
  584. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  585. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x08);//ѡͨ0Чݿ
  586. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  587. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  588. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  589. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  590. }
  591. void NRF24L01_RX_SXYD_CONFIG(SPIType spiNum)
  592. {
  593. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  594. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)SHAN_XI_YI_DONG,4);//дRXڵַ
  595. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)SHAN_XI_YI_DONG,4);//дTXڵַ
  596. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  597. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  598. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,20); //RFͨƵ
  599. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  600. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  601. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x0A);//ѡͨ0Чݿ
  602. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  603. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  604. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  605. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  606. }
  607. void NRF24L01_RX_GSYD_CONFIG(SPIType spiNum)
  608. {
  609. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  610. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)GAN_SU_YI_DONG,4);//дRXڵַ
  611. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)GAN_SU_YI_DONG,4);//дTXڵַ
  612. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  613. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  614. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,22); //RFͨƵ
  615. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  616. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  617. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,0x08);//ѡͨ0Чݿ
  618. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  619. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  620. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  621. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  622. }
  623. void NRF24L01_RX_XDF_CONFIG(SPIType spiNum)
  624. {
  625. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --4ֽ
  626. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)XDF,3);//дRXڵַ
  627. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)XDF,3);//дTXڵַ
  628. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  629. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  630. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,50); //RFͨƵ
  631. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  632. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0F);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  633. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,16);//ѡͨ0Чݿ
  634. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  635. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  636. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  637. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  638. }
  639. void NRF24L01_RX_DH_CONFIG(SPIType spiNum)
  640. {
  641. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  642. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)DH,4);//дRXڵַ
  643. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)DH,4);//дTXڵַ
  644. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  645. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  646. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,51); //RFͨƵ
  647. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x07);//TX,0db,1Mbps,濪
  648. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0F);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  649. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,5);//ѡͨ0Чݿ
  650. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  651. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  652. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  653. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  654. }
  655. void NRF24L01_RX_AHDX_CONFIG(SPIType spiNum)
  656. {
  657. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  658. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)ANHUI_DIANXIN,4);//дRXڵַ
  659. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)ANHUI_DIANXIN,4);//дTXڵַ
  660. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x3f); //ʹͨ0ԶӦ
  661. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x3f);//ʹͨ0Ľյַ
  662. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,28); //RFͨƵ
  663. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x04);//TX,0db,1Mbps,濪
  664. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0F);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  665. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  666. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x01);
  667. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x00); /// P0
  668. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  669. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  670. }
  671. #endif
  672. #if APP
  673. void NRF24L01_RX_Mode_NOACK(SPIType spiNum,u8 num)
  674. {
  675. if(spiNum == SPI_PORT1){
  676. SPI1_CE =0;
  677. }else{
  678. SPI2_CE=0;
  679. }
  680. switch(num)
  681. {
  682. case 0:
  683. NRF24L01_RX_JiangXi_CONFIG(spiNum); //Э
  684. break;
  685. case 1:
  686. NRF24L01_RX_TelPo_CONFIG(spiNum); //첨Э
  687. break;
  688. case 2:
  689. NRF24L01_RX_YunNan_CONFIG(spiNum); //Э
  690. break;
  691. case 3:
  692. NRF24L01_RX_GuiZhou_CONFIG(spiNum); //Э
  693. break;
  694. case 4:
  695. NRF24L01_RX_SiChuan_CONFIG(spiNum); //ĴЭ
  696. break;
  697. case 5:
  698. NRF24L01_RX_NeiMengGu_CONFIG(spiNum); //ɹЭ
  699. break;
  700. case 6:
  701. NRF24L01_RX_AnHui_CONFIG(spiNum); //Э
  702. break;
  703. case 7:
  704. NRF24L01_RX_ShanXiXinNuo_CONFIG(spiNum); //ɽЭ
  705. break;
  706. case 8:
  707. NRF24L01_RX_VCM_CONFIG(spiNum); //ķЭ
  708. break;
  709. case 9:
  710. NRF24L01_RX_LIAO_NING_CONFIG(spiNum); //Э
  711. break;
  712. case 10:
  713. NRF24L01_RX_NEW_LIAO_NING_CONFIG(spiNum); //ƶЭ
  714. break;
  715. case 11:
  716. NRF24L01_RX_TP_CONFIG(spiNum); //TPרЭ
  717. break;
  718. case 12:
  719. NRF24L01_RX_NMGYD_CONFIG(spiNum); //ɹƶרЭ
  720. break;
  721. case 13:
  722. NRF24L01_RX_GXYD_CONFIG(spiNum); //ƶרЭ
  723. break;
  724. case 14:
  725. NRF24L01_RX_LIAO_NING_CONFIG(spiNum); //-ĴרЭ
  726. break;
  727. case 15:
  728. NRF24L01_RX_FJZZ_CONFIG(spiNum); //רЭ
  729. break;
  730. case 16:
  731. NRF24L01_RX_SZML_CONFIG(spiNum); //ľרЭ
  732. break;
  733. case 17:
  734. NRF24L01_RX_CQYD_CONFIG(spiNum); //ƶרЭ
  735. break;
  736. case 18:
  737. NRF24L01_RX_SXYD_CONFIG(spiNum); //ɽƶרЭ
  738. break;
  739. case 19:
  740. NRF24L01_RX_GSYD_CONFIG(spiNum); //ɽƶרЭ
  741. break;
  742. case 20:
  743. NRF24L01_RX_XDF_CONFIG(spiNum); //ŴרЭ
  744. break;
  745. case 21:
  746. NRF24L01_RX_DH_CONFIG(spiNum); //ºרЭ
  747. break;
  748. case 22:
  749. NRF24L01_RX_AHDX_CONFIG(spiNum); //յЭ
  750. break;
  751. }
  752. if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
  753. SPI1_CE =1;
  754. }else{
  755. SPI2_CE=1;
  756. }
  757. }
  758. #else
  759. void NRF24L01_RX_Mode_NOACK(SPIType spiNum)
  760. {
  761. if(spiNum == SPI_PORT1){
  762. SPI1_CE =0;
  763. }else{
  764. SPI2_CE=0;
  765. }
  766. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x02);//ַ --4ֽ
  767. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)addr,5);//дRXڵַ
  768. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)addr,5);//дTXڵַ
  769. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30); //ʹͨ0ԶӦ
  770. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//ʹͨ0Ľյַ
  771. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,18); //RFͨƵ
  772. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x24);//TX,0db,1Mbps,濪
  773. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, 0x0f);//ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ
  774. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,10);//ѡͨ0Чݿ
  775. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,0x00);
  776. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,0x01); /// P0
  777. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70); //TX_DSMAX_RTжϱ־
  778. NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff); //RX FIFOĴ
  779. if(spiNum == SPI_PORT1){ //CEΪ,ģʽ
  780. SPI1_CE =1;
  781. }else{
  782. SPI2_CE=1;
  783. }
  784. }
  785. #endif
  786. //úʼNRF24L01TXģʽ
  787. //TXַ,дTXݿ,RXԶӦĵַ,TX,ѡRFƵ,ʺLNA HCURR
  788. //PWR_UP,CRCʹ
  789. //CEߺ,RXģʽ,Խ
  790. //CEΪߴ10us,.
  791. void NRF24L01_TX_Mode(SPIType spiNum)
  792. {
  793. if(spiNum == SPI_PORT1){
  794. SPI1_CE =0;
  795. }else{
  796. SPI2_CE=0;
  797. }
  798. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x01);//ַ --3ֽ
  799. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)TX_ADDRESS,TX_ADR_WIDTH);//дTXڵַ
  800. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)RX_ADDRESS,RX_ADR_WIDTH); //TXڵַ,ҪΪʹACK
  801. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x01); //ʹͨ0ԶӦ
  802. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01); //ʹͨ0Ľյַ
  803. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_RETR,0x1a);//Զطʱ:500us + 86us;Զط:10
  804. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,42); //RFͨΪ40
  805. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,0x00); //TX,0db,1Mbps,濪
  806. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG,0x0e); //ûģʽIJ;PWR_UP,EN_CRC,16BIT_CRC,ģʽ,ж
  807. //CEΪ,10us
  808. if(spiNum == SPI_PORT1){
  809. SPI1_CE =1;
  810. }else{
  811. SPI2_CE=1;
  812. }
  813. }
  814. void RF24_CarrierTest(SPIType spiNum,unsigned char rf_channel)
  815. {
  816. unsigned char txAddr[32];
  817. unsigned char cnt;
  818. for(cnt=0;cnt<32;cnt++) txAddr[cnt] = 0xff;
  819. if(spiNum == SPI_PORT1){
  820. SPI1_CE =0;
  821. }else{
  822. SPI2_CE=0;
  823. }
  824. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+ STATUS, 0x70);
  825. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+ CONFIG, 0x72); // RF????????¡???????12?y?TX_DS ?a, power up? CRC16?騦??꨺?
  826. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,0x30);
  827. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0);
  828. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_RETR,0);
  829. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG +RF_SETUP,0x90+00); // ??22a????騦?1|?:1dBm, ??:1Mbps
  830. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,0x03);
  831. NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)NEW_LIAO_NING,5);
  832. NRF24L01_Write_Buf(spiNum,WR_TX_PLOAD,txAddr,32);
  833. NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG + RF_CH, rf_channel); // ???????騦??̨̦
  834. if(spiNum == SPI_PORT1){
  835. SPI1_CE =1;
  836. }else{
  837. SPI2_CE=1;
  838. }
  839. delay_5us(60); // ?a??300us
  840. }