commit cec8ffabff8c467acdf01b0a5f81e87096b417c2 Author: zhan <452019448@qq.com> Date: Mon Nov 8 09:51:24 2021 +0800 增加2.4G对比工具代码，版本号为V2.4 diff --git a/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c b/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c new file mode 100644 index 0000000..fcff0d1 --- /dev/null +++ b/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h b/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h new file mode 100644 index 0000000..7ab7b4b --- /dev/null +++ b/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html b/Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html new file mode 100644 index 0000000..f0cb0da --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html @@ -0,0 +1,266 @@ + + + + + + + + + +Release Notes for STM32F10x CMSIS + + + + +
+


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Release +Notes for STM32F10x CMSIS

+

Copyright 2010 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F10x CMSIS +update History

+

3.4.0 +- 10/15/2010

+ +
    +
  1. General
    2. +
+ +
    +
  • Add support +for STM32F10x High-density Value line devices.
    • +
+
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. +
+ + + +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
        • +
      • RCC, AFIO, FSMC bits definition updated
        • +
      +
    • + + All +STM32 devices definitions are commented by default. User has to select the +appropriate device before starting else an error will be signaled on compile +time.
      • +
    • Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
      • +
    • "bool" type removed.
      +
      • +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
      +
      • +
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
      • +
    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" +to select if the user want to place the Vector Table in internal SRAM. +An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
      +
      • + +
    +
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three +startup files for STM32 High-density Value line devices: + startup_stm32f10x_hd_vl.s
    +
+

3.3.0 +- 04/16/2010

+ +
  1. General
+
  • Add support +for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer
+ +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
      +
  • STM32F10x CMSIS startup files:
    • add three +startup files for STM32 XL-density devices: + startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • +
  • Directory structure updated to be aligned with CMSIS V1.30
    +
    • +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices. 
    • + +
+
    +
  1. CMSIS Core Peripheral Access Layer
+ +
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. + +
+ +
    + +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • +
      +
    • Update +the stm32f10x.h file to support new Value line devices features: CEC +peripheral, new General purpose timers TIM15, TIM16 and TIM17.
      • +
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      +
      • +
    • HSE_Value, +HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, +HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy +purposes.
      +
      • +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • SystemFrequency variable name changed to SystemCoreClock
      +
      • +
    • Default + SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
      +
      • +
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      +
      • +
    • Additional function void SystemCoreClockUpdate (void) is provided.
      +
      • +
    +
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • +
      +
    • Add new +startup files for STM32 Low-density Value line devices: + startup_stm32f10x_ld_vl.s
      • +
    • Add new startup +files for STM32 Medium-density Value line devices: + startup_stm32f10x_md_vl.s
      • +
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      +To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
      +
      • +
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      +
      • +
    + +
+ +
    +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s new file mode 100644 index 0000000..f56aca9 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s @@ -0,0 +1,472 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Connectivity line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x Connectivity line Devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s new file mode 100644 index 0000000..acd699e --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s @@ -0,0 +1,468 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x High Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Configure external SRAM mounted on STM3210E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..c1aa04f --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s @@ -0,0 +1,452 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x High Density Value Line Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Configure external SRAM mounted on STM32100E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word FSMC_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density Value line devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s new file mode 100644 index 0000000..750e958 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s @@ -0,0 +1,346 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Low Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Low Density devices.*/ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..b545c5d --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s @@ -0,0 +1,391 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s new file mode 100644 index 0000000..c9438d4 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s @@ -0,0 +1,362 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..f6d71ea --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s @@ -0,0 +1,406 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s new file mode 100644 index 0000000..4d8a006 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s @@ -0,0 +1,466 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM9_IRQHandler + .word TIM1_UP_TIM10_IRQHandler + .word TIM1_TRG_COM_TIM11_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_TIM12_IRQHandler + .word TIM8_UP_TIM13_IRQHandler + .word TIM8_TRG_COM_TIM14_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x XL-Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s new file mode 100644 index 0000000..17a5e59 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s @@ -0,0 +1,368 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s new file mode 100644 index 0000000..caf0f41 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s @@ -0,0 +1,358 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x High Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..d315c69 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s @@ -0,0 +1,348 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd_vl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x High Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM32100E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FSMC_IRQHandler ; FSMC + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +FSMC_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler +DMA2_Channel5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s new file mode 100644 index 0000000..9e8ac7b --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s @@ -0,0 +1,297 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Low Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..a565fb3 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s @@ -0,0 +1,304 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s new file mode 100644 index 0000000..eb5eb1a --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s @@ -0,0 +1,307 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..3b52ff7 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s @@ -0,0 +1,315 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s new file mode 100644 index 0000000..2f620a6 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s @@ -0,0 +1,358 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_xl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s new file mode 100644 index 0000000..55dd603 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s @@ -0,0 +1,467 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x Connectivity line Devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s new file mode 100644 index 0000000..0b392ad --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s @@ -0,0 +1,464 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..81ab8b4 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s @@ -0,0 +1,444 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM32100E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word FSMC_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density Value line devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s new file mode 100644 index 0000000..a5e0e12 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Low Density devices.*/ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..954b424 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Low Density Value Line devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s new file mode 100644 index 0000000..ea1ec05 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..111ab07 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s @@ -0,0 +1,398 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s new file mode 100644 index 0000000..9fd3e22 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s @@ -0,0 +1,464 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM9_IRQHandler + .word TIM1_UP_TIM10_IRQHandler + .word TIM1_TRG_COM_TIM11_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_TIM12_IRQHandler + .word TIM8_UP_TIM13_IRQHandler + .word TIM8_TRG_COM_TIM14_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x XL Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s new file mode 100644 index 0000000..7b61465 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s @@ -0,0 +1,507 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Connectivity line devices vector table for +;* EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s new file mode 100644 index 0000000..dcc5f29 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s @@ -0,0 +1,496 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x High Density Devices vector table for EWARM5.x +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR address, +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..31b2493 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s @@ -0,0 +1,466 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd_vl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x High Density Value Line Devices vector table +;* for EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM32100E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FSMC_IRQHandler ; FSMC + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s new file mode 100644 index 0000000..2d32918 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s @@ -0,0 +1,366 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Low Density Devices vector table for EWARM5.x +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..560ae9a --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s @@ -0,0 +1,369 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s new file mode 100644 index 0000000..0cc543d --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s @@ -0,0 +1,391 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Medium Density Devices vector table for +;* EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..197961b --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s @@ -0,0 +1,394 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s new file mode 100644 index 0000000..84b5f6d --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s @@ -0,0 +1,496 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_xl.s +;* Author : MCD Application Team +;* Version : V3.4.0 +;* Date : 10/15/2010 +;* Description : STM32F10x XL-Density Devices vector table for EWARM5.x +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR address, +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h new file mode 100644 index 0000000..4df1f24 --- /dev/null +++ b/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h @@ -0,0 +1,8319 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, + * High density, High density value line, Medium density, + * Medium density Value line, Low density, Low density Value line + * and XL-density devices. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + #define STM32F10X_HD /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ + /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ + | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ + | __STM32F10X_STDPERIPH_VERSION_SUB2) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is + mapped at postion 60 only if the MISC_REMAP bit in + the AFIO_MAPR2 register is set) */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_HD_VL + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_HD_VL +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ +#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ +#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!
© COPYRIGHT 2010 STMicroelectronics
+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/CMSIS debug support.htm b/Libraries/CMSIS/CMSIS debug support.htm new file mode 100644 index 0000000..36e0446 --- /dev/null +++ b/Libraries/CMSIS/CMSIS debug support.htm @@ -0,0 +1,243 @@ + + + +CMSIS Debug Support + + + + + + + + +

CMSIS Debug Support

+ +
+ +

Cortex-M3 ITM Debug Access

+

+ The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with + the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has + 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM + communication channels are used by CMSIS to output the following information: +

+
    +
  • ITM Channel 0: used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for RTOS kernel awareness debugging.
    • +
+ +

Debug IN / OUT functions

+

CMSIS provides following debug functions:

+
    +
  • ITM_SendChar (uses ITM channel 0)
    • +
  • ITM_ReceiveChar (uses global variable)
    • +
  • ITM_CheckChar (uses global variable)
    • +
+ +

ITM_SendChar

+

+ ITM_SendChar is used to transmit a character over ITM channel 0 from + the microcontroller system to the debug system.
+ Only a 8 bit value is transmitted. +

+
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  /* check if debugger connected and ITM channel enabled for tracing */
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&
+      (ITM->TER & (1UL << 0))  ) 
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }  
+  return (ch);
+}
+ +

ITM_ReceiveChar

+

+ ITM communication channel is only capable for OUT direction. For IN direction + a globel variable is used. A simple mechansim detects if a character is received. + The project to test need to be build with debug information. +

+ +

+ The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system + to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake. +

+
+extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */
+
+

+ A dedicated bit pattern is used to determin if ITM_RxBuffer is empty + or contains a valid value. +

+
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+
+

+ ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking. + It returns the received character or '-1' if no character was available. +

+
+static __INLINE int ITM_ReceiveChar (void) {
+  int ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+
+ +

ITM_CheckChar

+

+ ITM_CheckChar is used to check if a character is received. +

+
+static __INLINE int ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+ + +

ITM Debug Support in uVision

+

+ uVision uses in a debug session the Debug (printf) Viewer window to + display the debug data. +

+

Direction microcontroller system -> uVision:

+
    +
  • + Characters received via ITM communication channel 0 are written in a printf style + to Debug (printf) Viewer window. +
    • +
+ +

Direction uVision -> microcontroller system:

+
    +
  • Check if ITM_RxBuffer variable is available (only performed once).
    • +
  • Read character from Debug (printf) Viewer window.
    • +
  • If ITM_RxBuffer empty write character to ITM_RxBuffer.
    • +
+ +

Note

+
    +

  • Current solution does not use a buffer machanism for trasmitting the characters.

    +
    • +
+ +

RTX Kernel awareness in uVision

+

+ uVision / RTX are using a simple and efficient solution for RTX Kernel awareness. + No format overhead is necessary.
+ uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access + to ITM communication channel 31. +

+ +

Following RTX events are traced:

+
    +
  • Task Create / Delete event +
      +
    1. 32 bit access. Task start address is transmitted
      2. +
    2. 16 bit access. Task ID and Create/Delete flag are transmitted
      + High byte holds Create/Delete flag, Low byte holds TASK ID. +
      3. +
    +
    • +
  • Task switch event +
      +
    1. 8 bit access. Task ID of current task is transmitted
      2. +
    +
    • +
+ +

Note

+
    +

  • Other RTOS information could be retrieved via memory read access in a polling mode manner.

    +
    • +
+ + +

 

+ +
+ +

Copyright KEIL - An ARM Company.
+All rights reserved.
+Visit our web site at www.keil.com. +

+ + + + \ No newline at end of file diff --git a/Libraries/CMSIS/CMSIS_changes.htm b/Libraries/CMSIS/CMSIS_changes.htm new file mode 100644 index 0000000..5a17f1a --- /dev/null +++ b/Libraries/CMSIS/CMSIS_changes.htm @@ -0,0 +1,320 @@ + + + +CMSIS Changes + + + + + + + + +

Changes to CMSIS version V1.20

+ +
+ +

1. Removed CMSIS Middelware packages

+

+ CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. +

+ +

2. SystemFrequency renamed to SystemCoreClock

+

+ The variable name SystemCoreClock is more precise than SystemFrequency + because the variable holds the clock value at which the core is running. +

+ +

3. Changed startup concept

+

+ The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit + from main) has the weakness that it does not work for controllers which need a already + configuerd clock system to configure the external memory controller. +

+ +

Changed startup concept

+
    +
  • + SystemInit() is called from startup file before premain. +
    • +
  • + SystemInit() configures the clock system and also configures + an existing external memory controller. +
    • +
  • + SystemInit() must not use global variables. +
    • +
  • + SystemCoreClock is initialized with a correct predefined value. +
    • +
  • + Additional function void SystemCoreClockUpdate (void) is provided.
    + SystemCoreClockUpdate() updates the variable SystemCoreClock + and must be called whenever the core clock is changed.
    + SystemCoreClockUpdate() evaluates the clock register settings and calculates + the current core clock. +
    • +
+ + +

4. Advanced Debug Functions

+

+ ITM communication channel is only capable for OUT direction. To allow also communication for + IN direction a simple concept is provided. +

+
    +
  • + Global variable volatile int ITM_RxBuffer used for IN data. +
    • +
  • + Function int ITM_CheckChar (void) checks if a new character is available. +
    • +
  • + Function int ITM_ReceiveChar (void) retrieves the new character. +
    • +
+ +

+ For detailed explanation see file CMSIS debug support.htm. +

+ + +

5. Core Register Bit Definitions

+

+ Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the + defines correspond with the Cortex-M Technical Reference Manual. +

+

+ e.g. SysTick structure with bit definitions +

+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+  memory mapped structure for SysTick
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+ +

7. DoxyGen Tags

+

+ DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation + using DoxyGen. +

+ +

8. Folder Structure

+

+ The folder structure is changed to differentiate the single support packages. +

+ +
    +
  • CM0
    • +
  • CM3 +
      +
    • CoreSupport
      • +
    • DeviceSupport
      • +
        +
      • Vendor +
          +
        • Device +
            +
          • Startup +
              +
            • Toolchain
              • +
            • Toolchain
              • +
            • ...
              • +
            +
            • +
          +
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Vendor
        • +
      • ...
        • +
      + +
    • Example +
        +
      • Toolchain +
          +
        • Device
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Toolchain
        • +
      • ...
        • +
      +
      • +
    +
    • + +
  • Documentation
    • +
+ +

9. Open Points

+

+ Following points need to be clarified and solved: +

+
    +
  • +

    + Equivalent C and Assembler startup files. +

    +

    + Is there a need for having C startup files although assembler startup files are + very efficient and do not need to be changed? +

    +

    • +
  • +

    + Placing of HEAP in external RAM. +

    +

    + It must be possible to place HEAP in external RAM if the device supports an + external memory controller. +

    +
    • +
  • +

    + Placing of STACK /HEAP. +

    +

    + STACK should always be placed at the end of internal RAM. +

    +

    + If HEAP is placed in internal RAM than it should be placed after RW ZI section. +

    +
    • +
  • +

    + Removing core_cm3.c and core_cm0.c. +

    +

    + On a long term the functions in core_cm3.c and core_cm0.c must be replaced with + appropriate compiler intrinsics. +

    +
    • +
+ + +

10. Limitations

+

+ The following limitations are not covered with the current CMSIS version: +

+
    +
  • + No C startup files for ARM toolchain are provided. +
    • +
  • + No C startup files for GNU toolchain are provided. +
    • +
  • + No C startup files for IAR toolchain are provided. +
    • +
  • + No Tasking projects are provided yet. +
    • +
diff --git a/Libraries/CMSIS/Documentation/CMSIS_Core.htm b/Libraries/CMSIS/Documentation/CMSIS_Core.htm new file mode 100644 index 0000000..b8acb53 --- /dev/null +++ b/Libraries/CMSIS/Documentation/CMSIS_Core.htm @@ -0,0 +1,1337 @@ + + + + CMSIS: Cortex Microcontroller Software Interface Standard + + + +

Cortex Microcontroller Software Interface Standard

+ +

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

+

Version: 1.30 - 30. October 2009

+ +

Information in this file, the accompany manuals, and software is
+ Copyright ARM Ltd.
All rights reserved. +

+ +
+ +

Revision History

+
    +
  • Version 1.00: initial release.
    • +
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
    • +
  • Version 1.02: added Cortex-M0.
    • +
  • Version 1.10: second review.
    • +
  • Version 1.20: third review.
    • +
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
    • +
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
    • +
  • Version 1.30: updated Device Support Packages.
    • +
+ +
+ +

Contents

+ +
    +
  1. About
    2. +
  2. Coding Rules and Conventions
    3. +
  3. CMSIS Files
    4. +
  4. Core Peripheral Access Layer
    5. +
  5. CMSIS Example
    6. +
+ +

About

+ +

+ The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges + that are faced when software components are deployed to physical microcontroller devices based on a + Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M + processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation + with various silicon and software vendors and provides a common approach to interface to peripherals, + real-time operating systems, and middleware components. +

+ +

ARM provides as part of the CMSIS the following software layers that are +available for various compiler implementations:

+
    +
  • Core Peripheral Access Layer: contains name definitions, + address definitions and helper functions to + access core registers and peripherals. It defines also a device + independent interface for RTOS Kernels that includes debug channel + definitions.
    • +
+ +

These software layers are expanded by Silicon partners with:

+
    +
  • Device Peripheral Access Layer: provides definitions + for all device peripherals
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals
    • +
+ +

CMSIS defines for a Cortex-M Microcontroller System:

+
    +
  • A common way to access peripheral registers + and a common way to define exception vectors.
    • +
  • The register names of the Core + Peripherals and the names of the Core + Exception Vectors.
    • +
  • An device independent interface for RTOS Kernels including a debug + channel.
    • +
+ +

+ By using CMSIS compliant software components, the user can easier re-use template code. + CMSIS is intended to enable the combination of software components from multiple middleware vendors. +

+ +

Coding Rules and Conventions

+ +

+ The following section describes the coding rules and conventions used in the CMSIS + implementation. It contains also information about data types and version number information. +

+ +

Essentials

+
    +
  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, + there are disable and enable sequences for PC-LINT inserted.
    • +
  • ANSI standard data types defined in the ANSI C header file + <stdint.h> are used.
    • +
  • #define constants that include expressions must be enclosed by + parenthesis.
    • +
  • Variables and parameters have a complete data type.
    • +
  • All functions in the Core Peripheral Access Layer are + re-entrant.
    • +
  • The Core Peripheral Access Layer has no blocking code + (which means that wait/query loops are done at other software layers).
    • +
  • For each exception/interrupt there is definition for: +
      +
    • an exception/interrupt handler with the postfix _Handler + (for exceptions) or _IRQHandler (for interrupts).
      • +
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
      • +
    • a #define of the interrupt number with the postfix _IRQn.
      • +
    • +
+ +

Recommendations

+ +

The CMSIS recommends the following conventions for identifiers.

+
    +
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • +
  • CamelCase names to identify peripherals access functions and interrupts.
    • +
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
    • +
  • Doxygen comments for all functions are included as described under Function Comments below.
    • +
+ +Comments + +
    +
  • Comments use the ANSI C90 style (/* comment */) or C++ style + (// comment). It is assumed that the programming tools support today + consistently the C++ comment style.
    • +
  • Function Comments provide for each function the following information: +
      +
    • one-line brief function overview.
      • +
    • detailed parameter explanation.
      • +
    • detailed information about return values.
      • +
    • detailed description of the actual function.
      • +
    +

    Doxygen Example:

    + 
    +/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
    +
    • +
+ +

Data Types and IO Type Qualifiers

+ +

+ The Cortex-M HAL uses the standard types from the standard ANSI C header file + <stdint.h>. IO Type Qualifiers are used to specify the access + to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of + debug information of peripheral registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + +
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access
+ +

CMSIS Version Number

+

+ File core_cm3.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
+ +

+ File core_cm0.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
+ + +

CMSIS Cortex Core

+

+ File core_cm3.h contains the type of the CMSIS Cortex-M with the following define: +

+ +
+#define __CORTEX_M                (0x03)
+ +

+ File core_cm0.h contains the type of the CMSIS Cortex-M with the following define: +

+ +
+#define __CORTEX_M                (0x00)
+ + +

CMSIS Files

+

+ This section describes the Files provided in context with the CMSIS to access the Cortex-M + hardware and peripherals. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use + several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm0.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
core_cm3.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes + typically the oscillator (PLL) that is part of the microcontroller device
+ +

device.h

+ +

+ The file device.h is provided by the silicon vendor and is the + central include file that the application programmer is using in + the C source code. This file contains: +

+
    +
  • +

    Interrupt Number Definition: provides interrupt numbers + (IRQn) for all core and device specific exceptions and interrupts.

    +
    • +
  • +

    Configuration for core_cm0.h / core_cm3.h: reflects the + actual configuration of the Cortex-M processor that is part of the actual + device. As such the file core_cm0.h / core_cm3.h is included that + implements access to processor registers and core peripherals.

    +
    • +
  • +

    Device Peripheral Access Layer: provides definitions + for all device peripherals. It contains all data structures and the address + mapping for the device specific peripherals.

    +
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals that are useful for programming + of these peripherals. Access Functions may be provided as inline functions + or can be extern references to a device specific library provided by the + silicon vendor.
    • +
+ + +

Interrupt Number Definition

+ +

To access the device specific interrupts the device.h file defines IRQn +numbers for the complete device using a enum typedef as shown below:

+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
+  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
+/******  STM32 specific Interrupt Numbers ****************************************************************/
+  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
+  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
+  :
+  :
+  } IRQn_Type;
+ + +

Configuration for core_cm0.h / core_cm3.h

+

+ The Cortex-M core configuration options which are defined for each device implementation. Some + configuration options are reflected in the CMSIS layer using the #define settings described below. +

+

+ To access core peripherals file device.h includes file core_cm0.h / core_cm3.h. + Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be + defined before #include <core_cm0.h> / #include <core_cm3.h> + preprocessor command. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#defineFileValueDescription
__NVIC_PRIO_BITScore_cm0.h(2)Number of priority bits implemented in the NVIC (device specific)
__NVIC_PRIO_BITScore_cm3.h(2 ... 8)Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTcore_cm0.h, core_cm3.h(0, 1)Defines if an MPU is present or not
__Vendor_SysTickConfigcore_cm0.h, core_cm3.h(1)When this define is setup to 1, the SysTickConfig function + in core_cm3.h is excluded. In this case the device.h + file must contain a vendor specific implementation of this function.
+ + +

Device Peripheral Access Layer

+

+ Each peripheral uses a prefix which consists of <device abbreviation>_ + and <peripheral name>_ to identify peripheral registers that access this + specific peripheral. The intention of this is to avoid name collisions caused + due to short names. If more than one peripheral of the same type exists, + identifiers have a postfix (digit or letter). For example: +

+
    +
  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device. + 
    +typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000   Receiver Buffer Register    */
+  __O  uint8_t  THR;                     /*!< Offset: 0x000   Transmit Holding Register   */
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000   Divisor Latch LSB           */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004   Divisor Latch MSB           */
+  __IO uint32_t IER;                     /*!< Offset: 0x004   Interrupt Enable Register   */
+  };
+  union {
+  __I  uint32_t IIR;                     /*!< Offset: 0x008   Interrupt ID Register       */
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008   FIFO Control Register       */
+  };
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C   Line Control Register       */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014   Line Status Register        */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C   Scratch Pad Register        */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                     /*!< Offset: 0x020   Autobaud Control Register   */
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024   IrDA Control Register       */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028   Fractional Divider Register */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                     /*!< Offset: 0x030   Transmit Enable Register    */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058   FIFO Level Register         */
+} LPC_UART_TypeDef;
    +
    • +
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. + For example UART1->DR is the data register of UART1. + 
    +#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
    +
    • +
+ +
Minimal Requiements
+

+ To access the peripheral registers and related function in a device the files device.h + and core_cm0.h / core_cm3.h defines as a minimum: +

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. + Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of + the peripheral registers. For example: + 
    +typedef struct {
+  __IO uint32_t CTRL;      /* SysTick Control and Status Register */
+  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */
+  __IO uint32_t VAL;       /* SysTick Current Value Register      */
+  __I  uint32_t CALIB;     /* SysTick Calibration Register        */
+  } SysTick_Type;
    +
    • + +
  • + Base Address for each peripheral (in case of multiple peripherals + that use the same register layout typedef multiple base addresses are defined). For example: + 
    +#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
    +
    • + +
  • + Access Definition for each peripheral (in case of multiple peripherals that use + the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, + LPC_UART2). For Example: + 
    +#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
    +
    • +
+ +

+ These definitions allow to access the peripheral registers from user code with simple assignments like: +

+
SysTick->CTRL = 0;
+ +
Optional Features
+

In addition the device.h file may define:

+
    +
  • + #define constants that simplify access to the peripheral registers. + These constant define bit-positions or other specific patterns are that required for the + programming of the peripheral registers. The identifiers used start with + <device abbreviation>_ and <peripheral name>_. + It is recommended to use CAPITAL letters for such #define constants. +
    • +
  • + Functions that perform more complex functions with the peripheral (i.e. status query before + a sending register is accessed). Again these function start with + <device abbreviation>_ and <peripheral name>_. +
    • +
+ +

core_cm0.h and core_cm0.c

+

+ File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers + and core peripherals with efficient functions (defined as static inline). +

+

+ File core_cm0.c defines several helper functions that access processor registers. +

+

Together these files implement the Core Peripheral Access Layer for a Cortex-M0.

+ +

core_cm3.h and core_cm3.c

+

+ File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers + and core peripherals with efficient functions (defined as static inline). +

+

+ File core_cm3.c defines several helper functions that access processor registers. +

+

Together these files implement the Core Peripheral Access Layer for a Cortex-M3.

+ +

startup_device

+

+ A template file for startup_device is provided by ARM for each supported + compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific + interrupt handlers. Each interrupt handler is defined as weak function + to an dummy handler. Therefore the interrupt handler can be directly used in application software + without any requirements to adapt the startup_device file. +

+

+ The following exception names are fixed and define the start of the vector table for a Cortex-M0: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ The following exception names are fixed and define the start of the vector table for a Cortex-M3: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ In the following examples for device specific interrupts are shown: +

+
+; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+ +

+ Device specific interrupts must have a dummy function that can be overwritten in user code. + Below is an example for this dummy function. +

+
+Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP
+ +

+ The user application may simply define an interrupt handler function by using the handler name + as shown below. +

+
+void WWDG_IRQHandler(void)
+{
+  :
+  :
+}
+ + +

system_device.c

+

+ A template file for system_device.c is provided by ARM but adapted by + the silicon vendor to match their actual device. As a minimum requirement + this file must provide a device specific system configuration function and a global variable + that contains the system frequency. It configures the device and initializes typically the + oscillator (PLL) that is part of the microcontroller device. +

+

+ The file system_device.c must provide + as a minimum requirement the SystemInit function as shown below. +

+ + + + + + + + + + + + + + + + +
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the + oscillator (PLL) that is part of the microcontroller device. For systems + with variable clock speed it also updates the variable SystemCoreClock.
+ SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void)Updates the variable SystemCoreClock and must be called whenever the + core clock is changed during program execution. SystemCoreClockUpdate() + evaluates the clock register settings and calculates the current core clock. +
+ +

+ Also part of the file system_device.c + is the variable SystemCoreClock which contains the current CPU clock speed shown below. +

+ + + + + + + + + + + + +
Variable DefinitionDescription
uint32_t SystemCoreClockContains the system core clock (which is the system clock frequency supplied + to the SysTick timer and the processor core clock). This variable can be + used by the user application to setup the SysTick timer or configure other + parameters. It may also be used by debugger to query the frequency of the + debug timer or configure the trace clock speed.
+ SystemCoreClock is initialized with a correct predefined value.

+ The compiler must be configured to avoid the removal of this variable in + case that the application program is not using it. It is important for + debug systems that the variable is physically present in memory so that + it can be examined to configure the debugger.
+ +

Note

+
    +

  • The above definitions are the minimum requirements for the file + system_device.c. This + file may export more functions or variables that provide a more flexible + configuration of the microcontroller system.

    +
    • +
+ + +

Core Peripheral Access Layer

+ +

Cortex-M Core Register Access

+

+ The following functions are defined in core_cm0.h / core_cm3.h + and provide access to Cortex-M core registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3PRIMASK = 0Global Interrupt enable (using the instruction CPSIE + i)
void __disable_irq (void)M0, M3PRIMASK = 1Global Interrupt disable (using the instruction + CPSID i)
void __set_PRIMASK (uint32_t value)M0, M3PRIMASK = valueAssign value to Priority Mask Register (using the instruction + MSR)
uint32_t __get_PRIMASK (void)M0, M3return PRIMASKReturn Priority Mask Register (using the instruction + MRS)
void __enable_fault_irq (void)M3FAULTMASK = 0Global Fault exception and Interrupt enable (using the + instruction CPSIE + f)
void __disable_fault_irq (void)M3FAULTMASK = 1Global Fault exception and Interrupt disable (using the + instruction CPSID f)
void __set_FAULTMASK (uint32_t value)M3FAULTMASK = valueAssign value to Fault Mask Register (using the instruction + MSR)
uint32_t __get_FAULTMASK (void)M3return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3BASEPRI = valueSet Base Priority (using the instruction MSR)
uiuint32_t __get_BASEPRI (void)M3return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_CONTROL (void)M0, M3return CONTROLReturn Control Register Value (using the instruction + MRS)
void __set_PSP (uint32_t TopOfProcStack)M0, M3PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction + MSR)
uint32_t __get_PSP (void)M0, M3return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3return MSPReturn Main Stack Pointer (using the instruction MRS)
+ +

Cortex-M Instruction Access

+

+ The following functions are defined in core_cm0.h / core_cm3.hand + generate specific Cortex-M instructions. The functions are implemented in the file + core_cm0.c / core_cm3.c. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreGenerated CPU InstructionDescription
void __NOP (void)M0, M3NOPNo Operation
void __WFI (void)M0, M3WFIWait for Interrupt
void __WFE (void)M0, M3WFEWait for Event
void __SEV (void)M0, M3SEVSet Event
void __ISB (void)M0, M3ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3DSBData Synchronization Barrier
void __DMB (void)M0, M3DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3REV16Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value)M0, M3REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3LDREXWLoad exclusive word
uint32_t __STREXB (uint8_t value, uint8_t *addr)M3STREXBStore exclusive byte
uint32_t __STREXB (uint16_t value, uint16_t *addr)M3STREXHStore exclusive half-word
uint32_t __STREXB (uint32_t value, uint32_t *addr)M3STREXWStore exclusive word
void __CLREX (void)M3CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
+ + +

NVIC Access Functions

+

+ The CMSIS provides access to the NVIC via the register interface structure and several helper + functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to + identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative + IRQn values are used for processor core exceptions. +

+

+ For the IRQn values of core exceptions the file device.h provides + the following enum names. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3-14Cortex-M Non Maskable Interrupt
HardFault_IRQnM0, M3-13Cortex-M Hard Fault Interrupt
MemoryManagement_IRQnM3-12Cortex-M Memory Management Interrupt
BusFault_IRQnM3-11Cortex-M Bus Fault Interrupt
UsageFault_IRQnM3-10Cortex-M Usage Fault Interrupt
SVCall_IRQnM0, M3-5Cortex-M SV Call Interrupt
DebugMonitor_IRQnM3-4Cortex-M Debug Monitor Interrupt
PendSV_IRQnM0, M3-2Cortex-M Pend SV Interrupt
SysTick_IRQnM0, M3-1Cortex-M System Tick Interrupt
+ +

The following functions simplify the setup of the NVIC. +The functions are defined as static inline.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreParameterDescription
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)M3Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void)M3(void)Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberEnable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberReturn 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3IRQ NumberReturn 1 if IRQn is active else 0
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)M0, M3IRQ Number, PrioritySet Priority for IRQn
+ (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3IRQ NumberGet Priority for IRQn
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)M3IRQ Number, Priority Group, Preemptive Priority, Sub PriorityEncode priority for given group, preemptive and sub priority
NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)M3IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub PriorityDeccode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void)M0, M3(void)Resets the System
+

Note

+
    +

  • The processor exceptions have negative enum values. Device specific interrupts + have positive enum values and start with 0. The values are defined in + device.h file. +

    +
    • +

  • The values for PreemptPriority and SubPriority + used in functions NVIC_EncodePriority and NVIC_DecodePriority + depend on the available __NVIC_PRIO_BITS implemented in the NVIC. +

    +
    • +
+ + +

SysTick Configuration Function

+ +

The following function is used to configure the SysTick timer and start the +SysTick interrupt.

+ + + + + + + + + + + + + + +
NameParameterDescription
uint32_t SysTickConfig + (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this + call the SysTick timer creates interrupts with the specified time + interval.
+
+ Return: 0 when successful, 1 on failure.
+
+ + +

Cortex-M3 ITM Debug Access

+ +

The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that +provides together with the Serial Viewer Output trace capabilities for the +microcontroller system. The ITM has 32 communication channels; two ITM +communication channels are used by CMSIS to output the following information:

+
    +
  • ITM Channel 0: implements the ITM_SendChar function + which can be used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for + kernel awareness debugging.
    • +
+

Note

+
    +

  • The ITM channel 31 is selected for the RTOS kernel since some kernels + may use the Privileged level for program execution. ITM + channels have 4 groups with 8 channels each, whereby each group can be + configured for access rights in the Unprivileged level. The ITM channel 0 + may be therefore enabled for the user task whereas ITM channel 31 may be + accessible only in Privileged level from the RTOS kernel itself.

    +
    • +
+ +

The prototype of the ITM_SendChar routine is shown in the +table below.

+ + + + + + + + + + + + + + +
NameParameterDescription
void uint32_t ITM_SendChar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The + function returns when no debugger is connected that has booked the + output. It is blocking when a debugger is connected, but the + previous character send is not transmitted.

+ Return: the input character 'chr'.
+ +

+ Example for the usage of the ITM Channel 31 for RTOS Kernels: +

+
+  // check if debugger connected and ITM channel enabled for tracing
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+  (ITM->TCR & ITM_TCR_ITMENA) &&
+  (ITM->TER & (1UL << 31))) {
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+  }
+ + +

Cortex-M3 additional Debug Access

+ +

CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. +Data can be transmitted via a certain global buffer variable towards the target system.

+ +

The buffer variable and the prototypes of the additional functions are shown in the +table below.

+ + + + + + + + + + + + + + + + + + + + + + + + +
NameParameterDescription
extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system.

+ Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in + ITM_RxBuffer.

+ Return: -1 indicates that no character was received.
int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer.

+ Return: 1 indicates that a character is available, 0 indicates that + no character is available.
+ + +

CMSIS Example

+

+ The following section shows a typical example for using the CMSIS layer in user applications. + The example is based on a STM32F10x Device. +

+
+#include "stm32f10x.h"
+
+volatile uint32_t msTicks;                       /* timeTicks counter */
+
+void SysTick_Handler(void) {
+  msTicks++;                                     /* increment timeTicks counter */
+}
+
+__INLINE static void Delay (uint32_t dlyTicks) {
+  uint32_t curTicks = msTicks;
+
+  while ((msTicks - curTicks) < dlyTicks);
+}
+
+__INLINE static void LED_Config(void) {
+  ;                                              /* Configure the LEDs */
+}
+
+__INLINE static void LED_On (uint32_t led) {
+  ;                                              /* Turn On  LED */
+}
+
+__INLINE static void LED_Off (uint32_t led) {
+  ;                                              /* Turn Off LED */
+}
+
+int main (void) {
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+    ;                                            /* Handle Error */
+    while (1);
+  }
+  
+  LED_Config();                                  /* configure the LEDs */                            
+ 
+  while(1) {
+    LED_On (0x100);                              /* Turn  on the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+    LED_Off (0x100);                             /* Turn off the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+  }
+}
+ + + \ No newline at end of file diff --git a/Libraries/CMSIS/License.doc b/Libraries/CMSIS/License.doc new file mode 100644 index 0000000..b6b8ace Binary files /dev/null and b/Libraries/CMSIS/License.doc differ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html b/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html new file mode 100644 index 0000000..e58d1f0 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html @@ -0,0 +1,295 @@ + + + + + + + + +Release Notes for STM32F10x Standard Peripherals Library Drivers + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F10x Standard Peripherals Library Drivers +(StdPeriph_Driver)

+

Copyright 2010 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x Standard Peripherals Library +Drivers update History
    2. +
  2. License
    3. +
+ + +

STM32F10x Standard +Peripherals Library Drivers  update History

+

3.4.0 +- 10/15/2010

+ +
    +
  1. General
    2. +
+ +
    +
  • Add support for STM32F10x High-density value line devices.
    • +
+ +
    +
  1. STM32F10x_StdPeriph_Driver
    2. +
+ + +
    + +
  • stm32f10x_bkp.h/.c
    • +
      +
    • Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_can.h/.c
    • +
      +
    • Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
      +
      • +
    • Update the wording of some defines and Asserts macro.
      +
      • +
    • CAN_GetFlagStatus() +and CAN_ClearFlag() functions: updated to support new flags (were not +supported in previous version). These flags are:  CAN_FLAG_RQCP0, +CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1, +CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,   CAN_FLAG_FOV0, +CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
      +
      • +
    • CAN_GetITStatus() +function: add a check of the interrupt enable bit before getting the +status of corresponding interrupt pending bit.
      +
      • +
    • CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
      +
      • +
    +
  • stm32f10x_crc.h/.c
    • +
      +
    • Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_dac.h/.c
    • +
      +
    • Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_dbgmcu.h/.c
    • +
      +
    • Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_dma.h/.c
    • +
      +
    • Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
      • +
    • Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
      +
      • +
    +
  • stm32f10x_flash.h/.c
    • +
      +
    • FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
      • +
    +
  • stm32f10x_fsmc.h/.c
    • +
      +
    • Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
      • +
    +
  • stm32f10x_gpio.h/.c
    • +
      +
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
      • +
    +
  • stm32f10x_pwr.h/.c
    • +
      +
    • Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
      • +
    +
  • stm32f10x_rtc.h/.c
    • +
      +
    • Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_spi.h/.c
    • +
      +
    • Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
      • +
    +
  • stm32f10x_tim.h/.c
    • +
    • Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".
    + +
+ +

3.3.0 +- 04/16/2010

+ +
  1. General
+
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
+
  1. STM32F10x_StdPeriph_Driver
+
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: +updated to support Bank2 of XL-density devices (up to 1MByte of Flash +memory). For more details, refer to the description provided within +stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() +function: updated to check whether the last event contains the +I2C_EVENT  (instead of check whether the last event is equal to +I2C_EVENT)
    • Add +detailed description of I2C events and how to manage them using the +functions provided by this driver. For more information, refer to +stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        +#define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000000)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000001)
      by
        #define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000001)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000000)
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
    • +
  • Almost +peripherals drivers were updated to support Value +line devices features
    • +
  • Drivers limitations fix and enhancements.
    • + +
+
    +
  1. STM32F10x_StdPeriph_Driver
    2. +
+
    +
  • Add new +firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • +
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • +
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • +
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • +
  • USART +driver: add support for Oversampling by 8 mode and onebit method. 2 +functions has been added: USART_OverSampling8Cmd() and +USART_OneBitMethodCmd().
    +
    • +
  • DAC +driver: add new functions handling the DAC under run feature: +DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() +and DAC_ClearITPendingBit().
    • +
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    +
    • +
  • FLASH +driver: the FLASH_EraseOptionBytes() function updated. This is now just +erasing the option bytes without modifying the RDP status either +enabled or disabled.
    • +
  • PWR +driver: the PWR_EnterSTOPMode() function updated. When woken up from +STOP mode, this function resets again the SLEEPDEEP bit in the +Cortex-M3 System Control register to allow Sleep mode entering.
    • + + +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h new file mode 100644 index 0000000..934d8f0 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32f10x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h new file mode 100644 index 0000000..b775ceb --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h @@ -0,0 +1,482 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; +/** + * @} + */ + +/** @defgroup ADC_Exported_Constants + * @{ + */ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_mode + * @{ + */ + +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) +/** + * @} + */ + +/** @defgroup ADC_sampling_time + * @{ + */ + +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) +/** + * @} + */ + +/** @defgroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_offset + * @{ + */ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_length + * @{ + */ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @defgroup ADC_injected_rank + * @{ + */ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC_regular_rank + * @{ + */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h new file mode 100644 index 0000000..8e2083a --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the BKP firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @defgroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Constants + * @{ + */ + +/** @defgroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** + * @} + */ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin + * @{ + */ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** + * @} + */ + +/** @defgroup Data_Backup_Register + * @{ + */ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_BKP_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h new file mode 100644 index 0000000..057db59 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h @@ -0,0 +1,583 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter can be a value between 0 to 0xFF */ +} CanRxMsg; + +/** + * @} + */ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */ + +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#ifndef STM32F10X_CL + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#else + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ + +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ + +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ + +#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/** + * @} + */ + +/** @defgroup Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) + +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ + +#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ + +#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ + + + +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions + * @{ + */ + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CAN_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h new file mode 100644 index 0000000..69c256c --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CEC_H +#define __STM32F10x_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + + +/** @defgroup CEC_Exported_Types + * @{ + */ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. + This parameter can be a value of @ref CEC_BitTiming_Mode */ + uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. + This parameter can be a value of @ref CEC_BitPeriod_Mode */ +}CEC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_BitTiming_Mode + * @{ + */ +#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ + +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ + ((MODE) == CEC_BitTimingErrFreeMode)) +/** + * @} + */ + +/** @defgroup CEC_BitPeriod_Mode + * @{ + */ +#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ + ((MODE) == CEC_BitPeriodFlexibleMode)) +/** + * @} + */ + + +/** @defgroup CEC_interrupts_definition + * @{ + */ +#define CEC_IT_TERR CEC_CSR_TERR +#define CEC_IT_TBTRF CEC_CSR_TBTRF +#define CEC_IT_RERR CEC_CSR_RERR +#define CEC_IT_RBTF CEC_CSR_RBTF +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ + ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) +/** + * @} + */ + + +/** @defgroup CEC_Own_Addres + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) +/** + * @} + */ + +/** @defgroup CEC_Prescaler + * @{ + */ +#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) + +/** + * @} + */ + +/** @defgroup CEC_flags_definition + * @{ + */ + +/** + * @brief ESR register flags + */ +#define CEC_FLAG_BTE ((uint32_t)0x10010000) +#define CEC_FLAG_BPE ((uint32_t)0x10020000) +#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) +#define CEC_FLAG_SBE ((uint32_t)0x10080000) +#define CEC_FLAG_ACKE ((uint32_t)0x10100000) +#define CEC_FLAG_LINE ((uint32_t)0x10200000) +#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) + +/** + * @brief CSR register flags + */ +#define CEC_FLAG_TEOM ((uint32_t)0x00000002) +#define CEC_FLAG_TERR ((uint32_t)0x00000004) +#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) +#define CEC_FLAG_RSOM ((uint32_t)0x00000010) +#define CEC_FLAG_REOM ((uint32_t)0x00000020) +#define CEC_FLAG_RERR ((uint32_t)0x00000040) +#define CEC_FLAG_RBTF ((uint32_t)0x00000080) + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ + ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ + ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ + ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ + ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ + ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ + ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions + * @{ + */ +void CEC_DeInit(void); +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ITConfig(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_SetPrescaler(uint16_t CEC_Prescaler); +void CEC_SendDataByte(uint8_t Data); +uint8_t CEC_ReceiveDataByte(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessageCmd(FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint8_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h new file mode 100644 index 0000000..32f6264 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h new file mode 100644 index 0000000..1511e38 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in Connectivity line, Medium-density and Low-density Value Line devices */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel + only in Medium-density and Low-density Value Line devices*/ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ +#endif + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +#endif +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h new file mode 100644 index 0000000..c55acd5 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) +#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) +#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) +#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) +#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h new file mode 100644 index 0000000..3e79cea --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h @@ -0,0 +1,438 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); +void DMA_ClearFlag(uint32_t DMA_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMA_IT); +void DMA_ClearITPendingBit(uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DMA_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h new file mode 100644 index 0000000..b18ffd5 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h new file mode 100644 index 0000000..331c58b --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h @@ -0,0 +1,425 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32 Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with STM32 Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ + +/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ +#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +#ifdef STM32F10X_XL +/** + * @} + */ +/** @defgroup FLASH_Boot + * @{ + */ +#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ +#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 or Bank 1, + depending on the activation of the bank */ +#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) +#endif +/** + * @} + */ +/** @defgroup FLASH_Interrupts + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ +#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ + +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#else +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#endif + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ +#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ +#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ +#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)|| \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) +#else +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for all STM32F10x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +/*------------ New function used for all STM32F10x devices -----*/ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef STM32F10X_XL +/*---- New Functions used only with STM32F10x_XL density devices -----*/ +void FLASH_UnlockBank2(void); +void FLASH_LockBank2(void); +FLASH_Status FLASH_EraseAllBank2Pages(void); +FLASH_Status FLASH_GetBank2Status(void); +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000..1fade96 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h @@ -0,0 +1,732 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is dont care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait + * @{ + */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) +#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ + ((STATE) == FSMC_AsynchronousWait_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h new file mode 100644 index 0000000..1a6d260 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h @@ -0,0 +1,384 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Remap_define + * @{ + */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ + +#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ + +#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ +#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ +#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + only for High density Value line devices) */ + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ + ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ + ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ + ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ + ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ + ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ + ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ + ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ + ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) + +/** + * @} + */ + +/** @defgroup GPIO_Port_Sources + * @{ + */ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** + * @} + */ + +/** @defgroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ + ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) + +/** + * @} + */ +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h new file mode 100644 index 0000000..27c8e85 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h @@ -0,0 +1,670 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of tranfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlagStatus() function (see below). + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h new file mode 100644 index 0000000..288a0cd --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @defgroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IWDG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h new file mode 100644 index 0000000..c5a1ae1 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h @@ -0,0 +1,155 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h new file mode 100644 index 0000000..be69b88 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h @@ -0,0 +1,726 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the RCC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) + #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) + #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +#else + #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup PLL_multiplication_factor + * @{ + */ +#ifndef STM32F10X_CL + #define RCC_PLLMul_2 ((uint32_t)0x00000000) + #define RCC_PLLMul_3 ((uint32_t)0x00040000) + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_10 ((uint32_t)0x00200000) + #define RCC_PLLMul_11 ((uint32_t)0x00240000) + #define RCC_PLLMul_12 ((uint32_t)0x00280000) + #define RCC_PLLMul_13 ((uint32_t)0x002C0000) + #define RCC_PLLMul_14 ((uint32_t)0x00300000) + #define RCC_PLLMul_15 ((uint32_t)0x00340000) + #define RCC_PLLMul_16 ((uint32_t)0x00380000) + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +#else + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) + + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_6_5)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup PREDIV1_division_factor + * @{ + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) + #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) + #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) + #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) + #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) + #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) + #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) + #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) + #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) + #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) + #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) + #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) + #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) + #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) + #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + + #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +#endif +/** + * @} + */ + + +/** @defgroup PREDIV1_clock_source + * @{ + */ +#ifdef STM32F10X_CL +/* PREDIV1 clock source (for STM32 connectivity line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ + ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/* PREDIV1 clock source (for STM32 Value line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) +#endif +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup PREDIV2_division_factor + * @{ + */ + + #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) + #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) + #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) + #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) + #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) + #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) + #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) + #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) + #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) + #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) + #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) + #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) + #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) + #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) + #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + + #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ + ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ + ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ + ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ + ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ + ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ + ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ + ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) +/** + * @} + */ + + +/** @defgroup PLL2_multiplication_factor + * @{ + */ + + #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) + #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) + #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) + #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) + #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) + #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) + #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) + #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) + #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + + #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ + ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ + ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ + ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ + ((MUL) == RCC_PLL2Mul_20)) +/** + * @} + */ + + +/** @defgroup PLL3_multiplication_factor + * @{ + */ + + #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) + #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) + #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) + #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) + #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) + #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) + #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) + #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) + #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + + #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ + ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ + ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ + ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ + ((MUL) == RCC_PLL3Mul_20)) +/** + * @} + */ + +#endif /* STM32F10X_CL */ + + +/** @defgroup System_clock_source + * @{ + */ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifndef STM32F10X_CL + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +#else + #define RCC_IT_PLL2RDY ((uint8_t)0x20) + #define RCC_IT_PLL3RDY ((uint8_t)0x40) + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) + #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) +#endif /* STM32F10X_CL */ + + +/** + * @} + */ + +#ifndef STM32F10X_CL +/** @defgroup USB_Device_clock_source + * @{ + */ + + #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) + #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** + * @} + */ +#else +/** @defgroup USB_OTG_FS_clock_source + * @{ + */ + #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) + #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) + + #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ + ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +#ifdef STM32F10X_CL +/** @defgroup I2S2_clock_source + * @{ + */ + #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) +/** + * @} + */ + +/** @defgroup I2S3_clock_source + * @{ + */ + #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +/** @defgroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** + * @} + */ + +/** @defgroup LSE_configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** + * @} + */ + +/** @defgroup AHB_peripheral + * @{ + */ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) + +#ifndef STM32F10X_CL + #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +#else + #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) + #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) + #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) + #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup APB2_peripheral + * @{ + */ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_peripheral + * @{ + */ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifndef STM32F10X_CL + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) +#else + #define RCC_MCO_PLL2CLK ((uint8_t)0x08) + #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) + #define RCC_MCO_XT1 ((uint8_t)0x0A) + #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ + ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ + ((MCO) == RCC_MCO_PLL3CLK)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifndef STM32F10X_CL + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#else + #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) + #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#endif /* STM32F10X_CL */ + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +#endif + +#ifdef STM32F10X_CL + void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); + void RCC_PLL2Config(uint32_t RCC_PLL2Mul); + void RCC_PLL2Cmd(FunctionalState NewState); + void RCC_PLL3Config(uint32_t RCC_PLL3Mul); + void RCC_PLL3Cmd(FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); + +#ifndef STM32F10X_CL + void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +#else + void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +#endif /* STM32F10X_CL */ + +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); + +#ifdef STM32F10X_CL + void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); + void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +#endif /* STM32F10X_CL */ + +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +#ifdef STM32F10X_CL +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h new file mode 100644 index 0000000..17fefc2 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + +/** @defgroup RTC_interrupts_define + * @{ + */ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** + * @} + */ + +/** @defgroup RTC_interrupts_flags + * @{ + */ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions + * @{ + */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RTC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h new file mode 100644 index 0000000..7808c06 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h @@ -0,0 +1,530 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_soucres + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h new file mode 100644 index 0000000..53c868a --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_mangement + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h new file mode 100644 index 0000000..a71e654 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h @@ -0,0 +1,1137 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @defgroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This sturcture is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 and 8 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8, 15 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ + ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_18Bytes)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_TIM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h new file mode 100644 index 0000000..cce998c --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/** + * @} + */ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4)) +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ + ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTS)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_USART_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h new file mode 100644 index 0000000..09575ea --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @defgroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c new file mode 100644 index 0000000..964e5bf --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c new file mode 100644 index 0000000..a2b3054 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c @@ -0,0 +1,1306 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the ADC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((uint32_t)0x00000800) +#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((uint32_t)0x00000001) +#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((uint32_t)0x00000100) +#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((uint32_t)0x0000001F) +#define SQR2_SQ_Set ((uint32_t)0x0000001F) +#define SQR1_SQ_Set ((uint32_t)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((uint32_t)0x00300000) +#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((uint32_t)0x00000007) +#define SMPR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((uint8_t)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } + else + { + if (ADCx == ADC3) + { + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. + * Note: ADC2 hasn't a DMA capability. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Resets the selected ADC calibration registers. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Resets the selected ADC calibartion registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/** + * @brief Gets the selected ADC reset calibration registers status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC reset calibration registers (SET or RESET). + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * @retval The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) DR_ADDRESS); +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_Offset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param NewState: new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCxs interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c new file mode 100644 index 0000000..ce3519e --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the BKP firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @defgroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_MASK ((uint16_t)0xFF80) +#define RTCCR_MASK ((uint16_t)0xFC7F) + +/** + * @} + */ + + +/** @defgroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TamperPinLevel_High: Tamper pin active on high level + * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level + * @retval None + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param NewState: new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param NewState: new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** + * @brief Select the RTC output source to output on the Tamper pin. + * @param BKP_RTCOutputSource: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. + * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency + * divided by 64 on the Tamper pin. + * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on + * the Tamper pin. + * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on + * the Tamper pin. + * @retval None + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_MASK; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Sets RTC Clock Calibration value. + * @param CalibrationValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_MASK; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @param Data: data to write + * @retval None + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @retval The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @param None + * @retval The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + * @param None + * @retval None + */ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= BKP_CSR_CTE; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @param None + * @retval The new state of the Tamper Pin Interrupt (SET or RESET). + */ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + * @param None + * @retval None + */ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= BKP_CSR_CTI; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c new file mode 100644 index 0000000..dfbc158 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c @@ -0,0 +1,1166 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the CAN firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @defgroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ + +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + + +/** + * @} + */ + +/** @defgroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_FunctionPrototypes + * @{ + */ + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CANINITFAILED or CANINITOK. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CANINITFAILED; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0x00; + + while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + InitStatus = CANINITOK ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * @retval None. + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which + * will be initialized. + * @retval None. + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @note This function applies only to STM32 Connectivity line devices. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None. + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + /* enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * -CAN_IT_TME, + * -CAN_IT_FMP0, + * -CAN_IT_FF0, + * -CAN_IT_FOV0, + * -CAN_IT_FMP1, + * -CAN_IT_FF1, + * -CAN_IT_FOV1, + * -CAN_IT_EWG, + * -CAN_IT_EPV, + * -CAN_IT_LEC, + * -CAN_IT_ERR, + * -CAN_IT_WKU or + * -CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} + +/** + * @brief Initiates the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN + * DLC and CAN datas. + * @retval The number of the mailbox that is used for transmission + * or CAN_NO_MB if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_NO_MB; + } + + if (transmit_mailbox != CAN_NO_MB) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | + TxMessage->RTR); + } + + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + /* RQCP, TXOK and TME bits */ + uint8_t state = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + switch (TransmitMailbox) + { + case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2); + state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0); + state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26); + break; + case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6); + state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8); + state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27); + break; + case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14); + state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16); + state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28); + break; + default: + state = CANTXFAILED; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CANTXPENDING; + break; + /* transmit failed */ + case (0x5): state = CANTXFAILED; + break; + /* transmit succedeed */ + case (0x7): state = CANTXOK; + break; + default: + state = CANTXFAILED; + break; + } + return state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None. + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} + +/** + * @brief Releases a FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None. + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which + * contains CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_ID_STD) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + CAN_FIFORelease(CANx, FIFONumber); +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + +/** + * @brief Enters the low power mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CANSLEEPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CANSLEEPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CANWAKEUPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* Sleep mode exited */ + wakeupstatus = CANWAKEUPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWG + * - CAN_FLAG_EPV + * - CAN_FLAG_BOF + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FMP1 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FMP0 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval None. + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_IT_TME + * - CAN_IT_FMP0 + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FMP1 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the enable interrupt bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC); + itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default : + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANxs interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * - CAN_IT_TME + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval None. + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/ + break; + default : + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c new file mode 100644 index 0000000..f9ea52c --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the CEC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_cec.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/** @defgroup CEC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Defines + * @{ + */ + +/* ------------ CEC registers bit address in the alias region ----------- */ +#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) + +/* --- CFGR Register ---*/ + +/* Alias word address of PE bit */ +#define CFGR_OFFSET (CEC_OFFSET + 0x00) +#define PE_BitNumber 0x00 +#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) + +/* Alias word address of IE bit */ +#define IE_BitNumber 0x01 +#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TSOM bit */ +#define CSR_OFFSET (CEC_OFFSET + 0x10) +#define TSOM_BitNumber 0x00 +#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) + +/* Alias word address of TEOM bit */ +#define TEOM_BitNumber 0x01 +#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) + +#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + /* Enable CEC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + /* Release CEC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + + +/** + * @brief Initializes the CEC peripheral according to the specified + * parameters in the CEC_InitStruct. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that + * contains the configuration information for the specified + * CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); + assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); + + /*---------------------------- CEC CFGR Configuration -----------------*/ + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear BTEM and BPEM bits */ + tmpreg &= CFGR_CLEAR_Mask; + + /* Configure CEC: Bit Timing Error and Bit Period Error */ + tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); + + /* Write to CEC CFGR register*/ + CEC->CFGR = tmpreg; + +} + +/** + * @brief Enables or disables the specified CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; + + if(NewState == DISABLE) + { + /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ + while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) + { + } + } +} + +/** + * @brief Enables or disables the CEC interrupt. + * @param NewState: new state of the CEC interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + + /* Set the CEC own address */ + CEC->OAR = CEC_OwnAddress; +} + +/** + * @brief Sets the CEC prescaler value. + * @param CEC_Prescaler: CEC prescaler new value + * @retval None + */ +void CEC_SetPrescaler(uint16_t CEC_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); + + /* Set the Prescaler value*/ + CEC->PRES = CEC_Prescaler; +} + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendDataByte(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXD = Data ; +} + + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveDataByte(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXD); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; +} + +/** + * @brief Transmits message with or without an EOM bit. + * @param NewState: new state of the CEC Tx End Of Message. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_EndOfMessageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The data byte will be transmitted with or without an EOM bit*/ + *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; +} + +/** + * @brief Gets the CEC flag status + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_BTE: Bit Timing Error + * @arg CEC_FLAG_BPE: Bit Period Error + * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error + * @arg CEC_FLAG_SBE: Start Bit Error + * @arg CEC_FLAG_ACKE: Block Acknowledge Error + * @arg CEC_FLAG_LINE: Line Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error + * @arg CEC_FLAG_TEOM: Tx End Of Message + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t cecreg = 0, cecbase = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Get the CEC peripheral base address */ + cecbase = (uint32_t)(CEC_BASE); + + /* Read flag register index */ + cecreg = CEC_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + CEC_FLAG &= FLAG_Mask; + + if(cecreg != 0) + { + /* Flag in CEC ESR Register */ + CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); + + /* Get the CEC ESR register address */ + cecbase += 0xC; + } + else + { + /* Get the CEC CSR register address */ + cecbase += 0x10; + } + + if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) + { + /* CEC_FLAG is set */ + bitstatus = SET; + } + else + { + /* CEC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CEC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC flags */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint8_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; + + /* Check the status of the specified CEC interrupt */ + if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC_IT is set */ + bitstatus = SET; + } + else + { + /* CEC_IT is reset */ + bitstatus = RESET; + } + /* Return the CEC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC interrupt pending bits */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c new file mode 100644 index 0000000..9e8e329 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c @@ -0,0 +1,159 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c new file mode 100644 index 0000000..613ed6d --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c @@ -0,0 +1,570 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave genration, + mask/amplitude for wave genration */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); + } +} +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} +#endif + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignement for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignement for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignement for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC cahnnel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelxs interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c new file mode 100644 index 0000000..3238f8a --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c @@ -0,0 +1,161 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c new file mode 100644 index 0000000..ddf7b82 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c @@ -0,0 +1,711 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= DMA_CCR1_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Calculate the used DMA */ + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + /* Calculate the used DMA */ + + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA flags */ + DMA2->IFCR = DMA_FLAG; + } + else + { + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA interrupt */ + if ((tmpreg & DMA_IT) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelxs interrupt pending bits. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA interrupt pending bits */ + DMA2->IFCR = DMA_IT; + } + else + { + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c new file mode 100644 index 0000000..e88af56 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTIs line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTIs line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c new file mode 100644 index 0000000..d009164 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c @@ -0,0 +1,1683 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** +@code + + This driver provides functions to configure and program the Flash memory of all STM32F10x devices, + including the latest STM32F10x_XL density devices. + + STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: + - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) + - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) + While other STM32F10x devices features only one bank with memory up to 512 Kbytes. + + In version V3.3.0, some functions were updated and new ones were added to support + STM32F10x_XL devices. Thus some functions manages all devices, while other are + dedicated for XL devices only. + + The table below presents the list of available functions depending on the used STM32F10x devices. + + *************************************************** + * Legacy functions used for all STM32F10x devices * + *************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_SetLatency | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_PrefetchBufferCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | + | | | | - For other devices: unlock Bank1 and it is equivalent | + | | | | to FLASH_UnlockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | + | | | | - For other devices: lock Bank1 and it is equivalent | + | | | | to FLASH_LockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | + | | | | - For other devices: erase a page in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | + | | | | - For other devices: erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseOptionBytes | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramOptionByteData | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EnableWriteProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ReadOutProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_UserOptionByteConfig | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetUserOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| + | | | | - For other devices: enable Bank1's interrupts | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| + | | | | - For other devices: return Bank1's flag status | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | + | | | | - For other devices: clear Bank1's flag | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | + | | | | equivalent to FLASH_GetBank1Status function | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | + | | | | equivalent to: FLASH_WaitForLastBank1Operation function | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ************************************************************************************************************************ + * New functions used for all STM32F10x devices to manage Bank1: * + * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * + * - For other devices, these functions are optional (covered by functions listed above) * + ************************************************************************************************************************ + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ***************************************************************************** + * New Functions used only with STM32F10x_XL density devices to manage Bank2 * + ***************************************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank2 | Yes | No | - Lock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | + +----------------------------------------------------------------------------------------------------------------------------------+ +@endcode +*/ + + +/** + * @brief Sets the code latency value. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. + * - For all other devices it unlocks Bank1 and it is equivalent + * to FLASH_UnlockBank1 function.. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + +#ifdef STM32F10X_XL + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; +#endif /* STM32F10X_XL */ +} +/** + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1. + * - For all other devices it unlocks Bank1 and it is + * equivalent to FLASH_Unlock function. + * @param None + * @retval None + */ +void FLASH_UnlockBank1(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +#ifdef STM32F10X_XL +/** + * @brief Unlocks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_UnlockBank2(void) +{ + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; + +} +#endif /* STM32F10X_XL */ + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_LockBank1 function. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; + +#ifdef STM32F10X_XL + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Locks the FLASH Bank1 Program Erase Controller. + * @note this function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_Lock function. + * @param None + * @retval None + */ +void FLASH_LockBank1(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; +} + +#ifdef STM32F10X_XL +/** + * @brief Locks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_LockBank2(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for all STM32F10x devices. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + +#ifdef STM32F10X_XL + if(Page_Address < FLASH_BANK1_END_ADDRESS) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR2|= CR_PER_Set; + FLASH->AR2 = Page_Address; + FLASH->CR2|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR2 &= CR_PER_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all Bank1 FLASH pages. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function erases all Bank1 pages. + * - For all other devices it erases all Bank1 pages and it is equivalent + * to FLASH_EraseAllPages function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Erases all Bank2 FLASH pages. + * @note This function can be used only for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank2Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + if(Address < FLASH_BANK1_END_ADDRESS - 2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + FLASH->CR2 |= CR_PG_Set; + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(Address < FLASH_BANK1_END_ADDRESS) + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Pages: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 + * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 + * and FLASH_WRProt_Pages124to127 + * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 + * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 + * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 + * @arg FLASH_WRProt_AllPages + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for all STM32F10x devices. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for all STM32F10x devices. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Configures to boot from Bank1 or Bank2. + * @note This function can be used only for STM32F10x_XL density devices. + * @param FLASH_BOOT: select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * For more information, please refer to AN2606 from www.st.com. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) +{ + FLASH_Status status = FLASH_COMPLETE; + assert_param(IS_FLASH_BOOT(FLASH_BOOT)); + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + if(FLASH_BOOT == FLASH_BOOT_Bank1) + { + OB->USER |= OB_USER_BFB2; + } + else + { + OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Falsh write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts + for Bank1 and Bank2. + * - For other devices it enables or disables the specified FLASH interrupts for Bank1. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((FLASH_IT & 0x80000000) != 0x0) + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); + } + else + { + /* Disable the interrupt sources */ + FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); + } + } + else + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +#endif /* STM32F10X_XL */ +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function checks whether the specified + * Bank1 or Bank2 flag is set or not. + * - For other devices, it checks whether the specified Bank1 flag is + * set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH_FLAG & 0x80000000) != 0x0) + { + if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } +#endif /* STM32F10X_XL */ + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASHs pending flags. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function clears Bank1 or Bank2s pending flags + * - For other devices, it clears Bank1s pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + if((FLASH_FLAG & 0x80000000) != 0x0) + { + /* Clear the flags */ + FLASH->SR2 = FLASH_FLAG; + } + else + { + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; + } + +#else + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Returns the FLASH Bank1 Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetStatus function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +#ifdef STM32F10X_XL +/** + * @brief Returns the FLASH Bank2 Status. + * @note This function can be used for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank2Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} +#endif /* STM32F10X_XL */ +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation. + * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation + * to complete or a TIMEOUT to occur. + * - For all other devices it waits for a Flash operation to complete + * or a TIMEOUT to occur. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastOperation. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. + * @note This function can be used only for STM32F10x_XL density devices. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank2Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) + { + status = FLASH_GetBank2Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c new file mode 100644 index 0000000..b4584aa --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c @@ -0,0 +1,863 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for the FSMC PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMCs pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMCs interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c new file mode 100644 index 0000000..f4ccba9 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c @@ -0,0 +1,647 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +/* --- MAPR Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * @param None + * @retval None + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param GPIO_PortSource: selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param GPIO_PinSource: specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** + * @brief Enables or disables the Event Output. + * @param NewState: new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIO_Remap: selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping + * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping + * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping + * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping + * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping + * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping + * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping + * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping + * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping + * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) + * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) + * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) + * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) + * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) + * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to + * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. + * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) + * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) + * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) + * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) + * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + * only for High density Value line devices) + * @param NewState: new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->MAPR2; + } + else + { + tmpreg = AFIO->MAPR; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->MAPR2 = tmpreg; + } + else + { + AFIO->MAPR = tmpreg; + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param GPIO_PinSource: specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to STM32 Connectivity line devices. + * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MediaInterface_MII: MII mode + * @arg GPIO_ETH_MediaInterface_RMII: RMII mode + * @retval None + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); + + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c new file mode 100644 index 0000000..7b35a62 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c @@ -0,0 +1,1285 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the I2C firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CR1_PE_Set ((uint16_t)0x0001) +#define CR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((uint16_t)0x0100) +#define CR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((uint16_t)0x0200) +#define CR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((uint16_t)0x0400) +#define CR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((uint16_t)0x0040) +#define CR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((uint16_t)0x1000) +#define CR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((uint16_t)0x0020) +#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((uint16_t)0x0010) +#define CR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((uint16_t)0x0800) +#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((uint16_t)0x1000) +#define CR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((uint16_t)0x0001) +#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((uint16_t)0x0001) +#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | CCR_FS_Set); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transfered bytes. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + + + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applciations as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentionned limitation of I2C_GetFlagStatus() function. + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defiend by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * stm32f10x_i2c.h file. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval An ErrorStatus enumuration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Return status */ + return lastevent; +} + +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL + * Address matched flag (Slave mode)ENDAD + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + + + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) ADSL + * Address matched flag (Slave mode)ENDAD + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cxs interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c new file mode 100644 index 0000000..d1014c9 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the IWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @defgroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @defgroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c new file mode 100644 index 0000000..9d7a4b5 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V + * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V + * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V + * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V + * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_MASK; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters STANDBY mode. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= PWR_CR_CWUF; + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c new file mode 100644 index 0000000..ba805d6 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c @@ -0,0 +1,1474 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +#ifdef STM32F10X_CL + /* Alias word address of PLL2ON bit */ + #define PLL2ON_BitNumber 0x1A + #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) + + /* Alias word address of PLL3ON bit */ + #define PLL3ON_BitNumber 0x1C + #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) + +#ifndef STM32F10X_CL + #define USBPRE_BitNumber 0x16 + #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) +#else + #define OTGFSPRE_BitNumber 0x16 + #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +#ifdef STM32F10X_CL +/* --- CFGR2 Register ---*/ + + /* Alias word address of I2S2SRC bit */ + #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) + #define I2S2SRC_BitNumber 0x11 + #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) + + /* Alias word address of I2S3SRC bit */ + #define I2S3SRC_BitNumber 0x12 + #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) +#else + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#endif /* STM32F10X_CL */ + +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/* CFGR2 register bit mask */ + #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) + #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#endif +#ifdef STM32F10X_CL + #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) + #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) + #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) +#endif /* STM32F10X_CL */ + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, + * this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} + * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/** + * @brief Configures the PREDIV1 division factor. + * @note + * - This function must be used only when the PLL is disabled. + * - This function applies only to STM32 Connectivity line and Value line + * devices. + * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock + * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @note + * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + /* Set the PREDIV1 clock source and division factor */ + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} +#endif + +#ifdef STM32F10X_CL +/** + * @brief Configures the PREDIV2 division factor. + * @note + * - This function must be used only when both PLL2 and PLL3 are disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV2[3:0] bits */ + tmpreg &= ~CFGR2_PREDIV2; + /* Set the PREDIV2 division factor */ + tmpreg |= RCC_PREDIV2_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Configures the PLL2 multiplication factor. + * @note + * - This function must be used only when the PLL2 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL2Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL2MUL; + /* Set the PLL2 configuration bits */ + tmpreg |= RCC_PLL2Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL2. + * @note + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * - This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; +} + + +/** + * @brief Configures the PLL3 multiplication factor. + * @note + * - This function must be used only when the PLL3 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL3Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL3MUL; + /* Set the PLL3 configuration bits */ + tmpreg |= RCC_PLL3Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL3. + * @note This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +#ifndef STM32F10X_CL +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source + * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} +#else +/** + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * This function applies only to STM32 Connectivity line devices. + * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. + * This clock is derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @retval None + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); + + *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * This parameter can be one of the following values: + * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 + * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 + * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 + * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the I2S2 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S2 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry + * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry + * @retval None + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; +} + +/** + * @brief Configures the I2S3 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S3 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry + * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry + * @retval None + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it cant be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + + #if defined (STM32F10X_HD_VL) + prediv1factor = ((RCC->CFGR & RCC_CFGR_PLLXTPRE) >>17) +1; + #else + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + #endif + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; + RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @arg RCC_AHBPeriph_ETH_MAC_Tx + * @arg RCC_AHBPeriph_ETH_MAC_Rx + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FSMC + * @arg RCC_AHBPeriph_SDIO + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +#ifdef STM32F10X_CL +/** + * @brief Forces or releases AHB peripheral reset. + * @note This function applies only to STM32 Connectivity line devices. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} +#endif /* STM32F10X_CL */ + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO: specifies the clock source to output. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * @arg RCC_MCO_PLL2CLK: PLL2 clock selected + * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected + * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected + * @arg RCC_MCO_PLL3CLK: PLL3 clock selected + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCCs interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c new file mode 100644 index 0000000..2478e25 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c @@ -0,0 +1,338 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the RTC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup RTC_Private_Defines + * @{ + */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** + * @brief Enters the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CRL_CNF; +} + +/** + * @brief Exits from the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); +} + +/** + * @brief Gets the RTC counter value. + * @param None + * @retval RTC counter value. + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t tmp = 0; + tmp = RTC->CNTL; + return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; +} + +/** + * @brief Sets the RTC counter value. + * @param CounterValue: RTC counter new value. + * @retval None + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC prescaler value. + * @param PrescalerValue: RTC prescaler new value. + * @retval None + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC alarm value. + * @param AlarmValue: RTC alarm new value. + * @retval None + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Gets the RTC divider value. + * @param None + * @retval RTC Divider value. + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** + * @brief Waits until last write operation on RTC registers has finished. + * @note This function must be called before any write to RTC registers. + * @param None + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param None + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one the following values: + * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTCs pending flags. + * @param RTC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after + * an APB reset or an APB Clock stop. + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval None + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the coressponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occured or not. + * @param RTC_IT: specifies the RTC interrupts sources to check. + * This parameter can be one of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval The new state of the RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTCs interrupt pending bits. + * @param RTC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c new file mode 100644 index 0000000..75008e1 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c @@ -0,0 +1,798 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parametre can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIOs interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c new file mode 100644 index 0000000..f71f93c --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c @@ -0,0 +1,907 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if(((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLOCK_SRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLOCK_SRC; + } + + /* Check the I2S clock source configuration depending on the Device: + Only Connectivity line devices have the PLL3 VCO clock */ +#ifdef STM32F10X_CL + if((RCC->CFGR2 & tmp) != 0) + { + /* Get the configuration bits of RCC PLL3 multiplier */ + tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); + + /* Get the value of the PLL3 multiplier */ + if((tmp > 5) && (tmp < 15)) + { + /* Multplier is between 8 and 14 (value 15 is forbidden) */ + tmp += 2; + } + else + { + if (tmp == 15) + { + /* Multiplier is 20 */ + tmp = 20; + } + } + /* Get the PREDIV2 value */ + sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); + + /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ + sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); + } + else + { + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + } +#else /* STM32F10X_HD */ + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; +#endif /* STM32F10X_CL */ + + /* Compute the Real divider depending on the MCLK output state with a flaoting point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flaoting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data : Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the transfered bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR intetrrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c new file mode 100644 index 0000000..74561e7 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c @@ -0,0 +1,2888 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the TIM firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @defgroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval None + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| + (TIMx == TIM16)|| (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + } + else + { + assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Configures the TIMxs DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMxs DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 + * to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx interrnal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 + * to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @param TIM_TS_ITR0: Internal Trigger 0 + * @param TIM_TS_ITR1: Internal Trigger 1 + * @param TIM_TS_ITR2: Internal Trigger 2 + * @param TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 + * to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_Set << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_Set << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM Ouput Compare Mode. + * @note This function disables the selected channel before changing the Ouput + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This paramter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_Offset; + + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables the TIMxs Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @brief Selects the TIMxs One Pulse Mode. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST7_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); + } + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); + } + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c new file mode 100644 index 0000000..c791b72 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c @@ -0,0 +1,1055 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the USART firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/** @defgroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Defines + * @{ + */ + +#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ +#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ + +#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ + +#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ +#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USARTs DMA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @note The DMA mode is not available for UART5 except in the STM32 + * High density value line devices(STM32F10X_HD_VL). + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USARTs LIN mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @note The guard time bits are not available for UART4 and UART5. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USARTs Smart Card mode. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/** + * @brief Enables or disables the USARTs Half Duplex communication. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= CR1_OVER8_Set; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= CR1_OVER8_Reset; + } +} + +/** + * @brief Enables or disables the USART's one bit sampling methode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= CR3_ONEBITE_Set; + } + else + { + /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= CR3_ONEBITE_Reset; + } +} + +/** + * @brief Configures the USARTs IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USARTs IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTxs interrupt pending bits. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c new file mode 100644 index 0000000..7d44b09 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file provides all the WWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @defgroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/stm32f10x_conf.h b/Libraries/stm32f10x_conf.h new file mode 100644 index 0000000..7189f0d --- /dev/null +++ b/Libraries/stm32f10x_conf.h @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief Library configuration file. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ + #include "stm32f10x_adc.h" + #include "stm32f10x_bkp.h" + #include "stm32f10x_can.h" + #include "stm32f10x_cec.h" + #include "stm32f10x_crc.h" + #include "stm32f10x_dac.h" + #include "stm32f10x_dbgmcu.h" +#include "stm32f10x_dma.h" +#include "stm32f10x_exti.h" +#include "stm32f10x_flash.h" +#include "stm32f10x_fsmc.h" +#include "stm32f10x_gpio.h" +#include "stm32f10x_i2c.h" + #include "stm32f10x_iwdg.h" + #include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + #include "stm32f10x_rtc.h" + #include "stm32f10x_sdio.h" +#include "stm32f10x_spi.h" + #include "stm32f10x_tim.h" +#include "stm32f10x_usart.h" + #include "stm32f10x_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/stm32f10x_it.c b/Libraries/stm32f10x_it.c new file mode 100644 index 0000000..fbd3688 --- /dev/null +++ b/Libraries/stm32f10x_it.c @@ -0,0 +1,161 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_it.h" + + +/** @addtogroup STM32F10x_StdPeriph_Template + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F10x Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f10x_xx.s). */ +/******************************************************************************/ + + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/stm32f10x_it.h b/Libraries/stm32f10x_it.h new file mode 100644 index 0000000..2e660a1 --- /dev/null +++ b/Libraries/stm32f10x_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IT_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/system_stm32f10x.c b/Libraries/system_stm32f10x.c new file mode 100644 index 0000000..94e35b8 --- /dev/null +++ b/Libraries/system_stm32f10x.c @@ -0,0 +1,1033 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note None + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/RVMDK/DebugConfig/CreativeST_VC_STM32F100RC.dbgconf b/RVMDK/DebugConfig/CreativeST_VC_STM32F100RC.dbgconf new file mode 100644 index 0000000..756c47b --- /dev/null +++ b/RVMDK/DebugConfig/CreativeST_VC_STM32F100RC.dbgconf @@ -0,0 +1,85 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM15_STOP +// Timer 15 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM16_STOP +// Timer 16 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM17_STOP +// Timer 17 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/RVMDK/DebugConfig/CreativeST_VC_STM32F100RC_1.0.0.dbgconf b/RVMDK/DebugConfig/CreativeST_VC_STM32F100RC_1.0.0.dbgconf new file mode 100644 index 0000000..756c47b --- /dev/null +++ b/RVMDK/DebugConfig/CreativeST_VC_STM32F100RC_1.0.0.dbgconf @@ -0,0 +1,85 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM15_STOP +// Timer 15 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM16_STOP +// Timer 16 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM17_STOP +// Timer 17 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/RVMDK/JLink Regs CM3.txt b/RVMDK/JLink Regs CM3.txt new file mode 100644 index 0000000..08327ff --- /dev/null +++ b/RVMDK/JLink Regs CM3.txt @@ -0,0 +1,32 @@ +0: R0: 0x00 +1: R1: 0x01 +2: R2: 0x02 +3: R3: 0x03 +4: R4: 0x04 +5: R5: 0x05 +6: R6: 0x06 +7: R7: 0x07 +8: R8: 0x08 +9: R9: 0x09 +10: R10: 0x0a +11: R11: 0x0b +12: R12: 0x0c +13: R13: 0x0d +14: R14: 0x0e +15: R15: 0x0f +16: XPSR: 0x10 +17: MSP: 0x11 +18: PSP: 0x12 +19: RAZ: 0x13 +20: CFBP: 0x14 +21: APSR: 0x15 +22: EPSR: 0x16 +23: IPSR: 0x17 +24: PRIMASK: 0x18 +25: BASEPRI: 0x19 +26: FAULTMASK: 0x1a +27: CONTROL: 0x1b +28: BASEPRI_MAX: 0x1c +29: IAPSR: 0x1d +30: EAPSR: 0x1e +31: IEPSR: 0x1f diff --git a/RVMDK/JLinkLog.txt b/RVMDK/JLinkLog.txt new file mode 100644 index 0000000..5c0aaed --- /dev/null +++ b/RVMDK/JLinkLog.txt @@ -0,0 +1,1231 @@ + +TCCA0 000:449 SEGGER J-Link V5.12 Log File (0015ms, 0321ms total) +TCCA0 000:449 DLL Compiled: Mar 30 2016 17:28:31 (0015ms, 0321ms total) +TCCA0 000:449 Logging started @ 2019-11-14 12:29 (0015ms, 0321ms total) +TCCA0 000:464 JLINK_SetWarnOutHandler(...) (0000ms, 0321ms total) +TCCA0 000:464 JLINK_OpenEx(...) +Firmware: J-Link ARM-OB STM32 compiled Aug 22 2012 19:52:04 +Hardware: V7.00 +S/N: 20090928 +Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull returns O.K. (0288ms, 0609ms total) +TCCA0 000:752 JLINK_SetErrorOutHandler(...) (0000ms, 0609ms total) +TCCA0 000:752 JLINK_ExecCommand("ProjectFile = "E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\JLinkSettings.ini"", ...) returns 0x00 (0016ms, 0625ms total) +TCCA0 000:781 JLINK_ExecCommand("Device = STM32F100RC", ...)Device "STM32F100RC" selected. returns 0x00 (0036ms, 0661ms total) +TCCA0 000:817 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0661ms total) +TCCA0 000:817 JLINK_GetHardwareVersion() returns 0x11170 (0000ms, 0661ms total) +TCCA0 000:817 JLINK_GetDLLVersion() returns 51200 (0000ms, 0661ms total) +TCCA0 000:817 JLINK_GetFirmwareString(...) (0000ms, 0661ms total) +TCCA0 000:840 JLINK_GetDLLVersion() returns 51200 (0000ms, 0661ms total) +TCCA0 000:840 JLINK_GetCompileDateTime() (0000ms, 0661ms total) +TCCA0 000:846 JLINK_GetFirmwareString(...) (0000ms, 0661ms total) +TCCA0 000:849 JLINK_GetHardwareVersion() returns 0x11170 (0000ms, 0661ms total) +TCCA0 000:864 JLINK_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0003ms, 0664ms total) +TCCA0 000:867 JLINK_SetSpeed(5000) (0001ms, 0665ms total) +TCCA0 000:868 JLINK_GetId() >0x108 TIF>Found SWD-DP with ID 0x1BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> + >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x108 TIF>Found SWD-DP with ID 0x1BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> + >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>Found Cortex-M3 r1p1, Little endian. -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) + -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 001BB000 SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 001BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) + -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 000BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 001BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 001BB923 TPIU-Lite -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0) +ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 101BB924 ETM-M3 >0x0D TIF> >0x21 TIF> returns 0x1BA01477 (0193ms, 0858ms total) +TCCA0 001:062 JLINK_GetDLLVersion() returns 51200 (0000ms, 0858ms total) +TCCA0 001:062 JLINK_CORE_GetFound() returns 0x30000FF (0000ms, 0858ms total) +TCCA0 001:062 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x101) -- Value=0xE0041000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x102) -- Value=0x00000000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x103) -- Value=0xE0040000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x104) -- Value=0xE0000000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x105) -- Value=0xE0001000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x106) -- Value=0xE0002000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x107) -- Value=0xE000E000 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_GetDebugInfo(0x10C) -- Value=0xE000EDF0 returns 0x00 (0000ms, 0858ms total) +TCCA0 001:068 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41 returns 0x01 (0002ms, 0860ms total) +TCCA0 001:070 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0860ms total) +TCCA0 001:070 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) >0x35 TIF> -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0025ms, 0885ms total) +TCCA0 001:096 JLINK_Halt() returns 0x00 (0000ms, 0885ms total) +TCCA0 001:096 JLINK_IsHalted() returns TRUE (0000ms, 0885ms total) +TCCA0 001:096 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 0886ms total) +TCCA0 001:097 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0001ms, 0887ms total) +TCCA0 001:098 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0002ms, 0889ms total) +TCCA0 001:114 JLINK_GetHWStatus(...) returns 0x00 (0001ms, 0890ms total) +TCCA0 001:129 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 0890ms total) +TCCA0 001:129 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 0890ms total) +TCCA0 001:129 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 0890ms total) +TCCA0 001:138 JLINK_GetSpeed() returns 0xFA0 (0000ms, 0890ms total) +TCCA0 001:159 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0001ms, 0891ms total) +TCCA0 001:160 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0001ms, 0892ms total) +TCCA0 001:161 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0002ms, 0894ms total) +TCCA0 001:163 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0895ms total) +TCCA0 001:164 JLINK_Halt() returns 0x00 (0000ms, 0895ms total) +TCCA0 001:164 JLINK_IsHalted() returns TRUE (0000ms, 0895ms total) +TCCA0 001:203 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0005ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0900ms total) +TCCA0 001:208 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000001 (0001ms, 0901ms total) +TCCA0 001:209 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0013ms, 0914ms total) +TCCA0 001:222 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0919ms total) +TCCA0 001:227 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0914ms total) +TCCA0 001:227 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:227 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:228 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0914ms total) +TCCA0 001:229 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 0915ms total) +TCCA0 001:229 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 0921ms total) +TCCA0 001:235 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0926ms total) +TCCA0 001:240 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:240 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0921ms total) +TCCA0 001:241 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0922ms total) +TCCA0 001:241 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0922ms total) +TCCA0 001:241 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0922ms total) +TCCA0 001:241 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 0922ms total) +TCCA0 001:241 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0925ms total) +TCCA0 001:244 JLINK_IsHalted() returns FALSE (0001ms, 0926ms total) +TCCA0 001:322 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0929ms total) +TCCA0 001:326 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0925ms total) +TCCA0 001:326 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0001ms, 0926ms total) +TCCA0 001:327 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0926ms total) +TCCA0 001:329 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 0927ms total) +TCCA0 001:330 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000004 (0000ms, 0927ms total) +TCCA0 001:330 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 0931ms total) +TCCA0 001:334 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0936ms total) +TCCA0 001:339 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 0931ms total) +TCCA0 001:339 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0934ms total) +TCCA0 001:342 JLINK_IsHalted() returns FALSE (0001ms, 0935ms total) +TCCA0 001:350 JLINK_IsHalted() returns FALSE (0001ms, 0935ms total) +TCCA0 001:352 JLINK_IsHalted() returns FALSE (0001ms, 0935ms total) +TCCA0 001:354 JLINK_IsHalted() returns FALSE (0001ms, 0935ms total) +TCCA0 001:356 JLINK_IsHalted() returns FALSE (0001ms, 0935ms total) +TCCA0 001:362 JLINK_IsHalted() returns FALSE (0001ms, 0935ms total) +TCCA0 001:364 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0938ms total) +TCCA0 001:368 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0934ms total) +TCCA0 001:368 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:368 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 0934ms total) +TCCA0 001:369 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 0938ms total) +TCCA0 001:373 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0942ms total) +TCCA0 001:377 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0938ms total) +TCCA0 001:377 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 0938ms total) +TCCA0 001:377 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0938ms total) +TCCA0 001:377 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 0938ms total) +TCCA0 001:377 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0938ms total) +TCCA0 001:377 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0001ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 0939ms total) +TCCA0 001:378 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0942ms total) +TCCA0 001:381 JLINK_IsHalted() returns FALSE (0001ms, 0943ms total) +TCCA0 001:386 JLINK_IsHalted() returns FALSE (0001ms, 0943ms total) +TCCA0 001:393 JLINK_IsHalted() returns FALSE (0001ms, 0943ms total) +TCCA0 001:395 JLINK_IsHalted() returns FALSE (0001ms, 0943ms total) +TCCA0 001:397 JLINK_IsHalted() returns FALSE (0001ms, 0943ms total) +TCCA0 001:399 JLINK_IsHalted() returns FALSE (0001ms, 0943ms total) +TCCA0 001:401 JLINK_IsHalted() returns FALSE (0001ms, 0943ms total) +TCCA0 001:403 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0946ms total) +TCCA0 001:407 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0943ms total) +TCCA0 001:408 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0943ms total) +TCCA0 001:408 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 0944ms total) +TCCA0 001:409 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0944ms total) +TCCA0 001:409 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0944ms total) +TCCA0 001:409 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0944ms total) +TCCA0 001:409 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0944ms total) +TCCA0 001:409 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0944ms total) +TCCA0 001:409 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 0944ms total) +TCCA0 001:409 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 0948ms total) +TCCA0 001:413 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0953ms total) +TCCA0 001:418 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 0948ms total) +TCCA0 001:418 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0951ms total) +TCCA0 001:421 JLINK_IsHalted() returns FALSE (0001ms, 0952ms total) +TCCA0 001:425 JLINK_IsHalted() returns FALSE (0001ms, 0952ms total) +TCCA0 001:427 JLINK_IsHalted() returns FALSE (0001ms, 0952ms total) +TCCA0 001:429 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:430 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:431 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:432 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:433 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:434 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:435 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:438 JLINK_IsHalted() returns FALSE (0001ms, 0952ms total) +TCCA0 001:440 JLINK_IsHalted() returns FALSE (0000ms, 0951ms total) +TCCA0 001:441 JLINK_IsHalted() returns FALSE (0001ms, 0952ms total) +TCCA0 001:443 JLINK_IsHalted() returns FALSE (0001ms, 0952ms total) +TCCA0 001:445 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 0959ms total) +TCCA0 001:453 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0951ms total) +TCCA0 001:453 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:453 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0951ms total) +TCCA0 001:454 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 0951ms total) +TCCA0 001:454 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 0955ms total) +TCCA0 001:458 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0959ms total) +TCCA0 001:462 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0955ms total) +TCCA0 001:462 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 0955ms total) +TCCA0 001:462 JLINK_ReadReg(R0) returns 0x00000001 (0001ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0956ms total) +TCCA0 001:463 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 0956ms total) +TCCA0 001:463 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 0962ms total) +TCCA0 001:469 JLINK_IsHalted() returns FALSE (0001ms, 0963ms total) +TCCA0 001:477 JLINK_IsHalted() returns FALSE (0001ms, 0963ms total) +TCCA0 001:479 JLINK_IsHalted() returns FALSE (0001ms, 0963ms total) +TCCA0 001:481 JLINK_IsHalted() returns FALSE (0001ms, 0963ms total) +TCCA0 001:488 JLINK_IsHalted() returns FALSE (0001ms, 0963ms total) +TCCA0 001:490 JLINK_IsHalted() returns FALSE (0001ms, 0963ms total) +TCCA0 001:492 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0966ms total) +TCCA0 001:496 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0962ms total) +TCCA0 001:496 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0001ms, 0963ms total) +TCCA0 001:497 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0963ms total) +TCCA0 001:502 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0001ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0964ms total) +TCCA0 001:503 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 0964ms total) +TCCA0 001:503 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0967ms total) +TCCA0 001:506 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0972ms total) +TCCA0 001:511 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0967ms total) +TCCA0 001:511 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 0967ms total) +TCCA0 001:511 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 0971ms total) +TCCA0 001:515 JLINK_IsHalted() returns FALSE (0001ms, 0972ms total) +TCCA0 001:521 JLINK_IsHalted() returns FALSE (0001ms, 0972ms total) +TCCA0 001:523 JLINK_IsHalted() returns FALSE (0001ms, 0972ms total) +TCCA0 001:525 JLINK_IsHalted() returns FALSE (0001ms, 0972ms total) +TCCA0 001:527 JLINK_IsHalted() returns FALSE (0001ms, 0972ms total) +TCCA0 001:535 JLINK_IsHalted() returns FALSE (0001ms, 0972ms total) +TCCA0 001:537 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0975ms total) +TCCA0 001:541 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0971ms total) +TCCA0 001:541 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 0971ms total) +TCCA0 001:541 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0971ms total) +TCCA0 001:546 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0972ms total) +TCCA0 001:546 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 0972ms total) +TCCA0 001:546 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0975ms total) +TCCA0 001:549 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0980ms total) +TCCA0 001:554 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0975ms total) +TCCA0 001:554 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0976ms total) +TCCA0 001:555 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0976ms total) +TCCA0 001:555 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0976ms total) +TCCA0 001:555 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0976ms total) +TCCA0 001:555 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000F (0000ms, 0976ms total) +TCCA0 001:555 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0979ms total) +TCCA0 001:558 JLINK_IsHalted() returns FALSE (0001ms, 0980ms total) +TCCA0 001:566 JLINK_IsHalted() returns FALSE (0001ms, 0980ms total) +TCCA0 001:568 JLINK_IsHalted() returns FALSE (0001ms, 0980ms total) +TCCA0 001:570 JLINK_IsHalted() returns FALSE (0001ms, 0980ms total) +TCCA0 001:572 JLINK_IsHalted() returns FALSE (0001ms, 0980ms total) +TCCA0 001:574 JLINK_IsHalted() returns FALSE (0001ms, 0980ms total) +TCCA0 001:576 JLINK_IsHalted() returns FALSE (0004ms, 0983ms total) +TCCA0 001:583 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0984ms total) +TCCA0 001:588 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R0, 0x00000001) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0979ms total) +TCCA0 001:588 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 0980ms total) +TCCA0 001:589 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 0986ms total) +TCCA0 001:595 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 0991ms total) +TCCA0 001:600 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0986ms total) +TCCA0 001:600 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 0986ms total) +TCCA0 001:600 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0986ms total) +TCCA0 001:662 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0005ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R2, 0x00000002) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0991ms total) +TCCA0 001:667 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000011 (0002ms, 0993ms total) +TCCA0 001:669 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 1000ms total) +TCCA0 001:676 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1005ms total) +TCCA0 001:681 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1000ms total) +TCCA0 001:681 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 1000ms total) +TCCA0 001:681 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1000ms total) +TCCA0 001:681 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 60 09 00 20 45 01 00 08 19 11 00 08 81 10 00 08 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 1013ms total) +TCCA0 001:694 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 1018ms total) +TCCA0 001:699 JLINK_IsHalted() returns FALSE (0002ms, 1020ms total) +TCCA0 001:714 JLINK_IsHalted() returns FALSE (0001ms, 1019ms total) +TCCA0 001:721 JLINK_IsHalted() returns FALSE (0001ms, 1019ms total) +TCCA0 001:723 JLINK_IsHalted() returns FALSE (0001ms, 1019ms total) +TCCA0 001:725 JLINK_IsHalted() returns FALSE (0001ms, 1019ms total) +TCCA0 001:727 JLINK_IsHalted() returns FALSE (0001ms, 1019ms total) +TCCA0 001:729 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1023ms total) +TCCA0 001:734 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1018ms total) +TCCA0 001:734 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 1018ms total) +TCCA0 001:734 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1018ms total) +TCCA0 001:737 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 3C D1 43 48 00 78 01 28 1B D1 41 48 00 78 40 1C ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0012ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:749 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1030ms total) +TCCA0 001:750 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 1031ms total) +TCCA0 001:750 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 1038ms total) +TCCA0 001:757 JLINK_IsHalted() returns FALSE (0002ms, 1040ms total) +TCCA0 001:761 JLINK_IsHalted() returns FALSE (0003ms, 1041ms total) +TCCA0 001:765 JLINK_IsHalted() returns FALSE (0001ms, 1039ms total) +TCCA0 001:767 JLINK_IsHalted() returns FALSE (0001ms, 1039ms total) +TCCA0 001:769 JLINK_IsHalted() returns FALSE (0001ms, 1039ms total) +TCCA0 001:771 JLINK_IsHalted() returns FALSE (0001ms, 1039ms total) +TCCA0 001:773 JLINK_IsHalted() returns FALSE (0001ms, 1039ms total) +TCCA0 001:775 JLINK_IsHalted() returns FALSE (0001ms, 1039ms total) +TCCA0 001:783 JLINK_IsHalted() returns FALSE (0001ms, 1040ms total) +TCCA0 001:785 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1044ms total) +TCCA0 001:790 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1039ms total) +TCCA0 001:790 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 1039ms total) +TCCA0 001:790 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1039ms total) +TCCA0 001:791 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 08 80 00 20 A9 49 08 70 11 21 A9 48 00 F0 01 FB ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0012ms, 1051ms total) +TCCA0 001:803 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:803 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:803 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:803 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000014 (0000ms, 1051ms total) +TCCA0 001:804 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1055ms total) +TCCA0 001:808 JLINK_IsHalted() returns FALSE (0002ms, 1057ms total) +TCCA0 001:820 JLINK_IsHalted() returns FALSE (0001ms, 1056ms total) +TCCA0 001:822 JLINK_IsHalted() returns FALSE (0001ms, 1056ms total) +TCCA0 001:824 JLINK_IsHalted() returns FALSE (0001ms, 1056ms total) +TCCA0 001:826 JLINK_IsHalted() returns FALSE (0002ms, 1057ms total) +TCCA0 001:832 JLINK_IsHalted() returns FALSE (0001ms, 1056ms total) +TCCA0 001:834 JLINK_IsHalted() returns FALSE (0001ms, 1056ms total) +TCCA0 001:836 JLINK_IsHalted() returns FALSE (0001ms, 1056ms total) +TCCA0 001:838 JLINK_IsHalted() returns FALSE (0001ms, 1056ms total) +TCCA0 001:840 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 1061ms total) +TCCA0 001:846 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1055ms total) +TCCA0 001:846 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 1055ms total) +TCCA0 001:846 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1055ms total) +TCCA0 001:847 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 30 49 88 71 26 48 C1 79 2E 48 C1 71 24 48 01 7A ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:860 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1068ms total) +TCCA0 001:861 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 1069ms total) +TCCA0 001:861 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 1072ms total) +TCCA0 001:864 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:868 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:870 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:872 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:874 JLINK_IsHalted() returns FALSE (0000ms, 1072ms total) +TCCA0 001:879 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:881 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:883 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:885 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:887 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:889 JLINK_IsHalted() returns FALSE (0001ms, 1073ms total) +TCCA0 001:891 JLINK_IsHalted() returns FALSE (0004ms, 1076ms total) +TCCA0 001:900 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1077ms total) +TCCA0 001:905 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1072ms total) +TCCA0 001:905 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 1072ms total) +TCCA0 001:905 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1072ms total) +TCCA0 001:906 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 34 DD 54 68 00 20 2E E0 00 F1 08 0C 4F F0 01 08 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0016ms, 1088ms total) +TCCA0 001:922 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 1088ms total) +TCCA0 001:922 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 1089ms total) +TCCA0 001:923 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1093ms total) +TCCA0 001:927 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:942 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:944 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:946 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:948 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:952 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:954 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:956 JLINK_IsHalted() returns FALSE (0001ms, 1094ms total) +TCCA0 001:958 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1098ms total) +TCCA0 001:963 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1093ms total) +TCCA0 001:963 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 1093ms total) +TCCA0 001:963 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1093ms total) +TCCA0 001:967 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 20 46 00 F0 13 FF 70 22 27 21 20 46 00 F0 0E FF ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0012ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:979 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1105ms total) +TCCA0 001:980 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000017 (0000ms, 1106ms total) +TCCA0 001:980 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 1112ms total) +TCCA0 001:986 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 001:991 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 001:993 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 001:995 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 002:002 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 002:004 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 002:006 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 002:008 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 002:010 JLINK_IsHalted() returns FALSE (0001ms, 1113ms total) +TCCA0 002:019 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1117ms total) +TCCA0 002:024 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1112ms total) +TCCA0 002:024 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 1112ms total) +TCCA0 002:024 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1112ms total) +TCCA0 002:025 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: FF 22 E2 21 20 46 00 F0 11 FD 10 BD A4 35 00 08 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0012ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 1124ms total) +TCCA0 002:038 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 1129ms total) +TCCA0 002:043 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:046 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:053 JLINK_IsHalted() returns FALSE (0002ms, 1131ms total) +TCCA0 002:056 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:058 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:060 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:063 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:065 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:067 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:069 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:071 JLINK_IsHalted() returns FALSE (0001ms, 1130ms total) +TCCA0 002:073 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 1138ms total) +TCCA0 002:082 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1129ms total) +TCCA0 002:083 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 1130ms total) +TCCA0 002:083 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1130ms total) +TCCA0 002:083 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: FF 22 E2 21 20 46 00 F0 11 FB 10 BD D1 35 00 08 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R0, 0x08001C00) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:096 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1143ms total) +TCCA0 002:097 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1144ms total) +TCCA0 002:097 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1144ms total) +TCCA0 002:097 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1144ms total) +TCCA0 002:097 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1144ms total) +TCCA0 002:097 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1144ms total) +TCCA0 002:097 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1144ms total) +TCCA0 002:097 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 1144ms total) +TCCA0 002:097 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1148ms total) +TCCA0 002:101 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:108 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:110 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:112 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:114 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:116 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:118 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:120 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:128 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:130 JLINK_IsHalted() returns FALSE (0001ms, 1149ms total) +TCCA0 002:132 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1153ms total) +TCCA0 002:137 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1148ms total) +TCCA0 002:137 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 1148ms total) +TCCA0 002:137 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1148ms total) +TCCA0 002:137 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 10 B5 04 46 03 22 23 21 20 46 00 F0 0F F9 05 23 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1161ms total) +TCCA0 002:150 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0001ms, 1162ms total) +TCCA0 002:151 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1162ms total) +TCCA0 002:151 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1162ms total) +TCCA0 002:151 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001A (0000ms, 1162ms total) +TCCA0 002:151 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1166ms total) +TCCA0 002:155 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:160 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:162 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:164 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:166 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:169 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:171 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:173 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:175 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:177 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:179 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:181 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:183 JLINK_IsHalted() returns FALSE (0001ms, 1167ms total) +TCCA0 002:192 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 1172ms total) +TCCA0 002:198 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1166ms total) +TCCA0 002:198 JLINK_ClrBPEx(BPHandle = 0x0000001A) returns 0x00 (0000ms, 1166ms total) +TCCA0 002:198 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1166ms total) +TCCA0 002:198 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: E0 22 50 61 50 17 0F 22 00 28 07 DA 13 07 1D 0E ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R0, 0x08002400) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1179ms total) +TCCA0 002:211 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 1180ms total) +TCCA0 002:212 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1180ms total) +TCCA0 002:212 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1180ms total) +TCCA0 002:212 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1180ms total) +TCCA0 002:212 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001B (0000ms, 1180ms total) +TCCA0 002:212 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 1186ms total) +TCCA0 002:218 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:222 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:224 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:226 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:228 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:235 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:237 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:239 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:241 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:243 JLINK_IsHalted() returns FALSE (0001ms, 1187ms total) +TCCA0 002:248 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 1192ms total) +TCCA0 002:254 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1186ms total) +TCCA0 002:254 JLINK_ClrBPEx(BPHandle = 0x0000001B) returns 0x00 (0000ms, 1186ms total) +TCCA0 002:254 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1186ms total) +TCCA0 002:254 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 70 BD 00 00 10 B5 86 B0 00 24 14 21 01 A8 FD F7 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1199ms total) +TCCA0 002:267 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001C (0000ms, 1199ms total) +TCCA0 002:267 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1203ms total) +TCCA0 002:271 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:276 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:278 JLINK_IsHalted() returns FALSE (0002ms, 1205ms total) +TCCA0 002:281 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:283 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:285 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:287 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:289 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:291 JLINK_IsHalted() returns FALSE (0001ms, 1204ms total) +TCCA0 002:302 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1208ms total) +TCCA0 002:307 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1203ms total) +TCCA0 002:307 JLINK_ClrBPEx(BPHandle = 0x0000001C) returns 0x00 (0000ms, 1203ms total) +TCCA0 002:307 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1203ms total) +TCCA0 002:308 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 02 D0 1A 4B 98 42 04 D1 4F F6 8F 73 1A 40 4B 88 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R0, 0x08002C00) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1216ms total) +TCCA0 002:321 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001D (0000ms, 1216ms total) +TCCA0 002:321 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 1222ms total) +TCCA0 002:327 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:332 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:334 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:336 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:338 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:340 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:347 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:349 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:351 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:353 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:356 JLINK_IsHalted() returns FALSE (0001ms, 1223ms total) +TCCA0 002:358 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1227ms total) +TCCA0 002:363 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1222ms total) +TCCA0 002:363 JLINK_ClrBPEx(BPHandle = 0x0000001D) returns 0x00 (0000ms, 1222ms total) +TCCA0 002:363 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1222ms total) +TCCA0 002:363 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 00 26 00 25 00 20 40 F6 6A 17 B9 42 00 D1 00 BF ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1235ms total) +TCCA0 002:377 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001E (0000ms, 1235ms total) +TCCA0 002:377 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 1240ms total) +TCCA0 002:382 JLINK_IsHalted() returns FALSE (0001ms, 1241ms total) +TCCA0 002:389 JLINK_IsHalted() returns FALSE (0001ms, 1241ms total) +TCCA0 002:391 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:392 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:393 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:394 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:395 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:396 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:397 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:398 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:399 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:400 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:407 JLINK_IsHalted() returns FALSE (0001ms, 1241ms total) +TCCA0 002:409 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:410 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:411 JLINK_IsHalted() returns FALSE (0000ms, 1240ms total) +TCCA0 002:412 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 1249ms total) +TCCA0 002:421 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1240ms total) +TCCA0 002:421 JLINK_ClrBPEx(BPHandle = 0x0000001E) returns 0x00 (0000ms, 1240ms total) +TCCA0 002:421 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1240ms total) +TCCA0 002:422 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 32 2E 34 2D 32 30 31 39 30 39 30 36 0A 00 00 00 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0013ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R0, 0x08003400) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R1, 0x000002B8) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1253ms total) +TCCA0 002:435 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001F (0000ms, 1253ms total) +TCCA0 002:435 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 1261ms total) +TCCA0 002:443 JLINK_IsHalted() returns FALSE (0001ms, 1262ms total) +TCCA0 002:458 JLINK_IsHalted() returns FALSE (0002ms, 1263ms total) +TCCA0 002:461 JLINK_IsHalted() returns FALSE (0001ms, 1262ms total) +TCCA0 002:463 JLINK_IsHalted() returns FALSE (0003ms, 1264ms total) +TCCA0 002:470 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1266ms total) +TCCA0 002:475 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_ClrBPEx(BPHandle = 0x0000001F) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R0, 0x00000002) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R1, 0x000002B8) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000020 (0000ms, 1261ms total) +TCCA0 002:475 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 1267ms total) +TCCA0 002:481 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1272ms total) +TCCA0 002:486 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1267ms total) +TCCA0 002:486 JLINK_ClrBPEx(BPHandle = 0x00000020) returns 0x00 (0000ms, 1267ms total) +TCCA0 002:486 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1267ms total) +TCCA0 002:542 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0005ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R2, 0x00000003) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1272ms total) +TCCA0 002:547 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000021 (0003ms, 1275ms total) +TCCA0 002:550 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1279ms total) +TCCA0 002:554 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 1285ms total) +TCCA0 002:560 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_ClrBPEx(BPHandle = 0x00000021) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R0, 0xFFFFFFFF) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R2, 0x000036B8) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(R15 (PC), 0x20000002) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000022 (0000ms, 1279ms total) +TCCA0 002:560 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1283ms total) +TCCA0 002:564 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:582 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:584 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:586 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:588 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:595 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:597 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:599 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:601 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:603 JLINK_IsHalted() returns FALSE (0003ms, 1286ms total) +TCCA0 002:607 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:609 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:611 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:613 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:615 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:617 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:619 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:625 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:627 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:629 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:631 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:633 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:635 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:638 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:640 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:642 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:644 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:646 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:648 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:650 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:657 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:659 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:661 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:663 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:665 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:667 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:676 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:678 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:680 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:682 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:688 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:690 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:692 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:694 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:696 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:698 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:700 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:707 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:709 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:711 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:713 JLINK_IsHalted() returns FALSE (0002ms, 1285ms total) +TCCA0 002:716 JLINK_IsHalted() returns FALSE (0001ms, 1284ms total) +TCCA0 002:718 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 1288ms total) +TCCA0 002:723 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1283ms total) +TCCA0 002:723 JLINK_ClrBPEx(BPHandle = 0x00000022) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:723 JLINK_ReadReg(R0) returns 0x3DDE0889 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R0, 0x00000003) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R2, 0x000036B8) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000023 (0000ms, 1283ms total) +TCCA0 002:725 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 1287ms total) +TCCA0 002:729 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 1296ms total) +TCCA0 002:738 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1287ms total) +TCCA0 002:738 JLINK_ClrBPEx(BPHandle = 0x00000023) returns 0x00 (0000ms, 1287ms total) +TCCA0 002:738 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1287ms total) +TCCA0 002:796 JLINK_WriteMem(0x20000000, 0x0002 Bytes, ...) - Data: FE E7 -- CPU_WriteMem(2 bytes @ 0x20000000) returns 0x02 (0001ms, 1288ms total) +TCCA0 002:797 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1288ms total) +TCCA0 002:797 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) >0x35 TIF> -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0025ms, 1313ms total) +TCCA0 002:822 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0011ms, 1324ms total) +TCCA0 002:864 JLINK_Close() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000201C) >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> (0014ms, 1338ms total) +TCCA0 002:864 (0014ms, 1338ms total) +TCCA0 002:864 Closed (0014ms, 1338ms total) diff --git a/RVMDK/JLinkSettings.ini b/RVMDK/JLinkSettings.ini new file mode 100644 index 0000000..5516360 --- /dev/null +++ b/RVMDK/JLinkSettings.ini @@ -0,0 +1,17 @@ +[FLASH] +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ADUC7020X62" +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[SWO] +SWOLogFile="" diff --git a/RVMDK/List/Printf.map b/RVMDK/List/Printf.map new file mode 100644 index 0000000..4d75043 --- /dev/null +++ b/RVMDK/List/Printf.map @@ -0,0 +1,1132 @@ +ARM Linker, 5.03 [Build 76] [MDK-ARM Standard] + +============================================================================== + +Section Cross References + + main.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig + main.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_Init) for NVIC_Init + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_DeInit) for RCC_DeInit + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_HSEConfig) for RCC_HSEConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) for RCC_WaitForHSEStartUp + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_HCLKConfig) for RCC_HCLKConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PCLK2Config) for RCC_PCLK2Config + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PCLK1Config) for RCC_PCLK1Config + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PLLConfig) for RCC_PLLConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PLLCmd) for RCC_PLLCmd + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_SYSCLKConfig) for RCC_SYSCLKConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_GetSYSCLKSource) for RCC_GetSYSCLKSource + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + main.o(i.main) refers to main.o(i.RCC_Configuration) for RCC_Configuration + main.o(i.main) refers to main.o(i.NVIC_Configuration) for NVIC_Configuration + main.o(i.main) refers to led.o(i.led_init) for led_init + main.o(i.main) refers to printf.o(i.USART_Configuration) for USART_Configuration + main.o(i.main) refers to usart2.o(i.USART2_Init) for USART2_Init + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_Init) for NRF24L01_Init + main.o(i.main) refers to printfb.o(i.__0printf$bare) for __2printf + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_Check) for NRF24L01_Check + main.o(i.main) refers to dataproc.o(i.Data_Init) for Data_Init + main.o(i.main) refers to delay.o(i.delay_ms) for delay_ms + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_TX_Mode) for NRF24L01_TX_Mode + main.o(i.main) refers to dataproc.o(i.DataProc_1356) for DataProc_1356 + main.o(i.main) refers to dataproc.o(i.DataProc_Nrf24l01) for DataProc_Nrf24l01 + main.o(i.main) refers to dataproc.o(i.DataProc_USART1) for DataProc_USART1 + printf.o(i.SendConsoleByte) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendConsoleData) refers to printf.o(i.SendUartData) for SendUartData + printf.o(i.SendConsoleStr) refers to printf.o(i.SendUartStr) for SendUartStr + printf.o(i.SendUartByte) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.SendUartByte) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.SendUartData) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendUartRStr) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendUartStr) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.USART1_IRQHandler) refers to printf.o(.bss) for USART1_RX_BUF + printf.o(i.USART1_IRQHandler) refers to printf.o(.data) for USART1_RX_CNT + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + printf.o(i.USART3_IRQHandler) refers to printf.o(.bss) for USART3_RX_BUF + printf.o(i.USART3_IRQHandler) refers to printf.o(.data) for USART3_RX_CNT + printf.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + printf.o(i.USART_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + printf.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + printf.o(i.Usart1_SendData) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.Usart1_SendData) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.fputc) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + led.o(i.led_init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + usart2.o(i.USART2_IRQHandler) refers to usart2.o(.bss) for USART2_RX_BUF + usart2.o(i.USART2_IRQHandler) refers to usart2.o(.data) for USART2_RX_CNT + usart2.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + usart2.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + usart2.o(i.USART2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + nrf24l01.o(i.NRF24L01_Check) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_Check) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_Check) refers to nrf24l01.o(i.NRF24L01_Read_Buf) for NRF24L01_Read_Buf + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + nrf24l01.o(i.NRF24L01_Init) refers to spi.o(i.SPI2_Init) for SPI2_Init + nrf24l01.o(i.NRF24L01_Init) refers to spi.o(i.SPI1_Init) for SPI1_Init + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(.constdata) for RX_ADDRESS + nrf24l01.o(i.NRF24L01_Read_Buf) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_Read_Reg) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_RxPacket) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Reg) for NRF24L01_Read_Reg + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Buf) for NRF24L01_Read_Buf + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(.constdata) for TX_ADDRESS + nrf24l01.o(i.NRF24L01_TxPacket) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Reg) for NRF24L01_Read_Reg + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_Write_Buf) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_Write_Reg) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + spi.o(i.SPI1_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + spi.o(i.SPI1_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + spi.o(i.SPI1_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.SPI1_Init) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init + spi.o(i.SPI1_Init) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + spi.o(i.SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + spi.o(i.SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + spi.o(i.SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + spi.o(i.SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init + spi.o(i.SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) for SPI_I2S_GetFlagStatus + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_SendData) for SPI_I2S_SendData + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_ReceiveData) for SPI_I2S_ReceiveData + spi.o(i.SPI_SetSpeed) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + dataproc.o(i.DataProc_1356) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + dataproc.o(i.DataProc_1356) refers to delay.o(i.delay_ms) for delay_ms + dataproc.o(i.DataProc_1356) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + dataproc.o(i.DataProc_1356) refers to printf.o(.data) for USART3_RX_CNT + dataproc.o(i.DataProc_1356) refers to printf.o(.bss) for USART3_RX_BUF + dataproc.o(i.DataProc_1356) refers to dataproc.o(.data) for CheckData_1356 + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(i.CheckSum) for CheckSum + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_RxPacket) for NRF24L01_RxPacket + dataproc.o(i.DataProc_Nrf24l01) refers to printf.o(i.SendConsoleByte) for SendConsoleByte + dataproc.o(i.DataProc_Nrf24l01) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(.data) for newIdFlag + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(.bss) for uartSendWrNumOkData + dataproc.o(i.DataProc_USART1) refers to printfb.o(i.__0printf$bare) for __2printf + dataproc.o(i.DataProc_USART1) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_USART1) refers to printf.o(.data) for USART1_RX_CNT + dataproc.o(i.DataProc_USART1) refers to printf.o(.bss) for USART1_RX_BUF + dataproc.o(i.DataProc_USART1) refers to dataproc.o(.bss) for uartRecData + dataproc.o(i.DataProc_USART1) refers to dataproc.o(.data) for idBuf + dataproc.o(i.Data_Init) refers to dataproc.o(.bss) for uartSendData + stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable + stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_usart.o(i.USART_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(i.I2S_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 + system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock + system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(.text) for Reset_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.NMI_Handler) for NMI_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.HardFault_Handler) for HardFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.MemManage_Handler) for MemManage_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.BusFault_Handler) for BusFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.UsageFault_Handler) for UsageFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SVC_Handler) for SVC_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.DebugMon_Handler) for DebugMon_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.PendSV_Handler) for PendSV_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SysTick_Handler) for SysTick_Handler + startup_stm32f10x_hd.o(RESET) refers to printf.o(i.USART1_IRQHandler) for USART1_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to usart2.o(i.USART2_IRQHandler) for USART2_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to printf.o(i.USART3_IRQHandler) for USART3_IRQHandler + startup_stm32f10x_hd.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + startup_stm32f10x_hd.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + printfb.o(i.__0fprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0fprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0printf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._sputc) for _sputc + printfb.o(i.__0vfprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vfprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._sputc) for _sputc + printf0.o(i.__0fprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0fprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0printf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0snprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0snprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0sprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0sprintf$0) refers to printf0.o(i._sputc) for _sputc + printf0.o(i.__0vfprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vfprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._sputc) for _sputc + printf1.o(i.__0fprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0fprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0printf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0snprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0snprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0sprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0sprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i.__0vfprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vfprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf2.o(i.__0fprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0fprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0printf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0snprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0snprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0sprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0sprintf$2) refers to printf2.o(i._sputc) for _sputc + printf2.o(i.__0vfprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vfprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._sputc) for _sputc + printf3.o(i.__0fprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0fprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0printf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0snprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0snprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0sprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0sprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i.__0vfprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vfprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf4.o(i.__0fprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0fprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0printf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0snprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0snprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0sprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0sprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i.__0vfprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vfprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf5.o(i.__0fprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0fprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0printf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0snprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0snprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0sprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0sprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i.__0vfprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vfprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf6.o(i.__0fprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0fprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0printf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0snprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0snprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0sprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0sprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i.__0vfprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vfprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i._printf_core) refers to printf6.o(i._printf_pre_padding) for _printf_pre_padding + printf6.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf6.o(i._printf_core) refers to printf6.o(i._printf_post_padding) for _printf_post_padding + printf7.o(i.__0fprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0fprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0printf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0snprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0snprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0sprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0sprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i.__0vfprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vfprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i._printf_core) refers to printf7.o(i._printf_pre_padding) for _printf_pre_padding + printf7.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf7.o(i._printf_core) refers to printf7.o(i._printf_post_padding) for _printf_post_padding + printf8.o(i.__0fprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0fprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0printf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0snprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0snprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0sprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0sprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i.__0vfprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vfprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i._printf_core) refers to printf8.o(i._printf_pre_padding) for _printf_pre_padding + printf8.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf8.o(i._printf_core) refers to printf8.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i.__0fprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0fprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0fprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0printf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0printf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0printf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0printf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0snprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0snprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0snprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0sprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0sprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0sprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i.__0vfprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vfprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vfprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0vsnprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsnprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsnprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0vsprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i._fp_digits) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._fp_digits) refers to dmul.o(.text) for __aeabi_dmul + printfa.o(i._fp_digits) refers to ddiv.o(.text) for __aeabi_ddiv + printfa.o(i._fp_digits) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + printfa.o(i._fp_digits) refers to dadd.o(.text) for __aeabi_dadd + printfa.o(i._fp_digits) refers to dfixul.o(.text) for __aeabi_d2ulz + printfa.o(i._fp_digits) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_core) refers to printfa.o(i._printf_pre_padding) for _printf_pre_padding + printfa.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers to printfa.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i._printf_core) refers to printfa.o(i._fp_digits) for _fp_digits + printfa.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printfa.o(i._printf_post_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_pre_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._snputc) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._sputc) refers (Special) to iusefp.o(.text) for __I$use$fp + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llsshr.o(.text) for __aeabi_lasr + dadd.o(.text) refers to depilogue.o(.text) for _double_epilogue + dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue + ddiv.o(.text) refers to depilogue.o(.text) for _double_round + dfixul.o(.text) refers to llushr.o(.text) for __aeabi_llsr + dfixul.o(.text) refers to llshl.o(.text) for __aeabi_llsl + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr + + +============================================================================== + +Removing Unused input sections from the image. + + Removing printf.o(i.SendConsoleStr), (20 bytes). + Removing printf.o(i.SendUartRStr), (60 bytes). + Removing printf.o(i.SendUartStr), (60 bytes). + Removing printf.o(i.Usart1_SendData), (44 bytes). + Removing nrf24l01.o(i.NRF24L01_Config), (56 bytes). + Removing nrf24l01.o(i.NRF24L01_TxPacket), (160 bytes). + Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ITConfig), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSEConfig), (52 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_MCOConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKConfig), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes). + Removing stm32f10x_usart.o(i.USART_ClockInit), (34 bytes). + Removing stm32f10x_usart.o(i.USART_ClockStructInit), (12 bytes). + Removing stm32f10x_usart.o(i.USART_DMACmd), (18 bytes). + Removing stm32f10x_usart.o(i.USART_DeInit), (156 bytes). + Removing stm32f10x_usart.o(i.USART_HalfDuplexCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_IrDACmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_IrDAConfig), (18 bytes). + Removing stm32f10x_usart.o(i.USART_LINBreakDetectLengthConfig), (18 bytes). + Removing stm32f10x_usart.o(i.USART_LINCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_OneBitMethodCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_OverSampling8Cmd), (22 bytes). + Removing stm32f10x_usart.o(i.USART_ReceiverWakeUpCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_SendBreak), (10 bytes). + Removing stm32f10x_usart.o(i.USART_SetAddress), (18 bytes). + Removing stm32f10x_usart.o(i.USART_SetGuardTime), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SetPrescaler), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardNACKCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_StructInit), (24 bytes). + Removing stm32f10x_usart.o(i.USART_WakeUpConfig), (18 bytes). + Removing misc.o(i.NVIC_SetVectorTable), (20 bytes). + Removing misc.o(i.NVIC_SystemLPConfig), (32 bytes). + Removing misc.o(i.SysTick_CLKSourceConfig), (40 bytes). + Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (20 bytes). + Removing stm32f10x_gpio.o(i.GPIO_DeInit), (200 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (64 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (32 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinRemapConfig), (144 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes). + Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes). + Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes). + Removing stm32f10x_spi.o(i.I2S_Cmd), (24 bytes). + Removing stm32f10x_spi.o(i.I2S_Init), (232 bytes). + Removing stm32f10x_spi.o(i.I2S_StructInit), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_BiDirectionalLineConfig), (28 bytes). + Removing stm32f10x_spi.o(i.SPI_CalculateCRC), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_DataSizeConfig), (18 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRC), (16 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRCPolynomial), (6 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearFlag), (6 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearITPendingBit), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_DMACmd), (18 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_DeInit), (88 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_GetITStatus), (52 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ITConfig), (32 bytes). + Removing stm32f10x_spi.o(i.SPI_NSSInternalSoftwareConfig), (30 bytes). + Removing stm32f10x_spi.o(i.SPI_SSOutputCmd), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_StructInit), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_TransmitCRC), (10 bytes). + Removing core_cm3.o(.emb_text), (32 bytes). + Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). + Removing system_stm32f10x.o(.data), (20 bytes). + Removing startup_stm32f10x_hd.o(HEAP), (512 bytes). + Removing dadd.o(.text), (334 bytes). + Removing dmul.o(.text), (228 bytes). + Removing ddiv.o(.text), (222 bytes). + Removing dfixul.o(.text), (48 bytes). + Removing cdrcmple.o(.text), (40 bytes). + Removing depilogue.o(.text), (190 bytes). + +90 unused section(s) (total 4470 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfb.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf0.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf1.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf6.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf2.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf3.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf4.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf5.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf7.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf8.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfa.o ABSOLUTE + ../clib/microlib/stdio/streams.c 0x00000000 Number 0 stdout.o ABSOLUTE + ../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 dadd.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 depilogue.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixul.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE + ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s 0x00000000 Number 0 startup_stm32f10x_hd.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c 0x00000000 Number 0 misc.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c 0x00000000 Number 0 stm32f10x_spi.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c 0x00000000 Number 0 stm32f10x_usart.o ABSOLUTE + ..\Libraries\stm32f10x_it.c 0x00000000 Number 0 stm32f10x_it.o ABSOLUTE + ..\Libraries\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + ..\\Libraries\\CMSIS\\CM3\\CoreSupport\\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + ..\bsp\DataProc.c 0x00000000 Number 0 dataproc.o ABSOLUTE + ..\bsp\LED.c 0x00000000 Number 0 led.o ABSOLUTE + ..\bsp\USART2.c 0x00000000 Number 0 usart2.o ABSOLUTE + ..\bsp\delay.c 0x00000000 Number 0 delay.o ABSOLUTE + ..\bsp\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\bsp\nrf24L01.c 0x00000000 Number 0 nrf24l01.o ABSOLUTE + ..\bsp\printf.c 0x00000000 Number 0 printf.o ABSOLUTE + ..\bsp\spi.c 0x00000000 Number 0 spi.o ABSOLUTE + cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + RESET 0x08000000 Section 304 startup_stm32f10x_hd.o(RESET) + .ARM.Collect$$$$00000000 0x08000130 Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x08000130 Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x08000134 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x08000138 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x08000138 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000B 0x08000138 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) + .ARM.Collect$$$$0000000D 0x08000140 Section 0 entry10a.o(.ARM.Collect$$$$0000000D) + .ARM.Collect$$$$0000000F 0x08000140 Section 0 entry11a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00002712 0x08000140 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x08000140 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x08000144 Section 36 startup_stm32f10x_hd.o(.text) + .text 0x08000168 Section 36 init.o(.text) + i.BusFault_Handler 0x0800018c Section 0 stm32f10x_it.o(i.BusFault_Handler) + i.CheckSum 0x08000190 Section 0 dataproc.o(i.CheckSum) + i.DataProc_1356 0x080001b4 Section 0 dataproc.o(i.DataProc_1356) + i.DataProc_Nrf24l01 0x080002b4 Section 0 dataproc.o(i.DataProc_Nrf24l01) + i.DataProc_USART1 0x080003fc Section 0 dataproc.o(i.DataProc_USART1) + i.Data_Init 0x0800082c Section 0 dataproc.o(i.Data_Init) + i.DebugMon_Handler 0x0800092c Section 0 stm32f10x_it.o(i.DebugMon_Handler) + i.GPIO_Init 0x0800092e Section 0 stm32f10x_gpio.o(i.GPIO_Init) + i.GPIO_ResetBits 0x08000a40 Section 0 stm32f10x_gpio.o(i.GPIO_ResetBits) + i.GPIO_SetBits 0x08000a44 Section 0 stm32f10x_gpio.o(i.GPIO_SetBits) + i.HardFault_Handler 0x08000a48 Section 0 stm32f10x_it.o(i.HardFault_Handler) + i.MemManage_Handler 0x08000a4c Section 0 stm32f10x_it.o(i.MemManage_Handler) + i.NMI_Handler 0x08000a50 Section 0 stm32f10x_it.o(i.NMI_Handler) + i.NRF24L01_Check 0x08000a54 Section 0 nrf24l01.o(i.NRF24L01_Check) + i.NRF24L01_Init 0x08000aac Section 0 nrf24l01.o(i.NRF24L01_Init) + i.NRF24L01_RX_Mode 0x08000ba8 Section 0 nrf24l01.o(i.NRF24L01_RX_Mode) + i.NRF24L01_Read_Buf 0x08000c60 Section 0 nrf24l01.o(i.NRF24L01_Read_Buf) + i.NRF24L01_Read_Reg 0x08000cdc Section 0 nrf24l01.o(i.NRF24L01_Read_Reg) + i.NRF24L01_RxPacket 0x08000d3c Section 0 nrf24l01.o(i.NRF24L01_RxPacket) + i.NRF24L01_TX_Mode 0x08000d80 Section 0 nrf24l01.o(i.NRF24L01_TX_Mode) + i.NRF24L01_Write_Buf 0x08000e18 Section 0 nrf24l01.o(i.NRF24L01_Write_Buf) + i.NRF24L01_Write_Reg 0x08000e94 Section 0 nrf24l01.o(i.NRF24L01_Write_Reg) + i.NVIC_Configuration 0x08000ef8 Section 0 main.o(i.NVIC_Configuration) + i.NVIC_Init 0x08000f58 Section 0 misc.o(i.NVIC_Init) + i.NVIC_PriorityGroupConfig 0x08000fcc Section 0 misc.o(i.NVIC_PriorityGroupConfig) + i.PendSV_Handler 0x08000fe0 Section 0 stm32f10x_it.o(i.PendSV_Handler) + i.RCC_APB1PeriphClockCmd 0x08000fe4 Section 0 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + i.RCC_APB2PeriphClockCmd 0x08001004 Section 0 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + i.RCC_Configuration 0x08001024 Section 0 main.o(i.RCC_Configuration) + i.RCC_DeInit 0x08001090 Section 0 stm32f10x_rcc.o(i.RCC_DeInit) + i.RCC_GetClocksFreq 0x080010dc Section 0 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + i.RCC_GetFlagStatus 0x080011b0 Section 0 stm32f10x_rcc.o(i.RCC_GetFlagStatus) + i.RCC_GetSYSCLKSource 0x080011ec Section 0 stm32f10x_rcc.o(i.RCC_GetSYSCLKSource) + i.RCC_HCLKConfig 0x080011fc Section 0 stm32f10x_rcc.o(i.RCC_HCLKConfig) + i.RCC_HSEConfig 0x08001214 Section 0 stm32f10x_rcc.o(i.RCC_HSEConfig) + i.RCC_PCLK1Config 0x08001260 Section 0 stm32f10x_rcc.o(i.RCC_PCLK1Config) + i.RCC_PCLK2Config 0x08001278 Section 0 stm32f10x_rcc.o(i.RCC_PCLK2Config) + i.RCC_PLLCmd 0x08001290 Section 0 stm32f10x_rcc.o(i.RCC_PLLCmd) + i.RCC_PLLConfig 0x0800129c Section 0 stm32f10x_rcc.o(i.RCC_PLLConfig) + i.RCC_SYSCLKConfig 0x080012b8 Section 0 stm32f10x_rcc.o(i.RCC_SYSCLKConfig) + i.RCC_WaitForHSEStartUp 0x080012d0 Section 0 stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) + i.SPI1_Init 0x08001308 Section 0 spi.o(i.SPI1_Init) + i.SPI2_Init 0x0800138c Section 0 spi.o(i.SPI2_Init) + i.SPI_Cmd 0x08001418 Section 0 stm32f10x_spi.o(i.SPI_Cmd) + i.SPI_I2S_GetFlagStatus 0x08001430 Section 0 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + i.SPI_I2S_ReceiveData 0x08001442 Section 0 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + i.SPI_I2S_SendData 0x08001448 Section 0 stm32f10x_spi.o(i.SPI_I2S_SendData) + i.SPI_Init 0x0800144c Section 0 stm32f10x_spi.o(i.SPI_Init) + i.SPI_ReadWriteByte 0x08001488 Section 0 spi.o(i.SPI_ReadWriteByte) + i.SPI_SetSpeed 0x08001530 Section 0 spi.o(i.SPI_SetSpeed) + i.SVC_Handler 0x08001580 Section 0 stm32f10x_it.o(i.SVC_Handler) + i.SendConsoleByte 0x08001584 Section 0 printf.o(i.SendConsoleByte) + i.SendConsoleData 0x08001598 Section 0 printf.o(i.SendConsoleData) + i.SendUartByte 0x080015b0 Section 0 printf.o(i.SendUartByte) + i.SendUartData 0x080015d0 Section 0 printf.o(i.SendUartData) + i.SetSysClock 0x08001602 Section 0 system_stm32f10x.o(i.SetSysClock) + SetSysClock 0x08001603 Thumb Code 8 system_stm32f10x.o(i.SetSysClock) + i.SetSysClockTo72 0x0800160c Section 0 system_stm32f10x.o(i.SetSysClockTo72) + SetSysClockTo72 0x0800160d Thumb Code 212 system_stm32f10x.o(i.SetSysClockTo72) + i.SysTick_Handler 0x080016e8 Section 0 stm32f10x_it.o(i.SysTick_Handler) + i.SystemInit 0x080016ec Section 0 system_stm32f10x.o(i.SystemInit) + i.USART1_IRQHandler 0x0800174c Section 0 printf.o(i.USART1_IRQHandler) + i.USART2_IRQHandler 0x08001798 Section 0 usart2.o(i.USART2_IRQHandler) + i.USART2_Init 0x080017f4 Section 0 usart2.o(i.USART2_Init) + i.USART3_IRQHandler 0x0800187c Section 0 printf.o(i.USART3_IRQHandler) + i.USART_ClearFlag 0x080018e0 Section 0 stm32f10x_usart.o(i.USART_ClearFlag) + i.USART_ClearITPendingBit 0x080018f2 Section 0 stm32f10x_usart.o(i.USART_ClearITPendingBit) + i.USART_Cmd 0x08001910 Section 0 stm32f10x_usart.o(i.USART_Cmd) + i.USART_Configuration 0x08001928 Section 0 printf.o(i.USART_Configuration) + i.USART_GetFlagStatus 0x08001a44 Section 0 stm32f10x_usart.o(i.USART_GetFlagStatus) + i.USART_GetITStatus 0x08001a5e Section 0 stm32f10x_usart.o(i.USART_GetITStatus) + i.USART_ITConfig 0x08001ab2 Section 0 stm32f10x_usart.o(i.USART_ITConfig) + i.USART_Init 0x08001afc Section 0 stm32f10x_usart.o(i.USART_Init) + i.USART_ReceiveData 0x08001bd4 Section 0 stm32f10x_usart.o(i.USART_ReceiveData) + i.USART_SendData 0x08001bde Section 0 stm32f10x_usart.o(i.USART_SendData) + i.UsageFault_Handler 0x08001be6 Section 0 stm32f10x_it.o(i.UsageFault_Handler) + i.__0printf$bare 0x08001bec Section 0 printfb.o(i.__0printf$bare) + i.__scatterload_copy 0x08001bfc Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x08001c0a Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x08001c0c Section 14 handlers.o(i.__scatterload_zeroinit) + i._printf_core 0x08001c1a Section 0 printfb.o(i._printf_core) + _printf_core 0x08001c1b Thumb Code 34 printfb.o(i._printf_core) + i.delay_ms 0x08001c3c Section 0 delay.o(i.delay_ms) + i.fputc 0x08001c68 Section 0 printf.o(i.fputc) + i.led_init 0x08001c8c Section 0 led.o(i.led_init) + i.main 0x08001ce4 Section 0 main.o(i.main) + .constdata 0x08001d94 Section 10 nrf24l01.o(.constdata) + .data 0x20000000 Section 10 printf.o(.data) + .data 0x2000000a Section 4 usart2.o(.data) + .data 0x2000000e Section 56 dataproc.o(.data) + .data 0x20000046 Section 20 stm32f10x_rcc.o(.data) + APBAHBPrescTable 0x20000046 Data 16 stm32f10x_rcc.o(.data) + ADCPrescTable 0x20000056 Data 4 stm32f10x_rcc.o(.data) + .data 0x2000005c Section 4 stdout.o(.data) + .bss 0x20000060 Section 500 printf.o(.bss) + .bss 0x20000254 Section 64 usart2.o(.bss) + .bss 0x20000294 Section 500 dataproc.o(.bss) + STACK 0x20000488 Section 1024 startup_stm32f10x_hd.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __decompress - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_Size 0x00000130 Number 0 startup_stm32f10x_hd.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f10x_hd.o(RESET) + __Vectors_End 0x08000130 Data 0 startup_stm32f10x_hd.o(RESET) + __main 0x08000131 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x08000131 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x08000135 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x08000139 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x08000139 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x08000139 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x08000139 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_final_cpp 0x08000141 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x08000141 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + Reset_Handler 0x08000145 Thumb Code 8 startup_stm32f10x_hd.o(.text) + ADC1_2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + ADC3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_RX1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_SCE_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel6_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel7_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel4_5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI0_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI15_10_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI9_5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + FLASH_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + FSMC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_ER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_EV_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_ER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_EV_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + PVD_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RCC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTCAlarm_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SDIO_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TAMPER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_BRK_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_CC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_TRG_COM_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_UP_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM6_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM7_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_BRK_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_CC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_TRG_COM_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_UP_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + UART4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + UART5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USBWakeUp_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USB_LP_CAN1_RX0_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + WWDG_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + __scatterload 0x08000169 Thumb Code 28 init.o(.text) + __scatterload_rt2 0x08000169 Thumb Code 0 init.o(.text) + BusFault_Handler 0x0800018d Thumb Code 4 stm32f10x_it.o(i.BusFault_Handler) + CheckSum 0x08000191 Thumb Code 36 dataproc.o(i.CheckSum) + DataProc_1356 0x080001b5 Thumb Code 216 dataproc.o(i.DataProc_1356) + DataProc_Nrf24l01 0x080002b5 Thumb Code 288 dataproc.o(i.DataProc_Nrf24l01) + DataProc_USART1 0x080003fd Thumb Code 834 dataproc.o(i.DataProc_USART1) + Data_Init 0x0800082d Thumb Code 240 dataproc.o(i.Data_Init) + DebugMon_Handler 0x0800092d Thumb Code 2 stm32f10x_it.o(i.DebugMon_Handler) + GPIO_Init 0x0800092f Thumb Code 274 stm32f10x_gpio.o(i.GPIO_Init) + GPIO_ResetBits 0x08000a41 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_ResetBits) + GPIO_SetBits 0x08000a45 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_SetBits) + HardFault_Handler 0x08000a49 Thumb Code 4 stm32f10x_it.o(i.HardFault_Handler) + MemManage_Handler 0x08000a4d Thumb Code 4 stm32f10x_it.o(i.MemManage_Handler) + NMI_Handler 0x08000a51 Thumb Code 2 stm32f10x_it.o(i.NMI_Handler) + NRF24L01_Check 0x08000a55 Thumb Code 80 nrf24l01.o(i.NRF24L01_Check) + NRF24L01_Init 0x08000aad Thumb Code 228 nrf24l01.o(i.NRF24L01_Init) + NRF24L01_RX_Mode 0x08000ba9 Thumb Code 166 nrf24l01.o(i.NRF24L01_RX_Mode) + NRF24L01_Read_Buf 0x08000c61 Thumb Code 114 nrf24l01.o(i.NRF24L01_Read_Buf) + NRF24L01_Read_Reg 0x08000cdd Thumb Code 78 nrf24l01.o(i.NRF24L01_Read_Reg) + NRF24L01_RxPacket 0x08000d3d Thumb Code 66 nrf24l01.o(i.NRF24L01_RxPacket) + NRF24L01_TX_Mode 0x08000d81 Thumb Code 136 nrf24l01.o(i.NRF24L01_TX_Mode) + NRF24L01_Write_Buf 0x08000e19 Thumb Code 114 nrf24l01.o(i.NRF24L01_Write_Buf) + NRF24L01_Write_Reg 0x08000e95 Thumb Code 84 nrf24l01.o(i.NRF24L01_Write_Reg) + NVIC_Configuration 0x08000ef9 Thumb Code 96 main.o(i.NVIC_Configuration) + NVIC_Init 0x08000f59 Thumb Code 102 misc.o(i.NVIC_Init) + NVIC_PriorityGroupConfig 0x08000fcd Thumb Code 10 misc.o(i.NVIC_PriorityGroupConfig) + PendSV_Handler 0x08000fe1 Thumb Code 2 stm32f10x_it.o(i.PendSV_Handler) + RCC_APB1PeriphClockCmd 0x08000fe5 Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + RCC_APB2PeriphClockCmd 0x08001005 Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + RCC_Configuration 0x08001025 Thumb Code 106 main.o(i.RCC_Configuration) + RCC_DeInit 0x08001091 Thumb Code 64 stm32f10x_rcc.o(i.RCC_DeInit) + RCC_GetClocksFreq 0x080010dd Thumb Code 192 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + RCC_GetFlagStatus 0x080011b1 Thumb Code 56 stm32f10x_rcc.o(i.RCC_GetFlagStatus) + RCC_GetSYSCLKSource 0x080011ed Thumb Code 10 stm32f10x_rcc.o(i.RCC_GetSYSCLKSource) + RCC_HCLKConfig 0x080011fd Thumb Code 18 stm32f10x_rcc.o(i.RCC_HCLKConfig) + RCC_HSEConfig 0x08001215 Thumb Code 70 stm32f10x_rcc.o(i.RCC_HSEConfig) + RCC_PCLK1Config 0x08001261 Thumb Code 18 stm32f10x_rcc.o(i.RCC_PCLK1Config) + RCC_PCLK2Config 0x08001279 Thumb Code 20 stm32f10x_rcc.o(i.RCC_PCLK2Config) + RCC_PLLCmd 0x08001291 Thumb Code 6 stm32f10x_rcc.o(i.RCC_PLLCmd) + RCC_PLLConfig 0x0800129d Thumb Code 24 stm32f10x_rcc.o(i.RCC_PLLConfig) + RCC_SYSCLKConfig 0x080012b9 Thumb Code 18 stm32f10x_rcc.o(i.RCC_SYSCLKConfig) + RCC_WaitForHSEStartUp 0x080012d1 Thumb Code 56 stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) + SPI1_Init 0x08001309 Thumb Code 122 spi.o(i.SPI1_Init) + SPI2_Init 0x0800138d Thumb Code 132 spi.o(i.SPI2_Init) + SPI_Cmd 0x08001419 Thumb Code 24 stm32f10x_spi.o(i.SPI_Cmd) + SPI_I2S_GetFlagStatus 0x08001431 Thumb Code 18 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + SPI_I2S_ReceiveData 0x08001443 Thumb Code 6 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + SPI_I2S_SendData 0x08001449 Thumb Code 4 stm32f10x_spi.o(i.SPI_I2S_SendData) + SPI_Init 0x0800144d Thumb Code 60 stm32f10x_spi.o(i.SPI_Init) + SPI_ReadWriteByte 0x08001489 Thumb Code 158 spi.o(i.SPI_ReadWriteByte) + SPI_SetSpeed 0x08001531 Thumb Code 72 spi.o(i.SPI_SetSpeed) + SVC_Handler 0x08001581 Thumb Code 2 stm32f10x_it.o(i.SVC_Handler) + SendConsoleByte 0x08001585 Thumb Code 14 printf.o(i.SendConsoleByte) + SendConsoleData 0x08001599 Thumb Code 18 printf.o(i.SendConsoleData) + SendUartByte 0x080015b1 Thumb Code 32 printf.o(i.SendUartByte) + SendUartData 0x080015d1 Thumb Code 50 printf.o(i.SendUartData) + SysTick_Handler 0x080016e9 Thumb Code 2 stm32f10x_it.o(i.SysTick_Handler) + SystemInit 0x080016ed Thumb Code 78 system_stm32f10x.o(i.SystemInit) + USART1_IRQHandler 0x0800174d Thumb Code 60 printf.o(i.USART1_IRQHandler) + USART2_IRQHandler 0x08001799 Thumb Code 78 usart2.o(i.USART2_IRQHandler) + USART2_Init 0x080017f5 Thumb Code 126 usart2.o(i.USART2_Init) + USART3_IRQHandler 0x0800187d Thumb Code 88 printf.o(i.USART3_IRQHandler) + USART_ClearFlag 0x080018e1 Thumb Code 18 stm32f10x_usart.o(i.USART_ClearFlag) + USART_ClearITPendingBit 0x080018f3 Thumb Code 30 stm32f10x_usart.o(i.USART_ClearITPendingBit) + USART_Cmd 0x08001911 Thumb Code 24 stm32f10x_usart.o(i.USART_Cmd) + USART_Configuration 0x08001929 Thumb Code 266 printf.o(i.USART_Configuration) + USART_GetFlagStatus 0x08001a45 Thumb Code 26 stm32f10x_usart.o(i.USART_GetFlagStatus) + USART_GetITStatus 0x08001a5f Thumb Code 84 stm32f10x_usart.o(i.USART_GetITStatus) + USART_ITConfig 0x08001ab3 Thumb Code 74 stm32f10x_usart.o(i.USART_ITConfig) + USART_Init 0x08001afd Thumb Code 210 stm32f10x_usart.o(i.USART_Init) + USART_ReceiveData 0x08001bd5 Thumb Code 10 stm32f10x_usart.o(i.USART_ReceiveData) + USART_SendData 0x08001bdf Thumb Code 8 stm32f10x_usart.o(i.USART_SendData) + UsageFault_Handler 0x08001be7 Thumb Code 4 stm32f10x_it.o(i.UsageFault_Handler) + __0printf$bare 0x08001bed Thumb Code 8 printfb.o(i.__0printf$bare) + __1printf$bare 0x08001bed Thumb Code 0 printfb.o(i.__0printf$bare) + __2printf 0x08001bed Thumb Code 0 printfb.o(i.__0printf$bare) + __scatterload_copy 0x08001bfd Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x08001c0b Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x08001c0d Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + delay_ms 0x08001c3d Thumb Code 42 delay.o(i.delay_ms) + fputc 0x08001c69 Thumb Code 32 printf.o(i.fputc) + led_init 0x08001c8d Thumb Code 84 led.o(i.led_init) + main 0x08001ce5 Thumb Code 132 main.o(i.main) + TX_ADDRESS 0x08001d94 Data 5 nrf24l01.o(.constdata) + RX_ADDRESS 0x08001d99 Data 5 nrf24l01.o(.constdata) + Region$$Table$$Base 0x08001da0 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08001dc0 Number 0 anon$$obj.o(Region$$Table) + UARTtoConsole_RxBufferWr 0x20000000 Data 1 printf.o(.data) + UARTtoConsole_RxBufferRd 0x20000001 Data 1 printf.o(.data) + USART1_TX_CNT 0x20000002 Data 1 printf.o(.data) + USART1_RX_CNT 0x20000003 Data 1 printf.o(.data) + USART1_REC_Status 0x20000004 Data 2 printf.o(.data) + USART3_TX_CNT 0x20000006 Data 1 printf.o(.data) + USART3_RX_CNT 0x20000007 Data 1 printf.o(.data) + USART3_REC_Status 0x20000008 Data 2 printf.o(.data) + USART2_TX_CNT 0x2000000a Data 1 usart2.o(.data) + USART2_RX_CNT 0x2000000b Data 1 usart2.o(.data) + USART2_REC_Status 0x2000000c Data 2 usart2.o(.data) + CheckData_1356 0x2000000e Data 10 dataproc.o(.data) + GetNum_1356 0x20000018 Data 5 dataproc.o(.data) + CmdRspBufferWr_Rx 0x2000001d Data 1 dataproc.o(.data) + txBuf 0x2000001e Data 32 dataproc.o(.data) + rspFlag 0x2000003e Data 1 dataproc.o(.data) + wrNumFlag 0x2000003f Data 1 dataproc.o(.data) + idBuf 0x20000040 Data 5 dataproc.o(.data) + newIdFlag 0x20000045 Data 1 dataproc.o(.data) + __stdout 0x2000005c Data 4 stdout.o(.data) + UARTtoConsole_RxBuffer 0x20000060 Data 100 printf.o(.bss) + USART1_RX_BUF 0x200000c4 Data 200 printf.o(.bss) + USART3_RX_BUF 0x2000018c Data 200 printf.o(.bss) + USART2_RX_BUF 0x20000254 Data 64 usart2.o(.bss) + uartSendData 0x20000294 Data 100 dataproc.o(.bss) + uartRecData 0x200002f8 Data 100 dataproc.o(.bss) + uartSendRdNumData 0x2000035c Data 100 dataproc.o(.bss) + uartSendWrNumOkData 0x200003c0 Data 100 dataproc.o(.bss) + CmdRspBuffer 0x20000424 Data 100 dataproc.o(.bss) + __initial_sp 0x20000888 Data 0 startup_stm32f10x_hd.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000131 + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00001e20, Max: 0x00040000, ABSOLUTE) + + Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x00001dc0, Max: 0x00040000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x00000130 Data RO 1314 RESET startup_stm32f10x_hd.o + 0x08000130 0x00000000 Code RO 1319 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x08000130 0x00000004 Code RO 1582 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x08000134 0x00000004 Code RO 1585 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x08000138 0x00000000 Code RO 1587 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x08000138 0x00000000 Code RO 1589 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x08000138 0x00000008 Code RO 1590 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x08000140 0x00000000 Code RO 1592 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o) + 0x08000140 0x00000000 Code RO 1594 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o) + 0x08000140 0x00000004 Code RO 1583 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000144 0x00000024 Code RO 1315 .text startup_stm32f10x_hd.o + 0x08000168 0x00000024 Code RO 1612 .text mc_w.l(init.o) + 0x0800018c 0x00000004 Code RO 427 i.BusFault_Handler stm32f10x_it.o + 0x08000190 0x00000024 Code RO 381 i.CheckSum dataproc.o + 0x080001b4 0x00000100 Code RO 382 i.DataProc_1356 dataproc.o + 0x080002b4 0x00000148 Code RO 383 i.DataProc_Nrf24l01 dataproc.o + 0x080003fc 0x00000430 Code RO 384 i.DataProc_USART1 dataproc.o + 0x0800082c 0x00000100 Code RO 385 i.Data_Init dataproc.o + 0x0800092c 0x00000002 Code RO 428 i.DebugMon_Handler stm32f10x_it.o + 0x0800092e 0x00000112 Code RO 1009 i.GPIO_Init stm32f10x_gpio.o + 0x08000a40 0x00000004 Code RO 1016 i.GPIO_ResetBits stm32f10x_gpio.o + 0x08000a44 0x00000004 Code RO 1017 i.GPIO_SetBits stm32f10x_gpio.o + 0x08000a48 0x00000004 Code RO 429 i.HardFault_Handler stm32f10x_it.o + 0x08000a4c 0x00000004 Code RO 430 i.MemManage_Handler stm32f10x_it.o + 0x08000a50 0x00000002 Code RO 431 i.NMI_Handler stm32f10x_it.o + 0x08000a52 0x00000002 PAD + 0x08000a54 0x00000058 Code RO 276 i.NRF24L01_Check nrf24l01.o + 0x08000aac 0x000000fc Code RO 278 i.NRF24L01_Init nrf24l01.o + 0x08000ba8 0x000000b8 Code RO 279 i.NRF24L01_RX_Mode nrf24l01.o + 0x08000c60 0x0000007c Code RO 280 i.NRF24L01_Read_Buf nrf24l01.o + 0x08000cdc 0x00000060 Code RO 281 i.NRF24L01_Read_Reg nrf24l01.o + 0x08000d3c 0x00000042 Code RO 282 i.NRF24L01_RxPacket nrf24l01.o + 0x08000d7e 0x00000002 PAD + 0x08000d80 0x00000098 Code RO 283 i.NRF24L01_TX_Mode nrf24l01.o + 0x08000e18 0x0000007c Code RO 285 i.NRF24L01_Write_Buf nrf24l01.o + 0x08000e94 0x00000064 Code RO 286 i.NRF24L01_Write_Reg nrf24l01.o + 0x08000ef8 0x00000060 Code RO 1 i.NVIC_Configuration main.o + 0x08000f58 0x00000074 Code RO 964 i.NVIC_Init misc.o + 0x08000fcc 0x00000014 Code RO 965 i.NVIC_PriorityGroupConfig misc.o + 0x08000fe0 0x00000002 Code RO 432 i.PendSV_Handler stm32f10x_it.o + 0x08000fe2 0x00000002 PAD + 0x08000fe4 0x00000020 Code RO 511 i.RCC_APB1PeriphClockCmd stm32f10x_rcc.o + 0x08001004 0x00000020 Code RO 513 i.RCC_APB2PeriphClockCmd stm32f10x_rcc.o + 0x08001024 0x0000006a Code RO 2 i.RCC_Configuration main.o + 0x0800108e 0x00000002 PAD + 0x08001090 0x0000004c Code RO 520 i.RCC_DeInit stm32f10x_rcc.o + 0x080010dc 0x000000d4 Code RO 521 i.RCC_GetClocksFreq stm32f10x_rcc.o + 0x080011b0 0x0000003c Code RO 522 i.RCC_GetFlagStatus stm32f10x_rcc.o + 0x080011ec 0x00000010 Code RO 524 i.RCC_GetSYSCLKSource stm32f10x_rcc.o + 0x080011fc 0x00000018 Code RO 525 i.RCC_HCLKConfig stm32f10x_rcc.o + 0x08001214 0x0000004c Code RO 526 i.RCC_HSEConfig stm32f10x_rcc.o + 0x08001260 0x00000018 Code RO 532 i.RCC_PCLK1Config stm32f10x_rcc.o + 0x08001278 0x00000018 Code RO 533 i.RCC_PCLK2Config stm32f10x_rcc.o + 0x08001290 0x0000000c Code RO 534 i.RCC_PLLCmd stm32f10x_rcc.o + 0x0800129c 0x0000001c Code RO 535 i.RCC_PLLConfig stm32f10x_rcc.o + 0x080012b8 0x00000018 Code RO 538 i.RCC_SYSCLKConfig stm32f10x_rcc.o + 0x080012d0 0x00000038 Code RO 540 i.RCC_WaitForHSEStartUp stm32f10x_rcc.o + 0x08001308 0x00000084 Code RO 351 i.SPI1_Init spi.o + 0x0800138c 0x0000008c Code RO 352 i.SPI2_Init spi.o + 0x08001418 0x00000018 Code RO 1125 i.SPI_Cmd stm32f10x_spi.o + 0x08001430 0x00000012 Code RO 1133 i.SPI_I2S_GetFlagStatus stm32f10x_spi.o + 0x08001442 0x00000006 Code RO 1136 i.SPI_I2S_ReceiveData stm32f10x_spi.o + 0x08001448 0x00000004 Code RO 1137 i.SPI_I2S_SendData stm32f10x_spi.o + 0x0800144c 0x0000003c Code RO 1138 i.SPI_Init stm32f10x_spi.o + 0x08001488 0x000000a8 Code RO 353 i.SPI_ReadWriteByte spi.o + 0x08001530 0x00000050 Code RO 354 i.SPI_SetSpeed spi.o + 0x08001580 0x00000002 Code RO 433 i.SVC_Handler stm32f10x_it.o + 0x08001582 0x00000002 PAD + 0x08001584 0x00000014 Code RO 145 i.SendConsoleByte printf.o + 0x08001598 0x00000018 Code RO 146 i.SendConsoleData printf.o + 0x080015b0 0x00000020 Code RO 148 i.SendUartByte printf.o + 0x080015d0 0x00000032 Code RO 149 i.SendUartData printf.o + 0x08001602 0x00000008 Code RO 1278 i.SetSysClock system_stm32f10x.o + 0x0800160a 0x00000002 PAD + 0x0800160c 0x000000dc Code RO 1279 i.SetSysClockTo72 system_stm32f10x.o + 0x080016e8 0x00000002 Code RO 434 i.SysTick_Handler stm32f10x_it.o + 0x080016ea 0x00000002 PAD + 0x080016ec 0x00000060 Code RO 1281 i.SystemInit system_stm32f10x.o + 0x0800174c 0x0000004c Code RO 152 i.USART1_IRQHandler printf.o + 0x08001798 0x0000005c Code RO 254 i.USART2_IRQHandler usart2.o + 0x080017f4 0x00000088 Code RO 255 i.USART2_Init usart2.o + 0x0800187c 0x00000064 Code RO 153 i.USART3_IRQHandler printf.o + 0x080018e0 0x00000012 Code RO 778 i.USART_ClearFlag stm32f10x_usart.o + 0x080018f2 0x0000001e Code RO 779 i.USART_ClearITPendingBit stm32f10x_usart.o + 0x08001910 0x00000018 Code RO 782 i.USART_Cmd stm32f10x_usart.o + 0x08001928 0x0000011c Code RO 154 i.USART_Configuration printf.o + 0x08001a44 0x0000001a Code RO 785 i.USART_GetFlagStatus stm32f10x_usart.o + 0x08001a5e 0x00000054 Code RO 786 i.USART_GetITStatus stm32f10x_usart.o + 0x08001ab2 0x0000004a Code RO 788 i.USART_ITConfig stm32f10x_usart.o + 0x08001afc 0x000000d8 Code RO 789 i.USART_Init stm32f10x_usart.o + 0x08001bd4 0x0000000a Code RO 796 i.USART_ReceiveData stm32f10x_usart.o + 0x08001bde 0x00000008 Code RO 799 i.USART_SendData stm32f10x_usart.o + 0x08001be6 0x00000004 Code RO 435 i.UsageFault_Handler stm32f10x_it.o + 0x08001bea 0x00000002 PAD + 0x08001bec 0x00000010 Code RO 1323 i.__0printf$bare mc_w.l(printfb.o) + 0x08001bfc 0x0000000e Code RO 1624 i.__scatterload_copy mc_w.l(handlers.o) + 0x08001c0a 0x00000002 Code RO 1625 i.__scatterload_null mc_w.l(handlers.o) + 0x08001c0c 0x0000000e Code RO 1626 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x08001c1a 0x00000022 Code RO 1330 i._printf_core mc_w.l(printfb.o) + 0x08001c3c 0x0000002a Code RO 230 i.delay_ms delay.o + 0x08001c66 0x00000002 PAD + 0x08001c68 0x00000024 Code RO 156 i.fputc printf.o + 0x08001c8c 0x00000058 Code RO 242 i.led_init led.o + 0x08001ce4 0x000000b0 Code RO 3 i.main main.o + 0x08001d94 0x0000000a Data RO 287 .constdata nrf24l01.o + 0x08001d9e 0x00000002 PAD + 0x08001da0 0x00000020 Data RO 1622 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x00000888, Max: 0x0000c000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x0000000a Data RW 158 .data printf.o + 0x2000000a 0x00000004 Data RW 257 .data usart2.o + 0x2000000e 0x00000038 Data RW 387 .data dataproc.o + 0x20000046 0x00000014 Data RW 541 .data stm32f10x_rcc.o + 0x2000005a 0x00000002 PAD + 0x2000005c 0x00000004 Data RW 1596 .data mc_w.l(stdout.o) + 0x20000060 0x000001f4 Zero RW 157 .bss printf.o + 0x20000254 0x00000040 Zero RW 256 .bss usart2.o + 0x20000294 0x000001f4 Zero RW 386 .bss dataproc.o + 0x20000488 0x00000400 Zero RW 1312 STACK startup_stm32f10x_hd.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 0 0 0 0 0 32 core_cm3.o + 1948 334 0 56 500 5488 dataproc.o + 42 0 0 0 0 511 delay.o + 88 4 0 0 0 463 led.o + 378 44 0 0 0 233724 main.o + 136 24 0 0 0 3387 misc.o + 1186 120 10 0 0 6133 nrf24l01.o + 622 62 0 10 500 5343 printf.o + 520 36 0 0 0 2339 spi.o + 36 8 304 0 1024 844 startup_stm32f10x_hd.o + 282 0 0 0 0 11568 stm32f10x_gpio.o + 26 0 0 0 0 3666 stm32f10x_it.o + 696 92 0 20 0 19526 stm32f10x_rcc.o + 112 0 0 0 0 10938 stm32f10x_spi.o + 490 6 0 0 0 22405 stm32f10x_usart.o + 324 26 0 0 0 1829 system_stm32f10x.o + 228 24 0 4 64 1684 usart2.o + + ---------------------------------------------------------------------- + 7132 780 348 92 2088 329880 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 18 0 2 2 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 8 4 0 0 0 0 entry9a.o + 30 0 0 0 0 0 handlers.o + 36 8 0 0 0 68 init.o + 50 8 0 0 0 152 printfb.o + 0 0 0 4 0 0 stdout.o + + ---------------------------------------------------------------------- + 136 24 0 4 0 220 Library Totals + 0 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 136 24 0 4 0 220 mc_w.l + + ---------------------------------------------------------------------- + 136 24 0 4 0 220 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 7268 804 348 96 2088 326148 Grand Totals + 7268 804 348 96 2088 326148 ELF Image Totals + 7268 804 348 96 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 7616 ( 7.44kB) + Total RW Size (RW Data + ZI Data) 2184 ( 2.13kB) + Total ROM Size (Code + RO Data + RW Data) 7712 ( 7.53kB) + +============================================================================== + diff --git a/RVMDK/List/Printf_AUTO.map b/RVMDK/List/Printf_AUTO.map new file mode 100644 index 0000000..4af04e5 --- /dev/null +++ b/RVMDK/List/Printf_AUTO.map @@ -0,0 +1,1275 @@ +ARM Linker, 5.03 [Build 76] [MDK-ARM Standard] + +============================================================================== + +Section Cross References + + main.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig + main.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_Init) for NVIC_Init + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_DeInit) for RCC_DeInit + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_HSEConfig) for RCC_HSEConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) for RCC_WaitForHSEStartUp + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_HCLKConfig) for RCC_HCLKConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PCLK2Config) for RCC_PCLK2Config + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PCLK1Config) for RCC_PCLK1Config + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PLLConfig) for RCC_PLLConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_PLLCmd) for RCC_PLLCmd + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_SYSCLKConfig) for RCC_SYSCLKConfig + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_GetSYSCLKSource) for RCC_GetSYSCLKSource + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + main.o(i.main) refers to main.o(i.RCC_Configuration) for RCC_Configuration + main.o(i.main) refers to main.o(i.NVIC_Configuration) for NVIC_Configuration + main.o(i.main) refers to tim.o(i.TIM3_Int_Init) for TIM3_Int_Init + main.o(i.main) refers to led.o(i.led_init) for led_init + main.o(i.main) refers to printf.o(i.USART_Configuration) for USART_Configuration + main.o(i.main) refers to usart2.o(i.USART2_Init) for USART2_Init + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_Init) for NRF24L01_Init + main.o(i.main) refers to printfb.o(i.__0printf$bare) for __2printf + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_Check) for NRF24L01_Check + main.o(i.main) refers to dataproc.o(i.Data_Init) for Data_Init + main.o(i.main) refers to delay.o(i.delay_ms) for delay_ms + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_TX_Mode) for NRF24L01_TX_Mode + main.o(i.main) refers to dataproc.o(i.DataProc_1356) for DataProc_1356 + main.o(i.main) refers to dataproc.o(i.DataProc_Nrf24l01) for DataProc_Nrf24l01 + main.o(i.main) refers to dataproc.o(i.DataProc_USART1) for DataProc_USART1 + printf.o(i.SendConsoleByte) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendConsoleData) refers to printf.o(i.SendUartData) for SendUartData + printf.o(i.SendConsoleStr) refers to printf.o(i.SendUartStr) for SendUartStr + printf.o(i.SendUartByte) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.SendUartByte) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.SendUartData) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendUartRStr) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendUartStr) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.USART1_IRQHandler) refers to printf.o(.bss) for USART1_RX_BUF + printf.o(i.USART1_IRQHandler) refers to printf.o(.data) for USART1_RX_CNT + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + printf.o(i.USART3_IRQHandler) refers to printf.o(.bss) for USART3_RX_BUF + printf.o(i.USART3_IRQHandler) refers to printf.o(.data) for USART3_RX_CNT + printf.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + printf.o(i.USART_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + printf.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + printf.o(i.Usart1_SendData) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.Usart1_SendData) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.fputc) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + led.o(i.led_init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + usart2.o(i.USART2_IRQHandler) refers to usart2.o(.bss) for USART2_RX_BUF + usart2.o(i.USART2_IRQHandler) refers to usart2.o(.data) for USART2_RX_CNT + usart2.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + usart2.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + usart2.o(i.USART2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + nrf24l01.o(i.NRF24L01_Check) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_Check) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_Check) refers to nrf24l01.o(i.NRF24L01_Read_Buf) for NRF24L01_Read_Buf + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + nrf24l01.o(i.NRF24L01_Init) refers to spi.o(i.SPI2_Init) for SPI2_Init + nrf24l01.o(i.NRF24L01_Init) refers to spi.o(i.SPI1_Init) for SPI1_Init + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(.constdata) for RX_ADDRESS + nrf24l01.o(i.NRF24L01_Read_Buf) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_Read_Reg) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_RxPacket) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Reg) for NRF24L01_Read_Reg + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Buf) for NRF24L01_Read_Buf + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(.constdata) for TX_ADDRESS + nrf24l01.o(i.NRF24L01_TxPacket) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Reg) for NRF24L01_Read_Reg + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_Write_Buf) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_Write_Reg) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + spi.o(i.SPI1_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + spi.o(i.SPI1_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + spi.o(i.SPI1_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.SPI1_Init) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init + spi.o(i.SPI1_Init) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + spi.o(i.SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + spi.o(i.SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + spi.o(i.SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + spi.o(i.SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init + spi.o(i.SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) for SPI_I2S_GetFlagStatus + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_SendData) for SPI_I2S_SendData + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_ReceiveData) for SPI_I2S_ReceiveData + spi.o(i.SPI_SetSpeed) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + dataproc.o(i.DataProc_1356) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + dataproc.o(i.DataProc_1356) refers to delay.o(i.delay_ms) for delay_ms + dataproc.o(i.DataProc_1356) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + dataproc.o(i.DataProc_1356) refers to printf.o(.data) for USART3_RX_CNT + dataproc.o(i.DataProc_1356) refers to printf.o(.bss) for USART3_RX_BUF + dataproc.o(i.DataProc_1356) refers to dataproc.o(.data) for CheckData_1356 + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(i.CheckSum) for CheckSum + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_RxPacket) for NRF24L01_RxPacket + dataproc.o(i.DataProc_Nrf24l01) refers to printf.o(i.SendConsoleByte) for SendConsoleByte + dataproc.o(i.DataProc_Nrf24l01) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(.data) for newIdFlag + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(.bss) for uartSendWrNumOkData + dataproc.o(i.DataProc_USART1) refers to printfb.o(i.__0printf$bare) for __2printf + dataproc.o(i.DataProc_USART1) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_USART1) refers to printf.o(.data) for USART1_RX_CNT + dataproc.o(i.DataProc_USART1) refers to printf.o(.bss) for USART1_RX_BUF + dataproc.o(i.DataProc_USART1) refers to dataproc.o(.bss) for uartRecData + dataproc.o(i.DataProc_USART1) refers to dataproc.o(.data) for idBuf + dataproc.o(i.Data_Init) refers to dataproc.o(.bss) for uartSendData + dataproc.o(i.TIM3_IRQHandler) refers to stm32f10x_tim.o(i.TIM_GetITStatus) for TIM_GetITStatus + dataproc.o(i.TIM3_IRQHandler) refers to stm32f10x_tim.o(i.TIM_ClearITPendingBit) for TIM_ClearITPendingBit + dataproc.o(i.TIM3_IRQHandler) refers to dataproc.o(.data) for count + tim.o(i.TIM3_Int_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + tim.o(i.TIM3_Int_Init) refers to stm32f10x_tim.o(i.TIM_TimeBaseInit) for TIM_TimeBaseInit + tim.o(i.TIM3_Int_Init) refers to stm32f10x_tim.o(i.TIM_ITConfig) for TIM_ITConfig + tim.o(i.TIM3_Int_Init) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd + stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable + stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_usart.o(i.USART_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(i.I2S_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_tim.o(i.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(i.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI3_Config) for TI3_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI4_Config) for TI4_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler + stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 + system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock + system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(.text) for Reset_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.NMI_Handler) for NMI_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.HardFault_Handler) for HardFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.MemManage_Handler) for MemManage_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.BusFault_Handler) for BusFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.UsageFault_Handler) for UsageFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SVC_Handler) for SVC_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.DebugMon_Handler) for DebugMon_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.PendSV_Handler) for PendSV_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SysTick_Handler) for SysTick_Handler + startup_stm32f10x_hd.o(RESET) refers to dataproc.o(i.TIM3_IRQHandler) for TIM3_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to printf.o(i.USART1_IRQHandler) for USART1_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to usart2.o(i.USART2_IRQHandler) for USART2_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to printf.o(i.USART3_IRQHandler) for USART3_IRQHandler + startup_stm32f10x_hd.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + startup_stm32f10x_hd.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + printfb.o(i.__0fprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0fprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0printf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._sputc) for _sputc + printfb.o(i.__0vfprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vfprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._sputc) for _sputc + printf0.o(i.__0fprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0fprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0printf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0snprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0snprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0sprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0sprintf$0) refers to printf0.o(i._sputc) for _sputc + printf0.o(i.__0vfprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vfprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._sputc) for _sputc + printf1.o(i.__0fprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0fprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0printf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0snprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0snprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0sprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0sprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i.__0vfprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vfprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf2.o(i.__0fprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0fprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0printf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0snprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0snprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0sprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0sprintf$2) refers to printf2.o(i._sputc) for _sputc + printf2.o(i.__0vfprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vfprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._sputc) for _sputc + printf3.o(i.__0fprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0fprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0printf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0snprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0snprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0sprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0sprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i.__0vfprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vfprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf4.o(i.__0fprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0fprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0printf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0snprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0snprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0sprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0sprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i.__0vfprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vfprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf5.o(i.__0fprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0fprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0printf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0snprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0snprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0sprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0sprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i.__0vfprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vfprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf6.o(i.__0fprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0fprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0printf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0snprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0snprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0sprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0sprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i.__0vfprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vfprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i._printf_core) refers to printf6.o(i._printf_pre_padding) for _printf_pre_padding + printf6.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf6.o(i._printf_core) refers to printf6.o(i._printf_post_padding) for _printf_post_padding + printf7.o(i.__0fprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0fprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0printf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0snprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0snprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0sprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0sprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i.__0vfprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vfprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i._printf_core) refers to printf7.o(i._printf_pre_padding) for _printf_pre_padding + printf7.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf7.o(i._printf_core) refers to printf7.o(i._printf_post_padding) for _printf_post_padding + printf8.o(i.__0fprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0fprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0printf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0snprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0snprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0sprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0sprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i.__0vfprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vfprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i._printf_core) refers to printf8.o(i._printf_pre_padding) for _printf_pre_padding + printf8.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf8.o(i._printf_core) refers to printf8.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i.__0fprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0fprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0fprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0printf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0printf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0printf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0printf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0snprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0snprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0snprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0sprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0sprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0sprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i.__0vfprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vfprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vfprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0vsnprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsnprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsnprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0vsprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i._fp_digits) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._fp_digits) refers to dmul.o(.text) for __aeabi_dmul + printfa.o(i._fp_digits) refers to ddiv.o(.text) for __aeabi_ddiv + printfa.o(i._fp_digits) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + printfa.o(i._fp_digits) refers to dadd.o(.text) for __aeabi_dadd + printfa.o(i._fp_digits) refers to dfixul.o(.text) for __aeabi_d2ulz + printfa.o(i._fp_digits) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_core) refers to printfa.o(i._printf_pre_padding) for _printf_pre_padding + printfa.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers to printfa.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i._printf_core) refers to printfa.o(i._fp_digits) for _fp_digits + printfa.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printfa.o(i._printf_post_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_pre_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._snputc) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._sputc) refers (Special) to iusefp.o(.text) for __I$use$fp + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llsshr.o(.text) for __aeabi_lasr + dadd.o(.text) refers to depilogue.o(.text) for _double_epilogue + dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue + ddiv.o(.text) refers to depilogue.o(.text) for _double_round + dfixul.o(.text) refers to llushr.o(.text) for __aeabi_llsr + dfixul.o(.text) refers to llshl.o(.text) for __aeabi_llsl + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr + + +============================================================================== + +Removing Unused input sections from the image. + + Removing printf.o(i.SendConsoleStr), (20 bytes). + Removing printf.o(i.SendUartRStr), (60 bytes). + Removing printf.o(i.SendUartStr), (60 bytes). + Removing printf.o(i.Usart1_SendData), (44 bytes). + Removing nrf24l01.o(i.NRF24L01_Config), (56 bytes). + Removing nrf24l01.o(i.NRF24L01_TxPacket), (160 bytes). + Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ITConfig), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSEConfig), (52 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_MCOConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKConfig), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes). + Removing stm32f10x_usart.o(i.USART_ClockInit), (34 bytes). + Removing stm32f10x_usart.o(i.USART_ClockStructInit), (12 bytes). + Removing stm32f10x_usart.o(i.USART_DMACmd), (18 bytes). + Removing stm32f10x_usart.o(i.USART_DeInit), (156 bytes). + Removing stm32f10x_usart.o(i.USART_HalfDuplexCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_IrDACmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_IrDAConfig), (18 bytes). + Removing stm32f10x_usart.o(i.USART_LINBreakDetectLengthConfig), (18 bytes). + Removing stm32f10x_usart.o(i.USART_LINCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_OneBitMethodCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_OverSampling8Cmd), (22 bytes). + Removing stm32f10x_usart.o(i.USART_ReceiverWakeUpCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_SendBreak), (10 bytes). + Removing stm32f10x_usart.o(i.USART_SetAddress), (18 bytes). + Removing stm32f10x_usart.o(i.USART_SetGuardTime), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SetPrescaler), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardNACKCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_StructInit), (24 bytes). + Removing stm32f10x_usart.o(i.USART_WakeUpConfig), (18 bytes). + Removing misc.o(i.NVIC_SetVectorTable), (20 bytes). + Removing misc.o(i.NVIC_SystemLPConfig), (32 bytes). + Removing misc.o(i.SysTick_CLKSourceConfig), (40 bytes). + Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (20 bytes). + Removing stm32f10x_gpio.o(i.GPIO_DeInit), (200 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (64 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (32 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinRemapConfig), (144 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes). + Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes). + Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes). + Removing stm32f10x_spi.o(i.I2S_Cmd), (24 bytes). + Removing stm32f10x_spi.o(i.I2S_Init), (232 bytes). + Removing stm32f10x_spi.o(i.I2S_StructInit), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_BiDirectionalLineConfig), (28 bytes). + Removing stm32f10x_spi.o(i.SPI_CalculateCRC), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_DataSizeConfig), (18 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRC), (16 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRCPolynomial), (6 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearFlag), (6 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearITPendingBit), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_DMACmd), (18 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_DeInit), (88 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_GetITStatus), (52 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ITConfig), (32 bytes). + Removing stm32f10x_spi.o(i.SPI_NSSInternalSoftwareConfig), (30 bytes). + Removing stm32f10x_spi.o(i.SPI_SSOutputCmd), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_StructInit), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_TransmitCRC), (10 bytes). + Removing stm32f10x_tim.o(i.TI1_Config), (128 bytes). + Removing stm32f10x_tim.o(i.TI2_Config), (152 bytes). + Removing stm32f10x_tim.o(i.TI3_Config), (144 bytes). + Removing stm32f10x_tim.o(i.TI4_Config), (152 bytes). + Removing stm32f10x_tim.o(i.TIM_ARRPreloadConfig), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_BDTRConfig), (32 bytes). + Removing stm32f10x_tim.o(i.TIM_BDTRStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_CCPreloadControl), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_CCxCmd), (30 bytes). + Removing stm32f10x_tim.o(i.TIM_CCxNCmd), (30 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearFlag), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC1Ref), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC2Ref), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC3Ref), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC4Ref), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_CounterModeConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_CtrlPWMOutputs), (30 bytes). + Removing stm32f10x_tim.o(i.TIM_DMACmd), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_DMAConfig), (10 bytes). + Removing stm32f10x_tim.o(i.TIM_DeInit), (488 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRClockMode1Config), (54 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRClockMode2Config), (32 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRConfig), (28 bytes). + Removing stm32f10x_tim.o(i.TIM_EncoderInterfaceConfig), (66 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC1Config), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC2Config), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC3Config), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC4Config), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_GenerateEvent), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture1), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture2), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture3), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture4), (8 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCounter), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetFlagStatus), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_GetPrescaler), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_ICInit), (172 bytes). + Removing stm32f10x_tim.o(i.TIM_ICStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_InternalClockConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1FastConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1Init), (152 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1NPolarityConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1PolarityConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1PreloadConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2FastConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2Init), (164 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2NPolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2PolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2PreloadConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3FastConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3Init), (160 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3NPolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3PolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3PreloadConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4FastConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4Init), (124 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4PolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4PreloadConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OCStructInit), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_PWMIConfig), (124 bytes). + Removing stm32f10x_tim.o(i.TIM_PrescalerConfig), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectCCDMA), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectCOM), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectHallSensor), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectInputTrigger), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectMasterSlaveMode), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOCxM), (82 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOnePulseMode), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOutputTrigger), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectSlaveMode), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetAutoreload), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetClockDivision), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare1), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare2), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare3), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare4), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCounter), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC1Prescaler), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC2Prescaler), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC3Prescaler), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC4Prescaler), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_TIxExternalClockConfig), (62 bytes). + Removing stm32f10x_tim.o(i.TIM_TimeBaseStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_UpdateDisableConfig), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_UpdateRequestConfig), (24 bytes). + Removing core_cm3.o(.emb_text), (32 bytes). + Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). + Removing system_stm32f10x.o(.data), (20 bytes). + Removing startup_stm32f10x_hd.o(HEAP), (512 bytes). + Removing dadd.o(.text), (334 bytes). + Removing dmul.o(.text), (228 bytes). + Removing ddiv.o(.text), (222 bytes). + Removing dfixul.o(.text), (48 bytes). + Removing cdrcmple.o(.text), (40 bytes). + Removing depilogue.o(.text), (190 bytes). + +176 unused section(s) (total 8008 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfb.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf0.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf1.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf2.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf3.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf4.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf5.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf7.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf8.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf6.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfa.o ABSOLUTE + ../clib/microlib/stdio/streams.c 0x00000000 Number 0 stdout.o ABSOLUTE + ../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 dadd.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 depilogue.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixul.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE + ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s 0x00000000 Number 0 startup_stm32f10x_hd.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c 0x00000000 Number 0 misc.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c 0x00000000 Number 0 stm32f10x_spi.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c 0x00000000 Number 0 stm32f10x_tim.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c 0x00000000 Number 0 stm32f10x_usart.o ABSOLUTE + ..\Libraries\stm32f10x_it.c 0x00000000 Number 0 stm32f10x_it.o ABSOLUTE + ..\Libraries\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + ..\\Libraries\\CMSIS\\CM3\\CoreSupport\\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + ..\bsp\DataProc.c 0x00000000 Number 0 dataproc.o ABSOLUTE + ..\bsp\LED.c 0x00000000 Number 0 led.o ABSOLUTE + ..\bsp\USART2.c 0x00000000 Number 0 usart2.o ABSOLUTE + ..\bsp\delay.c 0x00000000 Number 0 delay.o ABSOLUTE + ..\bsp\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\bsp\nrf24L01.c 0x00000000 Number 0 nrf24l01.o ABSOLUTE + ..\bsp\printf.c 0x00000000 Number 0 printf.o ABSOLUTE + ..\bsp\spi.c 0x00000000 Number 0 spi.o ABSOLUTE + ..\bsp\tim.c 0x00000000 Number 0 tim.o ABSOLUTE + cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + 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nrf24l01.o(i.NRF24L01_Check) + i.NRF24L01_Init 0x08000af0 Section 0 nrf24l01.o(i.NRF24L01_Init) + i.NRF24L01_RX_Mode 0x08000bec Section 0 nrf24l01.o(i.NRF24L01_RX_Mode) + i.NRF24L01_Read_Buf 0x08000ca4 Section 0 nrf24l01.o(i.NRF24L01_Read_Buf) + i.NRF24L01_Read_Reg 0x08000d20 Section 0 nrf24l01.o(i.NRF24L01_Read_Reg) + i.NRF24L01_RxPacket 0x08000d80 Section 0 nrf24l01.o(i.NRF24L01_RxPacket) + i.NRF24L01_TX_Mode 0x08000dc4 Section 0 nrf24l01.o(i.NRF24L01_TX_Mode) + i.NRF24L01_Write_Buf 0x08000e5c Section 0 nrf24l01.o(i.NRF24L01_Write_Buf) + i.NRF24L01_Write_Reg 0x08000ed8 Section 0 nrf24l01.o(i.NRF24L01_Write_Reg) + i.NVIC_Configuration 0x08000f3c Section 0 main.o(i.NVIC_Configuration) + i.NVIC_Init 0x08000fb8 Section 0 misc.o(i.NVIC_Init) + i.NVIC_PriorityGroupConfig 0x0800102c Section 0 misc.o(i.NVIC_PriorityGroupConfig) + i.PendSV_Handler 0x08001040 Section 0 stm32f10x_it.o(i.PendSV_Handler) + i.RCC_APB1PeriphClockCmd 0x08001044 Section 0 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + i.RCC_APB2PeriphClockCmd 0x08001064 Section 0 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + i.RCC_Configuration 0x08001084 Section 0 main.o(i.RCC_Configuration) + i.RCC_DeInit 0x080010f0 Section 0 stm32f10x_rcc.o(i.RCC_DeInit) + i.RCC_GetClocksFreq 0x0800113c Section 0 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + i.RCC_GetFlagStatus 0x08001210 Section 0 stm32f10x_rcc.o(i.RCC_GetFlagStatus) + i.RCC_GetSYSCLKSource 0x0800124c Section 0 stm32f10x_rcc.o(i.RCC_GetSYSCLKSource) + i.RCC_HCLKConfig 0x0800125c Section 0 stm32f10x_rcc.o(i.RCC_HCLKConfig) + i.RCC_HSEConfig 0x08001274 Section 0 stm32f10x_rcc.o(i.RCC_HSEConfig) + i.RCC_PCLK1Config 0x080012c0 Section 0 stm32f10x_rcc.o(i.RCC_PCLK1Config) + i.RCC_PCLK2Config 0x080012d8 Section 0 stm32f10x_rcc.o(i.RCC_PCLK2Config) + i.RCC_PLLCmd 0x080012f0 Section 0 stm32f10x_rcc.o(i.RCC_PLLCmd) + i.RCC_PLLConfig 0x080012fc Section 0 stm32f10x_rcc.o(i.RCC_PLLConfig) + i.RCC_SYSCLKConfig 0x08001318 Section 0 stm32f10x_rcc.o(i.RCC_SYSCLKConfig) + i.RCC_WaitForHSEStartUp 0x08001330 Section 0 stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) + i.SPI1_Init 0x08001368 Section 0 spi.o(i.SPI1_Init) + i.SPI2_Init 0x080013ec Section 0 spi.o(i.SPI2_Init) + i.SPI_Cmd 0x08001478 Section 0 stm32f10x_spi.o(i.SPI_Cmd) + i.SPI_I2S_GetFlagStatus 0x08001490 Section 0 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + i.SPI_I2S_ReceiveData 0x080014a2 Section 0 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + i.SPI_I2S_SendData 0x080014a8 Section 0 stm32f10x_spi.o(i.SPI_I2S_SendData) + i.SPI_Init 0x080014ac Section 0 stm32f10x_spi.o(i.SPI_Init) + i.SPI_ReadWriteByte 0x080014e8 Section 0 spi.o(i.SPI_ReadWriteByte) + i.SPI_SetSpeed 0x08001590 Section 0 spi.o(i.SPI_SetSpeed) + i.SVC_Handler 0x080015e0 Section 0 stm32f10x_it.o(i.SVC_Handler) + i.SendConsoleByte 0x080015e4 Section 0 printf.o(i.SendConsoleByte) + i.SendConsoleData 0x080015f8 Section 0 printf.o(i.SendConsoleData) + i.SendUartByte 0x08001610 Section 0 printf.o(i.SendUartByte) + i.SendUartData 0x08001630 Section 0 printf.o(i.SendUartData) + i.SetSysClock 0x08001662 Section 0 system_stm32f10x.o(i.SetSysClock) + SetSysClock 0x08001663 Thumb Code 8 system_stm32f10x.o(i.SetSysClock) + i.SetSysClockTo72 0x0800166c Section 0 system_stm32f10x.o(i.SetSysClockTo72) + SetSysClockTo72 0x0800166d Thumb Code 212 system_stm32f10x.o(i.SetSysClockTo72) + i.SysTick_Handler 0x08001748 Section 0 stm32f10x_it.o(i.SysTick_Handler) + i.SystemInit 0x0800174c Section 0 system_stm32f10x.o(i.SystemInit) + i.TIM3_IRQHandler 0x080017ac Section 0 dataproc.o(i.TIM3_IRQHandler) + i.TIM3_Int_Init 0x080017e0 Section 0 tim.o(i.TIM3_Int_Init) + i.TIM_ClearITPendingBit 0x08001820 Section 0 stm32f10x_tim.o(i.TIM_ClearITPendingBit) + i.TIM_Cmd 0x08001826 Section 0 stm32f10x_tim.o(i.TIM_Cmd) + i.TIM_GetITStatus 0x0800183e Section 0 stm32f10x_tim.o(i.TIM_GetITStatus) + i.TIM_ITConfig 0x08001860 Section 0 stm32f10x_tim.o(i.TIM_ITConfig) + i.TIM_TimeBaseInit 0x08001874 Section 0 stm32f10x_tim.o(i.TIM_TimeBaseInit) + i.USART1_IRQHandler 0x08001918 Section 0 printf.o(i.USART1_IRQHandler) + i.USART2_IRQHandler 0x08001964 Section 0 usart2.o(i.USART2_IRQHandler) + i.USART2_Init 0x080019c0 Section 0 usart2.o(i.USART2_Init) + i.USART3_IRQHandler 0x08001a48 Section 0 printf.o(i.USART3_IRQHandler) + i.USART_ClearFlag 0x08001aac Section 0 stm32f10x_usart.o(i.USART_ClearFlag) + i.USART_ClearITPendingBit 0x08001abe Section 0 stm32f10x_usart.o(i.USART_ClearITPendingBit) + i.USART_Cmd 0x08001adc Section 0 stm32f10x_usart.o(i.USART_Cmd) + i.USART_Configuration 0x08001af4 Section 0 printf.o(i.USART_Configuration) + i.USART_GetFlagStatus 0x08001c10 Section 0 stm32f10x_usart.o(i.USART_GetFlagStatus) + i.USART_GetITStatus 0x08001c2a Section 0 stm32f10x_usart.o(i.USART_GetITStatus) + i.USART_ITConfig 0x08001c7e Section 0 stm32f10x_usart.o(i.USART_ITConfig) + i.USART_Init 0x08001cc8 Section 0 stm32f10x_usart.o(i.USART_Init) + i.USART_ReceiveData 0x08001da0 Section 0 stm32f10x_usart.o(i.USART_ReceiveData) + i.USART_SendData 0x08001daa Section 0 stm32f10x_usart.o(i.USART_SendData) + i.UsageFault_Handler 0x08001db2 Section 0 stm32f10x_it.o(i.UsageFault_Handler) + i.__0printf$bare 0x08001db8 Section 0 printfb.o(i.__0printf$bare) + i.__scatterload_copy 0x08001dc8 Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x08001dd6 Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x08001dd8 Section 14 handlers.o(i.__scatterload_zeroinit) + i._printf_core 0x08001de6 Section 0 printfb.o(i._printf_core) + _printf_core 0x08001de7 Thumb Code 34 printfb.o(i._printf_core) + i.delay_ms 0x08001e08 Section 0 delay.o(i.delay_ms) + i.fputc 0x08001e34 Section 0 printf.o(i.fputc) + i.led_init 0x08001e58 Section 0 led.o(i.led_init) + i.main 0x08001eb0 Section 0 main.o(i.main) + .constdata 0x08001f50 Section 10 nrf24l01.o(.constdata) + .data 0x20000000 Section 10 printf.o(.data) + .data 0x2000000a Section 4 usart2.o(.data) + .data 0x2000000e Section 59 dataproc.o(.data) + .data 0x20000049 Section 20 stm32f10x_rcc.o(.data) + APBAHBPrescTable 0x20000049 Data 16 stm32f10x_rcc.o(.data) + ADCPrescTable 0x20000059 Data 4 stm32f10x_rcc.o(.data) + .data 0x20000060 Section 4 stdout.o(.data) + .bss 0x20000064 Section 500 printf.o(.bss) + .bss 0x20000258 Section 64 usart2.o(.bss) + .bss 0x20000298 Section 500 dataproc.o(.bss) + STACK 0x20000490 Section 1024 startup_stm32f10x_hd.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __decompress - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_Size 0x00000130 Number 0 startup_stm32f10x_hd.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f10x_hd.o(RESET) + __Vectors_End 0x08000130 Data 0 startup_stm32f10x_hd.o(RESET) + __main 0x08000131 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x08000131 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x08000135 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x08000139 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x08000139 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x08000139 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x08000139 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_final_cpp 0x08000141 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x08000141 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + Reset_Handler 0x08000145 Thumb Code 8 startup_stm32f10x_hd.o(.text) + ADC1_2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + ADC3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_RX1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_SCE_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel6_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel7_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel4_5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI0_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI15_10_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI9_5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + FLASH_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + FSMC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_ER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_EV_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_ER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_EV_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + PVD_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RCC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTCAlarm_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SDIO_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TAMPER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_BRK_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_CC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_TRG_COM_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_UP_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM6_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM7_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_BRK_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_CC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_TRG_COM_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_UP_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + UART4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + UART5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USBWakeUp_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USB_LP_CAN1_RX0_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + WWDG_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + __scatterload 0x08000169 Thumb Code 28 init.o(.text) + __scatterload_rt2 0x08000169 Thumb Code 0 init.o(.text) + BusFault_Handler 0x0800018d Thumb Code 4 stm32f10x_it.o(i.BusFault_Handler) + CheckSum 0x08000191 Thumb Code 36 dataproc.o(i.CheckSum) + DataProc_1356 0x080001b5 Thumb Code 210 dataproc.o(i.DataProc_1356) + DataProc_Nrf24l01 0x080002ad Thumb Code 352 dataproc.o(i.DataProc_Nrf24l01) + DataProc_USART1 0x08000439 Thumb Code 838 dataproc.o(i.DataProc_USART1) + Data_Init 0x08000871 Thumb Code 240 dataproc.o(i.Data_Init) + DebugMon_Handler 0x08000971 Thumb Code 2 stm32f10x_it.o(i.DebugMon_Handler) + GPIO_Init 0x08000973 Thumb Code 274 stm32f10x_gpio.o(i.GPIO_Init) + GPIO_ResetBits 0x08000a85 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_ResetBits) + GPIO_SetBits 0x08000a89 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_SetBits) + HardFault_Handler 0x08000a8d Thumb Code 4 stm32f10x_it.o(i.HardFault_Handler) + MemManage_Handler 0x08000a91 Thumb Code 4 stm32f10x_it.o(i.MemManage_Handler) + NMI_Handler 0x08000a95 Thumb Code 2 stm32f10x_it.o(i.NMI_Handler) + NRF24L01_Check 0x08000a99 Thumb Code 80 nrf24l01.o(i.NRF24L01_Check) + NRF24L01_Init 0x08000af1 Thumb Code 228 nrf24l01.o(i.NRF24L01_Init) + NRF24L01_RX_Mode 0x08000bed Thumb Code 166 nrf24l01.o(i.NRF24L01_RX_Mode) + NRF24L01_Read_Buf 0x08000ca5 Thumb Code 114 nrf24l01.o(i.NRF24L01_Read_Buf) + NRF24L01_Read_Reg 0x08000d21 Thumb Code 78 nrf24l01.o(i.NRF24L01_Read_Reg) + NRF24L01_RxPacket 0x08000d81 Thumb Code 66 nrf24l01.o(i.NRF24L01_RxPacket) + NRF24L01_TX_Mode 0x08000dc5 Thumb Code 136 nrf24l01.o(i.NRF24L01_TX_Mode) + NRF24L01_Write_Buf 0x08000e5d Thumb Code 114 nrf24l01.o(i.NRF24L01_Write_Buf) + NRF24L01_Write_Reg 0x08000ed9 Thumb Code 84 nrf24l01.o(i.NRF24L01_Write_Reg) + NVIC_Configuration 0x08000f3d Thumb Code 124 main.o(i.NVIC_Configuration) + NVIC_Init 0x08000fb9 Thumb Code 102 misc.o(i.NVIC_Init) + NVIC_PriorityGroupConfig 0x0800102d Thumb Code 10 misc.o(i.NVIC_PriorityGroupConfig) + PendSV_Handler 0x08001041 Thumb Code 2 stm32f10x_it.o(i.PendSV_Handler) + RCC_APB1PeriphClockCmd 0x08001045 Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + RCC_APB2PeriphClockCmd 0x08001065 Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + RCC_Configuration 0x08001085 Thumb Code 106 main.o(i.RCC_Configuration) + RCC_DeInit 0x080010f1 Thumb Code 64 stm32f10x_rcc.o(i.RCC_DeInit) + RCC_GetClocksFreq 0x0800113d Thumb Code 192 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + RCC_GetFlagStatus 0x08001211 Thumb Code 56 stm32f10x_rcc.o(i.RCC_GetFlagStatus) + RCC_GetSYSCLKSource 0x0800124d Thumb Code 10 stm32f10x_rcc.o(i.RCC_GetSYSCLKSource) + RCC_HCLKConfig 0x0800125d Thumb Code 18 stm32f10x_rcc.o(i.RCC_HCLKConfig) + RCC_HSEConfig 0x08001275 Thumb Code 70 stm32f10x_rcc.o(i.RCC_HSEConfig) + RCC_PCLK1Config 0x080012c1 Thumb Code 18 stm32f10x_rcc.o(i.RCC_PCLK1Config) + RCC_PCLK2Config 0x080012d9 Thumb Code 20 stm32f10x_rcc.o(i.RCC_PCLK2Config) + RCC_PLLCmd 0x080012f1 Thumb Code 6 stm32f10x_rcc.o(i.RCC_PLLCmd) + RCC_PLLConfig 0x080012fd Thumb Code 24 stm32f10x_rcc.o(i.RCC_PLLConfig) + RCC_SYSCLKConfig 0x08001319 Thumb Code 18 stm32f10x_rcc.o(i.RCC_SYSCLKConfig) + RCC_WaitForHSEStartUp 0x08001331 Thumb Code 56 stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) + SPI1_Init 0x08001369 Thumb Code 122 spi.o(i.SPI1_Init) + SPI2_Init 0x080013ed Thumb Code 132 spi.o(i.SPI2_Init) + SPI_Cmd 0x08001479 Thumb Code 24 stm32f10x_spi.o(i.SPI_Cmd) + SPI_I2S_GetFlagStatus 0x08001491 Thumb Code 18 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + SPI_I2S_ReceiveData 0x080014a3 Thumb Code 6 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + SPI_I2S_SendData 0x080014a9 Thumb Code 4 stm32f10x_spi.o(i.SPI_I2S_SendData) + SPI_Init 0x080014ad Thumb Code 60 stm32f10x_spi.o(i.SPI_Init) + SPI_ReadWriteByte 0x080014e9 Thumb Code 158 spi.o(i.SPI_ReadWriteByte) + SPI_SetSpeed 0x08001591 Thumb Code 72 spi.o(i.SPI_SetSpeed) + SVC_Handler 0x080015e1 Thumb Code 2 stm32f10x_it.o(i.SVC_Handler) + SendConsoleByte 0x080015e5 Thumb Code 14 printf.o(i.SendConsoleByte) + SendConsoleData 0x080015f9 Thumb Code 18 printf.o(i.SendConsoleData) + SendUartByte 0x08001611 Thumb Code 32 printf.o(i.SendUartByte) + SendUartData 0x08001631 Thumb Code 50 printf.o(i.SendUartData) + SysTick_Handler 0x08001749 Thumb Code 2 stm32f10x_it.o(i.SysTick_Handler) + SystemInit 0x0800174d Thumb Code 78 system_stm32f10x.o(i.SystemInit) + TIM3_IRQHandler 0x080017ad Thumb Code 38 dataproc.o(i.TIM3_IRQHandler) + TIM3_Int_Init 0x080017e1 Thumb Code 60 tim.o(i.TIM3_Int_Init) + TIM_ClearITPendingBit 0x08001821 Thumb Code 6 stm32f10x_tim.o(i.TIM_ClearITPendingBit) + TIM_Cmd 0x08001827 Thumb Code 24 stm32f10x_tim.o(i.TIM_Cmd) + TIM_GetITStatus 0x0800183f Thumb Code 34 stm32f10x_tim.o(i.TIM_GetITStatus) + TIM_ITConfig 0x08001861 Thumb Code 18 stm32f10x_tim.o(i.TIM_ITConfig) + TIM_TimeBaseInit 0x08001875 Thumb Code 122 stm32f10x_tim.o(i.TIM_TimeBaseInit) + USART1_IRQHandler 0x08001919 Thumb Code 60 printf.o(i.USART1_IRQHandler) + USART2_IRQHandler 0x08001965 Thumb Code 78 usart2.o(i.USART2_IRQHandler) + USART2_Init 0x080019c1 Thumb Code 126 usart2.o(i.USART2_Init) + USART3_IRQHandler 0x08001a49 Thumb Code 88 printf.o(i.USART3_IRQHandler) + USART_ClearFlag 0x08001aad Thumb Code 18 stm32f10x_usart.o(i.USART_ClearFlag) + USART_ClearITPendingBit 0x08001abf Thumb Code 30 stm32f10x_usart.o(i.USART_ClearITPendingBit) + USART_Cmd 0x08001add Thumb Code 24 stm32f10x_usart.o(i.USART_Cmd) + USART_Configuration 0x08001af5 Thumb Code 266 printf.o(i.USART_Configuration) + USART_GetFlagStatus 0x08001c11 Thumb Code 26 stm32f10x_usart.o(i.USART_GetFlagStatus) + USART_GetITStatus 0x08001c2b Thumb Code 84 stm32f10x_usart.o(i.USART_GetITStatus) + USART_ITConfig 0x08001c7f Thumb Code 74 stm32f10x_usart.o(i.USART_ITConfig) + USART_Init 0x08001cc9 Thumb Code 210 stm32f10x_usart.o(i.USART_Init) + USART_ReceiveData 0x08001da1 Thumb Code 10 stm32f10x_usart.o(i.USART_ReceiveData) + USART_SendData 0x08001dab Thumb Code 8 stm32f10x_usart.o(i.USART_SendData) + UsageFault_Handler 0x08001db3 Thumb Code 4 stm32f10x_it.o(i.UsageFault_Handler) + __0printf$bare 0x08001db9 Thumb Code 8 printfb.o(i.__0printf$bare) + __1printf$bare 0x08001db9 Thumb Code 0 printfb.o(i.__0printf$bare) + __2printf 0x08001db9 Thumb Code 0 printfb.o(i.__0printf$bare) + __scatterload_copy 0x08001dc9 Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x08001dd7 Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x08001dd9 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + delay_ms 0x08001e09 Thumb Code 42 delay.o(i.delay_ms) + fputc 0x08001e35 Thumb Code 32 printf.o(i.fputc) + led_init 0x08001e59 Thumb Code 84 led.o(i.led_init) + main 0x08001eb1 Thumb Code 136 main.o(i.main) + TX_ADDRESS 0x08001f50 Data 5 nrf24l01.o(.constdata) + RX_ADDRESS 0x08001f55 Data 5 nrf24l01.o(.constdata) + Region$$Table$$Base 0x08001f5c Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08001f7c Number 0 anon$$obj.o(Region$$Table) + UARTtoConsole_RxBufferWr 0x20000000 Data 1 printf.o(.data) + UARTtoConsole_RxBufferRd 0x20000001 Data 1 printf.o(.data) + USART1_TX_CNT 0x20000002 Data 1 printf.o(.data) + USART1_RX_CNT 0x20000003 Data 1 printf.o(.data) + USART1_REC_Status 0x20000004 Data 2 printf.o(.data) + USART3_TX_CNT 0x20000006 Data 1 printf.o(.data) + USART3_RX_CNT 0x20000007 Data 1 printf.o(.data) + USART3_REC_Status 0x20000008 Data 2 printf.o(.data) + USART2_TX_CNT 0x2000000a Data 1 usart2.o(.data) + USART2_RX_CNT 0x2000000b Data 1 usart2.o(.data) + USART2_REC_Status 0x2000000c Data 2 usart2.o(.data) + CheckData_1356 0x2000000e Data 10 dataproc.o(.data) + GetNum_1356 0x20000018 Data 5 dataproc.o(.data) + CmdRspBufferWr_Rx 0x2000001d Data 1 dataproc.o(.data) + txBuf 0x2000001e Data 32 dataproc.o(.data) + rspFlag 0x2000003e Data 1 dataproc.o(.data) + wrNumFlag 0x2000003f Data 1 dataproc.o(.data) + count 0x20000040 Data 2 dataproc.o(.data) + flag_1ms 0x20000042 Data 1 dataproc.o(.data) + idBuf 0x20000043 Data 5 dataproc.o(.data) + newIdFlag 0x20000048 Data 1 dataproc.o(.data) + __stdout 0x20000060 Data 4 stdout.o(.data) + UARTtoConsole_RxBuffer 0x20000064 Data 100 printf.o(.bss) + USART1_RX_BUF 0x200000c8 Data 200 printf.o(.bss) + USART3_RX_BUF 0x20000190 Data 200 printf.o(.bss) + USART2_RX_BUF 0x20000258 Data 64 usart2.o(.bss) + uartSendData 0x20000298 Data 100 dataproc.o(.bss) + uartRecData 0x200002fc Data 100 dataproc.o(.bss) + uartSendRdNumData 0x20000360 Data 100 dataproc.o(.bss) + uartSendWrNumOkData 0x200003c4 Data 100 dataproc.o(.bss) + CmdRspBuffer 0x20000428 Data 100 dataproc.o(.bss) + __initial_sp 0x20000890 Data 0 startup_stm32f10x_hd.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000131 + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00001fe0, Max: 0x00040000, ABSOLUTE) + + Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x00001f7c, Max: 0x00040000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x00000130 Data RO 2139 RESET startup_stm32f10x_hd.o + 0x08000130 0x00000000 Code RO 2144 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x08000130 0x00000004 Code RO 2407 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x08000134 0x00000004 Code RO 2410 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x08000138 0x00000000 Code RO 2412 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x08000138 0x00000000 Code RO 2414 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x08000138 0x00000008 Code RO 2415 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x08000140 0x00000000 Code RO 2417 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o) + 0x08000140 0x00000000 Code RO 2419 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o) + 0x08000140 0x00000004 Code RO 2408 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000144 0x00000024 Code RO 2140 .text startup_stm32f10x_hd.o + 0x08000168 0x00000024 Code RO 2437 .text mc_w.l(init.o) + 0x0800018c 0x00000004 Code RO 635 i.BusFault_Handler stm32f10x_it.o + 0x08000190 0x00000024 Code RO 485 i.CheckSum dataproc.o + 0x080001b4 0x000000f8 Code RO 486 i.DataProc_1356 dataproc.o + 0x080002ac 0x0000018c Code RO 487 i.DataProc_Nrf24l01 dataproc.o + 0x08000438 0x00000438 Code RO 488 i.DataProc_USART1 dataproc.o + 0x08000870 0x00000100 Code RO 489 i.Data_Init dataproc.o + 0x08000970 0x00000002 Code RO 636 i.DebugMon_Handler stm32f10x_it.o + 0x08000972 0x00000112 Code RO 1217 i.GPIO_Init stm32f10x_gpio.o + 0x08000a84 0x00000004 Code RO 1224 i.GPIO_ResetBits stm32f10x_gpio.o + 0x08000a88 0x00000004 Code RO 1225 i.GPIO_SetBits stm32f10x_gpio.o + 0x08000a8c 0x00000004 Code RO 637 i.HardFault_Handler stm32f10x_it.o + 0x08000a90 0x00000004 Code RO 638 i.MemManage_Handler stm32f10x_it.o + 0x08000a94 0x00000002 Code RO 639 i.NMI_Handler stm32f10x_it.o + 0x08000a96 0x00000002 PAD + 0x08000a98 0x00000058 Code RO 371 i.NRF24L01_Check nrf24l01.o + 0x08000af0 0x000000fc Code RO 373 i.NRF24L01_Init nrf24l01.o + 0x08000bec 0x000000b8 Code RO 374 i.NRF24L01_RX_Mode nrf24l01.o + 0x08000ca4 0x0000007c Code RO 375 i.NRF24L01_Read_Buf nrf24l01.o + 0x08000d20 0x00000060 Code RO 376 i.NRF24L01_Read_Reg nrf24l01.o + 0x08000d80 0x00000042 Code RO 377 i.NRF24L01_RxPacket nrf24l01.o + 0x08000dc2 0x00000002 PAD + 0x08000dc4 0x00000098 Code RO 378 i.NRF24L01_TX_Mode nrf24l01.o + 0x08000e5c 0x0000007c Code RO 380 i.NRF24L01_Write_Buf nrf24l01.o + 0x08000ed8 0x00000064 Code RO 381 i.NRF24L01_Write_Reg nrf24l01.o + 0x08000f3c 0x0000007c Code RO 1 i.NVIC_Configuration main.o + 0x08000fb8 0x00000074 Code RO 1172 i.NVIC_Init misc.o + 0x0800102c 0x00000014 Code RO 1173 i.NVIC_PriorityGroupConfig misc.o + 0x08001040 0x00000002 Code RO 640 i.PendSV_Handler stm32f10x_it.o + 0x08001042 0x00000002 PAD + 0x08001044 0x00000020 Code RO 719 i.RCC_APB1PeriphClockCmd stm32f10x_rcc.o + 0x08001064 0x00000020 Code RO 721 i.RCC_APB2PeriphClockCmd stm32f10x_rcc.o + 0x08001084 0x0000006a Code RO 2 i.RCC_Configuration main.o + 0x080010ee 0x00000002 PAD + 0x080010f0 0x0000004c Code RO 728 i.RCC_DeInit stm32f10x_rcc.o + 0x0800113c 0x000000d4 Code RO 729 i.RCC_GetClocksFreq stm32f10x_rcc.o + 0x08001210 0x0000003c Code RO 730 i.RCC_GetFlagStatus stm32f10x_rcc.o + 0x0800124c 0x00000010 Code RO 732 i.RCC_GetSYSCLKSource stm32f10x_rcc.o + 0x0800125c 0x00000018 Code RO 733 i.RCC_HCLKConfig stm32f10x_rcc.o + 0x08001274 0x0000004c Code RO 734 i.RCC_HSEConfig stm32f10x_rcc.o + 0x080012c0 0x00000018 Code RO 740 i.RCC_PCLK1Config stm32f10x_rcc.o + 0x080012d8 0x00000018 Code RO 741 i.RCC_PCLK2Config stm32f10x_rcc.o + 0x080012f0 0x0000000c Code RO 742 i.RCC_PLLCmd stm32f10x_rcc.o + 0x080012fc 0x0000001c Code RO 743 i.RCC_PLLConfig stm32f10x_rcc.o + 0x08001318 0x00000018 Code RO 746 i.RCC_SYSCLKConfig stm32f10x_rcc.o + 0x08001330 0x00000038 Code RO 748 i.RCC_WaitForHSEStartUp stm32f10x_rcc.o + 0x08001368 0x00000084 Code RO 455 i.SPI1_Init spi.o + 0x080013ec 0x0000008c Code RO 456 i.SPI2_Init spi.o + 0x08001478 0x00000018 Code RO 1333 i.SPI_Cmd stm32f10x_spi.o + 0x08001490 0x00000012 Code RO 1341 i.SPI_I2S_GetFlagStatus stm32f10x_spi.o + 0x080014a2 0x00000006 Code RO 1344 i.SPI_I2S_ReceiveData stm32f10x_spi.o + 0x080014a8 0x00000004 Code RO 1345 i.SPI_I2S_SendData stm32f10x_spi.o + 0x080014ac 0x0000003c Code RO 1346 i.SPI_Init stm32f10x_spi.o + 0x080014e8 0x000000a8 Code RO 457 i.SPI_ReadWriteByte spi.o + 0x08001590 0x00000050 Code RO 458 i.SPI_SetSpeed spi.o + 0x080015e0 0x00000002 Code RO 641 i.SVC_Handler stm32f10x_it.o + 0x080015e2 0x00000002 PAD + 0x080015e4 0x00000014 Code RO 148 i.SendConsoleByte printf.o + 0x080015f8 0x00000018 Code RO 149 i.SendConsoleData printf.o + 0x08001610 0x00000020 Code RO 151 i.SendUartByte printf.o + 0x08001630 0x00000032 Code RO 152 i.SendUartData printf.o + 0x08001662 0x00000008 Code RO 2103 i.SetSysClock system_stm32f10x.o + 0x0800166a 0x00000002 PAD + 0x0800166c 0x000000dc Code RO 2104 i.SetSysClockTo72 system_stm32f10x.o + 0x08001748 0x00000002 Code RO 642 i.SysTick_Handler stm32f10x_it.o + 0x0800174a 0x00000002 PAD + 0x0800174c 0x00000060 Code RO 2106 i.SystemInit system_stm32f10x.o + 0x080017ac 0x00000034 Code RO 490 i.TIM3_IRQHandler dataproc.o + 0x080017e0 0x00000040 Code RO 537 i.TIM3_Int_Init tim.o + 0x08001820 0x00000006 Code RO 1486 i.TIM_ClearITPendingBit stm32f10x_tim.o + 0x08001826 0x00000018 Code RO 1491 i.TIM_Cmd stm32f10x_tim.o + 0x0800183e 0x00000022 Code RO 1512 i.TIM_GetITStatus stm32f10x_tim.o + 0x08001860 0x00000012 Code RO 1516 i.TIM_ITConfig stm32f10x_tim.o + 0x08001872 0x00000002 PAD + 0x08001874 0x000000a4 Code RO 1562 i.TIM_TimeBaseInit stm32f10x_tim.o + 0x08001918 0x0000004c Code RO 155 i.USART1_IRQHandler printf.o + 0x08001964 0x0000005c Code RO 346 i.USART2_IRQHandler usart2.o + 0x080019c0 0x00000088 Code RO 347 i.USART2_Init usart2.o + 0x08001a48 0x00000064 Code RO 156 i.USART3_IRQHandler printf.o + 0x08001aac 0x00000012 Code RO 986 i.USART_ClearFlag stm32f10x_usart.o + 0x08001abe 0x0000001e Code RO 987 i.USART_ClearITPendingBit stm32f10x_usart.o + 0x08001adc 0x00000018 Code RO 990 i.USART_Cmd stm32f10x_usart.o + 0x08001af4 0x0000011c Code RO 157 i.USART_Configuration printf.o + 0x08001c10 0x0000001a Code RO 993 i.USART_GetFlagStatus stm32f10x_usart.o + 0x08001c2a 0x00000054 Code RO 994 i.USART_GetITStatus stm32f10x_usart.o + 0x08001c7e 0x0000004a Code RO 996 i.USART_ITConfig stm32f10x_usart.o + 0x08001cc8 0x000000d8 Code RO 997 i.USART_Init stm32f10x_usart.o + 0x08001da0 0x0000000a Code RO 1004 i.USART_ReceiveData stm32f10x_usart.o + 0x08001daa 0x00000008 Code RO 1007 i.USART_SendData stm32f10x_usart.o + 0x08001db2 0x00000004 Code RO 643 i.UsageFault_Handler stm32f10x_it.o + 0x08001db6 0x00000002 PAD + 0x08001db8 0x00000010 Code RO 2148 i.__0printf$bare mc_w.l(printfb.o) + 0x08001dc8 0x0000000e Code RO 2449 i.__scatterload_copy mc_w.l(handlers.o) + 0x08001dd6 0x00000002 Code RO 2450 i.__scatterload_null mc_w.l(handlers.o) + 0x08001dd8 0x0000000e Code RO 2451 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x08001de6 0x00000022 Code RO 2155 i._printf_core mc_w.l(printfb.o) + 0x08001e08 0x0000002a Code RO 316 i.delay_ms delay.o + 0x08001e32 0x00000002 PAD + 0x08001e34 0x00000024 Code RO 159 i.fputc printf.o + 0x08001e58 0x00000058 Code RO 331 i.led_init led.o + 0x08001eb0 0x000000a0 Code RO 3 i.main main.o + 0x08001f50 0x0000000a Data RO 382 .constdata nrf24l01.o + 0x08001f5a 0x00000002 PAD + 0x08001f5c 0x00000020 Data RO 2447 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x00000890, Max: 0x0000c000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x0000000a Data RW 161 .data printf.o + 0x2000000a 0x00000004 Data RW 349 .data usart2.o + 0x2000000e 0x0000003b Data RW 492 .data dataproc.o + 0x20000049 0x00000014 Data RW 749 .data stm32f10x_rcc.o + 0x2000005d 0x00000003 PAD + 0x20000060 0x00000004 Data RW 2421 .data mc_w.l(stdout.o) + 0x20000064 0x000001f4 Zero RW 160 .bss printf.o + 0x20000258 0x00000040 Zero RW 348 .bss usart2.o + 0x20000298 0x000001f4 Zero RW 491 .bss dataproc.o + 0x2000048c 0x00000004 PAD + 0x20000490 0x00000400 Zero RW 2137 STACK startup_stm32f10x_hd.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 0 0 0 0 0 32 core_cm3.o + 2068 354 0 59 500 6365 dataproc.o + 42 0 0 0 0 511 delay.o + 88 4 0 0 0 463 led.o + 390 24 0 0 0 212140 main.o + 136 24 0 0 0 3387 misc.o + 1186 120 10 0 0 6469 nrf24l01.o + 622 62 0 10 500 229995 printf.o + 520 36 0 0 0 2339 spi.o + 36 8 304 0 1024 844 startup_stm32f10x_hd.o + 282 0 0 0 0 11568 stm32f10x_gpio.o + 26 0 0 0 0 3666 stm32f10x_it.o + 696 92 0 20 0 19526 stm32f10x_rcc.o + 112 0 0 0 0 10938 stm32f10x_spi.o + 246 42 0 0 0 22930 stm32f10x_tim.o + 490 6 0 0 0 22405 stm32f10x_usart.o + 324 26 0 0 0 1829 system_stm32f10x.o + 64 4 0 0 0 222900 tim.o + 228 24 0 4 64 1684 usart2.o + + ---------------------------------------------------------------------- + 7576 826 348 96 2092 779991 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 20 0 2 3 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 8 4 0 0 0 0 entry9a.o + 30 0 0 0 0 0 handlers.o + 36 8 0 0 0 68 init.o + 50 8 0 0 0 152 printfb.o + 0 0 0 4 0 0 stdout.o + + ---------------------------------------------------------------------- + 136 24 0 4 0 220 Library Totals + 0 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 136 24 0 4 0 220 mc_w.l + + ---------------------------------------------------------------------- + 136 24 0 4 0 220 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 7712 850 348 100 2092 775895 Grand Totals + 7712 850 348 100 2092 775895 ELF Image Totals + 7712 850 348 100 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 8060 ( 7.87kB) + Total RW Size (RW Data + ZI Data) 2192 ( 2.14kB) + Total ROM Size (Code + RO Data + RW Data) 8160 ( 7.97kB) + +============================================================================== + diff --git a/RVMDK/List/Printf_PC.map b/RVMDK/List/Printf_PC.map new file mode 100644 index 0000000..3acfb56 --- /dev/null +++ b/RVMDK/List/Printf_PC.map @@ -0,0 +1,1755 @@ +Component: ARM Compiler 5.06 update 1 (build 61) Tool: armlink [4d35a8] + +============================================================================== + +Section Cross References + + printf.o(i.DegugPrintf) refers to printf.o(i.HexToAscii) for HexToAscii + printf.o(i.DegugPrintf) refers to printf.o(i.SendUSART2Byte) for SendUSART2Byte + printf.o(i.SendConsoleByte) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendConsoleData) refers to printf.o(i.SendUartData) for SendUartData + printf.o(i.SendConsoleStr) refers to printf.o(i.SendUartStr) for SendUartStr + printf.o(i.SendUSART2Byte) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendUSART2Str) refers to printf.o(i.SendUartStr) for SendUartStr + printf.o(i.SendUartByte) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.SendUartByte) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.SendUartData) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendUartRStr) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.SendUartStr) refers to printf.o(i.SendUartByte) for SendUartByte + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + printf.o(i.USART1_IRQHandler) refers to printf.o(.bss) for USART1_RX_BUF + printf.o(i.USART1_IRQHandler) refers to printf.o(.data) for USART1_RX_CNT + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + printf.o(i.USART3_IRQHandler) refers to printf.o(.bss) for USART3_RX_BUF + printf.o(i.USART3_IRQHandler) refers to printf.o(.data) for USART3_RX_CNT + printf.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + printf.o(i.USART_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + printf.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + printf.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + printf.o(i.Usart1_SendData) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + printf.o(i.Usart1_SendData) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + printf.o(i.fputc) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + main.o(i.IWDG_Feed) refers to stm32f10x_iwdg.o(i.IWDG_ReloadCounter) for IWDG_ReloadCounter + main.o(i.IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd) for IWDG_WriteAccessCmd + main.o(i.IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_SetPrescaler) for IWDG_SetPrescaler + main.o(i.IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_SetReload) for IWDG_SetReload + main.o(i.IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_ReloadCounter) for IWDG_ReloadCounter + main.o(i.IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_Enable) for IWDG_Enable + main.o(i.NRF24L01_RX_TelPo_CONFIG1) refers to main.o(i.NRF24L01_TELPO_RX_Mode) for NRF24L01_TELPO_RX_Mode + main.o(i.NRF24L01_RxPacket1) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + main.o(i.NRF24L01_RxPacket1) refers to nrf24l01.o(i.NRF24L01_Read_Reg) for NRF24L01_Read_Reg + main.o(i.NRF24L01_RxPacket1) refers to nrf24l01.o(i.NRF24L01_Read_Buf) for NRF24L01_Read_Buf + main.o(i.NRF24L01_RxPacket1) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + main.o(i.NRF24L01_RxPacket1) refers to delay.o(i.delay_5us) for delay_5us + main.o(i.NRF24L01_TELPO_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + main.o(i.NRF24L01_TELPO_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + main.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig + main.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_Init) for NVIC_Init + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + main.o(i.RCC_Configuration) refers to misc.o(i.SysTick_CLKSourceConfig) for SysTick_CLKSourceConfig + main.o(i.main) refers to main.o(i.RCC_Configuration) for RCC_Configuration + main.o(i.main) refers to main.o(i.NVIC_Configuration) for NVIC_Configuration + main.o(i.main) refers to main.o(i.IWDG_Init) for IWDG_Init + main.o(i.main) refers to main.o(i.IWDG_Feed) for IWDG_Feed + main.o(i.main) refers to tim.o(i.TIM3_Int_Init) for TIM3_Int_Init + main.o(i.main) refers to led.o(i.led_init) for led_init + main.o(i.main) refers to printf.o(i.USART_Configuration) for USART_Configuration + main.o(i.main) refers to usart2.o(i.USART2_Init) for USART2_Init + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_Init) for NRF24L01_Init + main.o(i.main) refers to printfb.o(i.__0printf$bare) for __2printf + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_Check) for NRF24L01_Check + main.o(i.main) refers to dataproc.o(i.Data_Init) for Data_Init + main.o(i.main) refers to delay.o(i.delay_ms) for delay_ms + main.o(i.main) refers to printf.o(i.DegugPrintf) for DegugPrintf + main.o(i.main) refers to printf.o(i.SendUSART2Str) for SendUSART2Str + main.o(i.main) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + main.o(i.main) refers to flash.o(i.Readpara_from_flash) for Readpara_from_flash + main.o(i.main) refers to dataproc.o(i.DataProc_1356) for DataProc_1356 + main.o(i.main) refers to dataproc.o(i.DataProc_USART1) for DataProc_USART1 + main.o(i.main) refers to flash.o(.bss) for Save_Buffer + main.o(i.main) refers to dataproc.o(.data) for protocol_config_flg + nrf24l01.o(i.NRF24L01_Check) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_Check) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_Check) refers to nrf24l01.o(i.NRF24L01_Read_Buf) for NRF24L01_Read_Buf + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + nrf24l01.o(i.NRF24L01_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + nrf24l01.o(i.NRF24L01_Init) refers to spi.o(i.SPI2_Init) for SPI2_Init + nrf24l01.o(i.NRF24L01_Init) refers to spi.o(i.SPI1_Init) for SPI1_Init + nrf24l01.o(i.NRF24L01_Init) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_RX_AHDX_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_AHDX_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_AHDX_CONFIG) refers to nrf24l01.o(.constdata) for ANHUI_DIANXIN + nrf24l01.o(i.NRF24L01_RX_AnHui_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_AnHui_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_AnHui_CONFIG) refers to nrf24l01.o(.constdata) for AN_HUI + nrf24l01.o(i.NRF24L01_RX_CQYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_CQYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_CQYD_CONFIG) refers to nrf24l01.o(.constdata) for CHONG_QIN_YI_DONG + nrf24l01.o(i.NRF24L01_RX_DH_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_DH_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_DH_CONFIG) refers to nrf24l01.o(.constdata) for DH + nrf24l01.o(i.NRF24L01_RX_FJZZ_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_FJZZ_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_FJZZ_CONFIG) refers to nrf24l01.o(.constdata) for FU_JIAN_ZHEN_ZHUO + nrf24l01.o(i.NRF24L01_RX_GSYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_GSYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_GSYD_CONFIG) refers to nrf24l01.o(.constdata) for GAN_SU_YI_DONG + nrf24l01.o(i.NRF24L01_RX_GXYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_GXYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_GXYD_CONFIG) refers to nrf24l01.o(.constdata) for GUANG_XI_YI_DONG + nrf24l01.o(i.NRF24L01_RX_GuiZhou_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_GuiZhou_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_GuiZhou_CONFIG) refers to nrf24l01.o(.constdata) for GUI_ZHOU + nrf24l01.o(i.NRF24L01_RX_JiangXi_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_JiangXi_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_JiangXi_CONFIG) refers to nrf24l01.o(.constdata) for Jiang_Xi + nrf24l01.o(i.NRF24L01_RX_LIAO_NING_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_LIAO_NING_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_LIAO_NING_CONFIG) refers to nrf24l01.o(.constdata) for LIAO_NING + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_Mode) refers to nrf24l01.o(.constdata) for RX_ADDRESS + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_JiangXi_CONFIG) for NRF24L01_RX_JiangXi_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_TelPo_CONFIG) for NRF24L01_RX_TelPo_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_YunNan_CONFIG) for NRF24L01_RX_YunNan_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_GuiZhou_CONFIG) for NRF24L01_RX_GuiZhou_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_SiChuan_CONFIG) for NRF24L01_RX_SiChuan_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_NeiMengGu_CONFIG) for NRF24L01_RX_NeiMengGu_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_AnHui_CONFIG) for NRF24L01_RX_AnHui_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_ShanXiXinNuo_CONFIG) for NRF24L01_RX_ShanXiXinNuo_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_VCM_CONFIG) for NRF24L01_RX_VCM_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_LIAO_NING_CONFIG) for NRF24L01_RX_LIAO_NING_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_NEW_LIAO_NING_CONFIG) for NRF24L01_RX_NEW_LIAO_NING_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_TP_CONFIG) for NRF24L01_RX_TP_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_NMGYD_CONFIG) for NRF24L01_RX_NMGYD_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_GXYD_CONFIG) for NRF24L01_RX_GXYD_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_FJZZ_CONFIG) for NRF24L01_RX_FJZZ_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_SZML_CONFIG) for NRF24L01_RX_SZML_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_CQYD_CONFIG) for NRF24L01_RX_CQYD_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_SXYD_CONFIG) for NRF24L01_RX_SXYD_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_GSYD_CONFIG) for NRF24L01_RX_GSYD_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_XDF_CONFIG) for NRF24L01_RX_XDF_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_DH_CONFIG) for NRF24L01_RX_DH_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) refers to nrf24l01.o(i.NRF24L01_RX_AHDX_CONFIG) for NRF24L01_RX_AHDX_CONFIG + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK_VCOM) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK_VCOM) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_Mode_NOACK_VCOM) refers to nrf24l01.o(.constdata) for RX_ADDRESS + nrf24l01.o(i.NRF24L01_RX_NEW_LIAO_NING_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_NEW_LIAO_NING_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_NEW_LIAO_NING_CONFIG) refers to nrf24l01.o(.constdata) for NEW_LIAO_NING + nrf24l01.o(i.NRF24L01_RX_NMGYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_NMGYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_NMGYD_CONFIG) refers to nrf24l01.o(.constdata) for NEI_MENG_GU_YI_DONG + nrf24l01.o(i.NRF24L01_RX_NeiMengGu_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_NeiMengGu_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_NeiMengGu_CONFIG) refers to nrf24l01.o(.constdata) for NEI_MENG_GU + nrf24l01.o(i.NRF24L01_RX_SXYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_SXYD_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_SXYD_CONFIG) refers to nrf24l01.o(.constdata) for SHAN_XI_YI_DONG + nrf24l01.o(i.NRF24L01_RX_SZML_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_SZML_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_SZML_CONFIG) refers to nrf24l01.o(.constdata) for SU_ZHOU_MU_LANG + nrf24l01.o(i.NRF24L01_RX_ShanXiXinNuo_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_ShanXiXinNuo_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_ShanXiXinNuo_CONFIG) refers to nrf24l01.o(.constdata) for SHAN_XI_XIN_NUO + nrf24l01.o(i.NRF24L01_RX_SiChuan_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_SiChuan_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_SiChuan_CONFIG) refers to nrf24l01.o(.constdata) for SI_CHUAN + nrf24l01.o(i.NRF24L01_RX_TP_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_TP_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_TP_CONFIG) refers to nrf24l01.o(.constdata) for TP + nrf24l01.o(i.NRF24L01_RX_TelPo_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_TelPo_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_TelPo_CONFIG) refers to nrf24l01.o(.constdata) for TEL_PO + nrf24l01.o(i.NRF24L01_RX_VCM_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_VCM_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_VCM_CONFIG) refers to nrf24l01.o(.constdata) for VCM + nrf24l01.o(i.NRF24L01_RX_XDF_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_XDF_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_XDF_CONFIG) refers to nrf24l01.o(.constdata) for XDF + nrf24l01.o(i.NRF24L01_RX_YunNan_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RX_YunNan_CONFIG) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_RX_YunNan_CONFIG) refers to nrf24l01.o(.constdata) for YUN_NAN + nrf24l01.o(i.NRF24L01_Read_Buf) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_Read_Reg) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_RxPacket) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Reg) for NRF24L01_Read_Reg + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_RxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Buf) for NRF24L01_Read_Buf + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_TX_Mode) refers to nrf24l01.o(.constdata) for TX_ADDRESS + nrf24l01.o(i.NRF24L01_TxPacket) refers to spi.o(i.SPI_SetSpeed) for SPI_SetSpeed + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Read_Reg) for NRF24L01_Read_Reg + nrf24l01.o(i.NRF24L01_TxPacket) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.NRF24L01_Write_Buf) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.NRF24L01_Write_Reg) refers to spi.o(i.SPI_ReadWriteByte) for SPI_ReadWriteByte + nrf24l01.o(i.RF24_CarrierTest) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + nrf24l01.o(i.RF24_CarrierTest) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + nrf24l01.o(i.RF24_CarrierTest) refers to delay.o(i.delay_5us) for delay_5us + nrf24l01.o(i.RF24_CarrierTest) refers to nrf24l01.o(.constdata) for NEW_LIAO_NING + tim.o(i.TIM3_Int_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + tim.o(i.TIM3_Int_Init) refers to stm32f10x_tim.o(i.TIM_TimeBaseInit) for TIM_TimeBaseInit + tim.o(i.TIM3_Int_Init) refers to stm32f10x_tim.o(i.TIM_ITConfig) for TIM_ITConfig + tim.o(i.TIM3_Int_Init) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd + spi.o(i.SPI1_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + spi.o(i.SPI1_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + spi.o(i.SPI1_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.SPI1_Init) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init + spi.o(i.SPI1_Init) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + spi.o(i.SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + spi.o(i.SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + spi.o(i.SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + spi.o(i.SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init + spi.o(i.SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) for SPI_I2S_GetFlagStatus + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_SendData) for SPI_I2S_SendData + spi.o(i.SPI_ReadWriteByte) refers to stm32f10x_spi.o(i.SPI_I2S_ReceiveData) for SPI_I2S_ReceiveData + spi.o(i.SPI_SetSpeed) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + led.o(i.led_init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + led.o(i.led_init) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + dataproc.o(i.DataProc_1356) refers to main.o(i.IWDG_Feed) for IWDG_Feed + dataproc.o(i.DataProc_1356) refers to memseta.o(.text) for __aeabi_memclr + dataproc.o(i.DataProc_1356) refers to printf.o(.data) for USART3_RX_CNT + dataproc.o(i.DataProc_1356) refers to printf.o(.bss) for USART3_RX_BUF + dataproc.o(i.DataProc_1356) refers to dataproc.o(.data) for CheckData_1356 + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to dataproc.o(i.CheckSum) for CheckSum + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to main.o(i.IWDG_Feed) for IWDG_Feed + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to nrf24l01.o(i.NRF24L01_RxPacket) for NRF24L01_RxPacket + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to printf.o(i.SendUSART2Byte) for SendUSART2Byte + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to printf.o(i.SendUSART2Str) for SendUSART2Str + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to printf.o(i.DegugPrintf) for DegugPrintf + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) for NRF24L01_RX_Mode_NOACK + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to dataproc.o(.data) for newIdFlag + dataproc.o(i.DataProc_A0_WriteNum_SPI2) refers to dataproc.o(.bss) for uartSendWrNumOkData + dataproc.o(i.DataProc_A3_nrf) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + dataproc.o(i.DataProc_A3_nrf) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + dataproc.o(i.DataProc_A3_nrf) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + dataproc.o(i.DataProc_A3_nrf) refers to main.o(i.IWDG_Feed) for IWDG_Feed + dataproc.o(i.DataProc_A3_nrf) refers to nrf24l01.o(i.NRF24L01_RxPacket) for NRF24L01_RxPacket + dataproc.o(i.DataProc_A3_nrf) refers to printf.o(i.DegugPrintf) for DegugPrintf + dataproc.o(i.DataProc_A3_nrf) refers to printf.o(i.SendUSART2Str) for SendUSART2Str + dataproc.o(i.DataProc_A3_nrf) refers to dataproc.o(.data) for rspFlag_A3 + dataproc.o(i.DataProc_A4_nrf) refers to main.o(i.IWDG_Feed) for IWDG_Feed + dataproc.o(i.DataProc_A4_nrf) refers to nrf24l01.o(i.NRF24L01_RxPacket) for NRF24L01_RxPacket + dataproc.o(i.DataProc_A4_nrf) refers to dataproc.o(.data) for count_A34 + dataproc.o(i.DataProc_Nrf24l01) refers to main.o(i.IWDG_Feed) for IWDG_Feed + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(i.CheckSum) for CheckSum + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + dataproc.o(i.DataProc_Nrf24l01) refers to nrf24l01.o(i.NRF24L01_RxPacket) for NRF24L01_RxPacket + dataproc.o(i.DataProc_Nrf24l01) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(.data) for newIdFlag + dataproc.o(i.DataProc_Nrf24l01) refers to dataproc.o(.bss) for uartSendWrNumOkData + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to main.o(i.IWDG_Feed) for IWDG_Feed + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to dataproc.o(i.CheckSum) for CheckSum + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to nrf24l01.o(i.NRF24L01_Write_Reg) for NRF24L01_Write_Reg + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to nrf24l01.o(i.NRF24L01_Write_Buf) for NRF24L01_Write_Buf + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to nrf24l01.o(i.NRF24L01_RxPacket) for NRF24L01_RxPacket + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to printf.o(i.DegugPrintf) for DegugPrintf + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to printf.o(i.SendUSART2Str) for SendUSART2Str + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) for NRF24L01_RX_Mode_NOACK + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to dataproc.o(.data) for newIdFlag + dataproc.o(i.DataProc_Nrf24l01_SPI2) refers to dataproc.o(.bss) for uartSendWrNumOkData + dataproc.o(i.DataProc_RecNrf24L01) refers to nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) for NRF24L01_RX_Mode_NOACK + dataproc.o(i.DataProc_RecNrf24L01) refers to dataproc.o(i.DataProc_A4_nrf) for DataProc_A4_nrf + dataproc.o(i.DataProc_RecNrf24L01) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_RecNrf24L01) refers to delay.o(i.delay_ms) for delay_ms + dataproc.o(i.DataProc_RecNrf24L01) refers to printf.o(i.DegugPrintf) for DegugPrintf + dataproc.o(i.DataProc_RecNrf24L01) refers to printf.o(i.SendUSART2Str) for SendUSART2Str + dataproc.o(i.DataProc_RecNrf24L01) refers to dataproc.o(.data) for protocol_config_flg + dataproc.o(i.DataProc_RecNrf24L01) refers to dataproc.o(.bss) for uartSendRdNumData + dataproc.o(i.DataProc_USART1) refers to main.o(i.IWDG_Feed) for IWDG_Feed + dataproc.o(i.DataProc_USART1) refers to printf.o(i.DegugPrintf) for DegugPrintf + dataproc.o(i.DataProc_USART1) refers to printf.o(i.SendUSART2Str) for SendUSART2Str + dataproc.o(i.DataProc_USART1) refers to nrf24l01.o(i.NRF24L01_RX_Mode) for NRF24L01_RX_Mode + dataproc.o(i.DataProc_USART1) refers to dataproc.o(i.DataProc_A0_WriteNum_SPI2) for DataProc_A0_WriteNum_SPI2 + dataproc.o(i.DataProc_USART1) refers to printf.o(i.SendConsoleData) for SendConsoleData + dataproc.o(i.DataProc_USART1) refers to delay.o(i.delay_ms) for delay_ms + dataproc.o(i.DataProc_USART1) refers to printf.o(.data) for USART1_RX_CNT + dataproc.o(i.DataProc_USART1) refers to printf.o(.bss) for USART1_RX_BUF + dataproc.o(i.DataProc_USART1) refers to dataproc.o(.bss) for uartRecData + dataproc.o(i.DataProc_USART1) refers to dataproc.o(.data) for idBuf + dataproc.o(i.DataProc_USART1) refers to nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) for NRF24L01_RX_Mode_NOACK + dataproc.o(i.DataProc_USART1) refers to dataproc.o(i.DataProc_A4_nrf) for DataProc_A4_nrf + dataproc.o(i.DataProc_USART1) refers to flash.o(i.SavePara_to_flash) for SavePara_to_flash + dataproc.o(i.DataProc_USART1) refers to flash.o(.bss) for StoreBuffer + dataproc.o(i.Data_Init) refers to dataproc.o(.bss) for uartSendData + dataproc.o(i.TIM3_IRQHandler) refers to stm32f10x_tim.o(i.TIM_GetITStatus) for TIM_GetITStatus + dataproc.o(i.TIM3_IRQHandler) refers to stm32f10x_tim.o(i.TIM_ClearITPendingBit) for TIM_ClearITPendingBit + dataproc.o(i.TIM3_IRQHandler) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + dataproc.o(i.TIM3_IRQHandler) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + dataproc.o(i.TIM3_IRQHandler) refers to dataproc.o(.data) for count + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + usart2.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearFlag) for USART_ClearFlag + usart2.o(i.USART2_IRQHandler) refers to usart2.o(.bss) for USART2_RX_BUF + usart2.o(i.USART2_IRQHandler) refers to usart2.o(.data) for USART2_RX_CNT + usart2.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + usart2.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + usart2.o(i.USART2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + usart2.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + flash.o(i.Readpara_from_flash) refers to memseta.o(.text) for __aeabi_memclr4 + flash.o(i.Readpara_from_flash) refers to flash.o(i.Readstr_of_flash) for Readstr_of_flash + flash.o(i.Readpara_from_flash) refers to flash.o(.bss) for Save_Buffer + flash.o(i.Readstr_of_flash) refers to flash.o(i.GetPara) for GetPara + flash.o(i.SavePara) refers to stm32f10x_flash.o(i.FLASH_ProgramHalfWord) for FLASH_ProgramHalfWord + flash.o(i.SavePara_to_flash) refers to memseta.o(.text) for __aeabi_memclr4 + flash.o(i.SavePara_to_flash) refers to flash.o(i.Startwritedata) for Startwritedata + flash.o(i.SavePara_to_flash) refers to flash.o(i.Savestr_to_flash) for Savestr_to_flash + flash.o(i.SavePara_to_flash) refers to flash.o(i.Write_Complete) for Write_Complete + flash.o(i.SavePara_to_flash) refers to flash.o(.bss) for StoreBuffer + flash.o(i.Savestr_to_flash) refers to flash.o(i.SavePara) for SavePara + flash.o(i.Startwritedata) refers to stm32f10x_flash.o(i.FLASH_Unlock) for FLASH_Unlock + flash.o(i.Startwritedata) refers to stm32f10x_flash.o(i.FLASH_ErasePage) for FLASH_ErasePage + flash.o(i.Write_Complete) refers to stm32f10x_flash.o(i.FLASH_Lock) for FLASH_Lock + lcd.o(i.AttenuatorConfig) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + lcd.o(i.AttenuatorConfig) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + lcd.o(i.Display_Icon) refers to lcd.o(i.SetLcdRow) for SetLcdRow + lcd.o(i.Display_Icon) refers to lcd.o(i._vDispAddr) for _vDispAddr + lcd.o(i.Display_Icon) refers to lcd.o(.data) for ucDispDT + lcd.o(i.Display_Icon16) refers to lcd.o(i.SetLcdRow) for SetLcdRow + lcd.o(i.Display_Icon16) refers to lcd.o(i._vDispAddr) for _vDispAddr + lcd.o(i.Display_Icon16) refers to lcd.o(.data) for ucDispDT + lcd.o(i.Get_8x16_Font) refers to memcpya.o(.text) for __aeabi_memcpy + lcd.o(i.Get_8x16_Font) refers to lcd.o(.constdata) for font816 + lcd.o(i._vDispAddr) refers to lcd.o(.data) for WriteIR + lcd.o(i._vWriteData_spi) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + lcd.o(i._vWriteData_spi) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + lcd.o(i._vWriteData_spi) refers to lcd.o(.data) for ucDispDT + lcd.o(i._vWriteIR_spi) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + lcd.o(i._vWriteIR_spi) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + lcd.o(i.lcd_init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + lcd.o(i.lcd_init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + lcd.o(i.lcd_init) refers to lcd.o(i.vDispInit) for vDispInit + lcd.o(i.lcd_init) refers to lcd.o(i.vDispClear) for vDispClear + lcd.o(i.vDispClear) refers to lcd.o(i._vDispAddr) for _vDispAddr + lcd.o(i.vDispClear) refers to lcd.o(.data) for ucDispDT + lcd.o(i.vDispClearLine) refers to lcd.o(i.SetLcdRow) for SetLcdRow + lcd.o(i.vDispClearLine) refers to lcd.o(i._vDispAddr) for _vDispAddr + lcd.o(i.vDispClearLine) refers to lcd.o(.data) for ucDispDT + lcd.o(i.vDispFull) refers to lcd.o(i._vDispAddr) for _vDispAddr + lcd.o(i.vDispFull) refers to lcd.o(.data) for ucDispDT + lcd.o(i.vDispInit) refers to lcd.o(i.vDispInit_spi) for vDispInit_spi + lcd.o(i.vDispInit) refers to lcd.o(i._vWriteIR_spi) for _vWriteIR_spi + lcd.o(i.vDispInit) refers to lcd.o(.data) for WriteIR + lcd.o(i.vDispInit) refers to lcd.o(i._vWriteData_spi) for _vWriteData_spi + lcd.o(i.vDispInit_spi) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + lcd.o(i.vDispInit_spi) refers to delay.o(i.delay_5us) for delay_5us + lcd.o(i.vDispInit_spi) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + lcd.o(i.vDispInit_spi) refers to delay.o(i.delay_ms) for delay_ms + lcd.o(i.vDispInit_spi) refers to lcd.o(.data) for WriteIR + lcd.o(i.vDispOn) refers to lcd.o(.data) for WriteIR + lcd.o(i.vDispStr) refers to lcd.o(i.Get_8x16_Font) for Get_8x16_Font + lcd.o(i.vDispStr) refers to lcd.o(i.Display_Icon) for Display_Icon + stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable + stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_usart.o(i.USART_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(i.I2S_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_tim.o(i.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(i.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI3_Config) for TI3_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI4_Config) for TI4_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler + stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + stm32f10x_flash.o(i.FLASH_EnableWriteProtection) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_EraseAllBank1Pages) refers to stm32f10x_flash.o(i.FLASH_WaitForLastBank1Operation) for FLASH_WaitForLastBank1Operation + stm32f10x_flash.o(i.FLASH_EraseAllPages) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(i.FLASH_GetReadOutProtectionStatus) for FLASH_GetReadOutProtectionStatus + stm32f10x_flash.o(i.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ErasePage) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ProgramHalfWord) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ProgramOptionByteData) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ProgramWord) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ReadOutProtection) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_UserOptionByteConfig) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_WaitForLastBank1Operation) refers to stm32f10x_flash.o(i.FLASH_GetBank1Status) for FLASH_GetBank1Status + stm32f10x_flash.o(i.FLASH_WaitForLastOperation) refers to stm32f10x_flash.o(i.FLASH_GetBank1Status) for FLASH_GetBank1Status + system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo24) for SetSysClockTo24 + system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock + system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(.text) for Reset_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.NMI_Handler) for NMI_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.HardFault_Handler) for HardFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.MemManage_Handler) for MemManage_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.BusFault_Handler) for BusFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.UsageFault_Handler) for UsageFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SVC_Handler) for SVC_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.DebugMon_Handler) for DebugMon_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.PendSV_Handler) for PendSV_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SysTick_Handler) for SysTick_Handler + startup_stm32f10x_hd.o(RESET) refers to dataproc.o(i.TIM3_IRQHandler) for TIM3_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to printf.o(i.USART1_IRQHandler) for USART1_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to usart2.o(i.USART2_IRQHandler) for USART2_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to printf.o(i.USART3_IRQHandler) for USART3_IRQHandler + startup_stm32f10x_hd.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + startup_stm32f10x_hd.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + printfb.o(i.__0fprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0fprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0printf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._sputc) for _sputc + printfb.o(i.__0vfprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vfprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vprintf$bare) refers to printf.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._sputc) for _sputc + printf0.o(i.__0fprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0fprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0printf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0snprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0snprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0sprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0sprintf$0) refers to printf0.o(i._sputc) for _sputc + printf0.o(i.__0vfprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vfprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vprintf$0) refers to printf.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._sputc) for _sputc + printf1.o(i.__0fprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0fprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0printf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0snprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0snprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0sprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0sprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i.__0vfprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vfprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vprintf$1) refers to printf.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf2.o(i.__0fprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0fprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0printf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0snprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0snprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0sprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0sprintf$2) refers to printf2.o(i._sputc) for _sputc + printf2.o(i.__0vfprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vfprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vprintf$2) refers to printf.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._sputc) for _sputc + printf3.o(i.__0fprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0fprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0printf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0snprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0snprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0sprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0sprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i.__0vfprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vfprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vprintf$3) refers to printf.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf4.o(i.__0fprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0fprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0printf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0snprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0snprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0sprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0sprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i.__0vfprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vfprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vprintf$4) refers to printf.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf5.o(i.__0fprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0fprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0printf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0snprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0snprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0sprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0sprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i.__0vfprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vfprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vprintf$5) refers to printf.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf6.o(i.__0fprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0fprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0printf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0snprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0snprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0sprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0sprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i.__0vfprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vfprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vprintf$6) refers to printf.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i._printf_core) refers to printf6.o(i._printf_pre_padding) for _printf_pre_padding + printf6.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf6.o(i._printf_core) refers to printf6.o(i._printf_post_padding) for _printf_post_padding + printf7.o(i.__0fprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0fprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0printf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0snprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0snprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0sprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0sprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i.__0vfprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vfprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vprintf$7) refers to printf.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i._printf_core) refers to printf7.o(i._printf_pre_padding) for _printf_pre_padding + printf7.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf7.o(i._printf_core) refers to printf7.o(i._printf_post_padding) for _printf_post_padding + printf8.o(i.__0fprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0fprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0printf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0snprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0snprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0sprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0sprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i.__0vfprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vfprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vprintf$8) refers to printf.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i._printf_core) refers to printf8.o(i._printf_pre_padding) for _printf_pre_padding + printf8.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf8.o(i._printf_core) refers to printf8.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i.__0fprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0fprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0fprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0printf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0printf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0printf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0printf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0snprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0snprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0snprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0sprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0sprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0sprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i.__0vfprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vfprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vfprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vprintf) refers to printf.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0vsnprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsnprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsnprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0vsprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i._fp_digits) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._fp_digits) refers to dmul.o(.text) for __aeabi_dmul + printfa.o(i._fp_digits) refers to ddiv.o(.text) for __aeabi_ddiv + printfa.o(i._fp_digits) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + printfa.o(i._fp_digits) refers to dadd.o(.text) for __aeabi_dadd + printfa.o(i._fp_digits) refers to dfixul.o(.text) for __aeabi_d2ulz + printfa.o(i._fp_digits) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_core) refers to printfa.o(i._printf_pre_padding) for _printf_pre_padding + printfa.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers to printfa.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i._printf_core) refers to printfa.o(i._fp_digits) for _fp_digits + printfa.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printfa.o(i._printf_post_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_pre_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._snputc) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._sputc) refers (Special) to iusefp.o(.text) for __I$use$fp + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llsshr.o(.text) for __aeabi_lasr + dadd.o(.text) refers to depilogue.o(.text) for _double_epilogue + dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue + ddiv.o(.text) refers to depilogue.o(.text) for _double_round + dfixul.o(.text) refers to llushr.o(.text) for __aeabi_llsr + dfixul.o(.text) refers to llshl.o(.text) for __aeabi_llsl + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr + + +============================================================================== + +Removing Unused input sections from the image. + + Removing printf.o(i.SendConsoleByte), (20 bytes). + Removing printf.o(i.SendConsoleStr), (20 bytes). + Removing printf.o(i.SendUartRStr), (60 bytes). + Removing printf.o(i.Usart1_SendData), (44 bytes). + Removing delay.o(i.delay_5us), (28 bytes). + Removing main.o(i.NRF24L01_RX_TelPo_CONFIG1), (92 bytes). + Removing main.o(i.NRF24L01_RxPacket1), (82 bytes). + Removing main.o(i.NRF24L01_TELPO_RX_Mode), (162 bytes). + Removing nrf24l01.o(i.NRF24L01_Config), (48 bytes). + Removing nrf24l01.o(i.NRF24L01_RX_Mode_NOACK_VCOM), (188 bytes). + Removing nrf24l01.o(i.NRF24L01_TX_Mode), (148 bytes). + Removing nrf24l01.o(i.NRF24L01_TxPacket), (148 bytes). + Removing nrf24l01.o(i.RF24_CarrierTest), (184 bytes). + Removing dataproc.o(i.DataProc_A3_nrf), (264 bytes). + Removing dataproc.o(i.DataProc_Nrf24l01), (612 bytes). + Removing dataproc.o(i.DataProc_Nrf24l01_SPI2), (544 bytes). + Removing dataproc.o(i.DataProc_RecNrf24L01), (148 bytes). + Removing lcd.o(i.AttenuatorConfig), (148 bytes). + Removing lcd.o(i.Display_Icon), (176 bytes). + Removing lcd.o(i.Display_Icon16), (168 bytes). + Removing lcd.o(i.Get_8x16_Font), (72 bytes). + Removing lcd.o(i.HexToDec), (604 bytes). + Removing lcd.o(i.SetLcdRow), (22 bytes). + Removing lcd.o(i._vDispAddr), (48 bytes). + Removing lcd.o(i._vWriteData_spi), (136 bytes). + Removing lcd.o(i._vWriteIR_spi), (124 bytes). + Removing lcd.o(i.lcd_init), (132 bytes). + Removing lcd.o(i.vDispClear), (76 bytes). + Removing lcd.o(i.vDispClearLine), (132 bytes). + Removing lcd.o(i.vDispFull), (76 bytes). + Removing lcd.o(i.vDispInit), (44 bytes). + Removing lcd.o(i.vDispInit_spi), (228 bytes). + Removing lcd.o(i.vDispOn), (16 bytes). + Removing lcd.o(i.vDispStr), (64 bytes). + Removing lcd.o(i.vI2cHzkGetStart), (16 bytes). + Removing lcd.o(.constdata), (608 bytes). + Removing lcd.o(.data), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_DeInit), (80 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetFlagStatus), (60 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_HCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSEConfig), (76 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ITConfig), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSEConfig), (52 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_MCOConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_PCLK1Config), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_PCLK2Config), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_PLLCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_PLLConfig), (28 bytes). + Removing stm32f10x_rcc.o(i.RCC_PREDIV1Config), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKConfig), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_SYSCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp), (56 bytes). + Removing stm32f10x_usart.o(i.USART_ClockInit), (34 bytes). + Removing stm32f10x_usart.o(i.USART_ClockStructInit), (12 bytes). + Removing stm32f10x_usart.o(i.USART_DMACmd), (18 bytes). + Removing stm32f10x_usart.o(i.USART_DeInit), (156 bytes). + Removing stm32f10x_usart.o(i.USART_HalfDuplexCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_IrDACmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_IrDAConfig), (18 bytes). + Removing stm32f10x_usart.o(i.USART_LINBreakDetectLengthConfig), (18 bytes). + Removing stm32f10x_usart.o(i.USART_LINCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_OneBitMethodCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_OverSampling8Cmd), (22 bytes). + Removing stm32f10x_usart.o(i.USART_ReceiverWakeUpCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_SendBreak), (10 bytes). + Removing stm32f10x_usart.o(i.USART_SetAddress), (18 bytes). + Removing stm32f10x_usart.o(i.USART_SetGuardTime), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SetPrescaler), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardNACKCmd), (24 bytes). + Removing stm32f10x_usart.o(i.USART_StructInit), (24 bytes). + Removing stm32f10x_usart.o(i.USART_WakeUpConfig), (18 bytes). + Removing misc.o(i.NVIC_SetVectorTable), (20 bytes). + Removing misc.o(i.NVIC_SystemLPConfig), (32 bytes). + Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (20 bytes). + Removing stm32f10x_gpio.o(i.GPIO_DeInit), (200 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (64 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (32 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinRemapConfig), (144 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes). + Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes). + Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes). + Removing stm32f10x_spi.o(i.I2S_Cmd), (24 bytes). + Removing stm32f10x_spi.o(i.I2S_Init), (232 bytes). + Removing stm32f10x_spi.o(i.I2S_StructInit), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_BiDirectionalLineConfig), (28 bytes). + Removing stm32f10x_spi.o(i.SPI_CalculateCRC), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_DataSizeConfig), (18 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRC), (16 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRCPolynomial), (6 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearFlag), (6 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearITPendingBit), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_DMACmd), (18 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_DeInit), (88 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_GetITStatus), (52 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ITConfig), (32 bytes). + Removing stm32f10x_spi.o(i.SPI_NSSInternalSoftwareConfig), (30 bytes). + Removing stm32f10x_spi.o(i.SPI_SSOutputCmd), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_StructInit), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_TransmitCRC), (10 bytes). + Removing stm32f10x_tim.o(i.TI1_Config), (128 bytes). + Removing stm32f10x_tim.o(i.TI2_Config), (152 bytes). + Removing stm32f10x_tim.o(i.TI3_Config), (144 bytes). + Removing stm32f10x_tim.o(i.TI4_Config), (152 bytes). + Removing stm32f10x_tim.o(i.TIM_ARRPreloadConfig), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_BDTRConfig), (32 bytes). + Removing stm32f10x_tim.o(i.TIM_BDTRStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_CCPreloadControl), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_CCxCmd), (30 bytes). + Removing stm32f10x_tim.o(i.TIM_CCxNCmd), (30 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearFlag), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC1Ref), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC2Ref), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC3Ref), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC4Ref), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_CounterModeConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_CtrlPWMOutputs), (30 bytes). + Removing stm32f10x_tim.o(i.TIM_DMACmd), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_DMAConfig), (10 bytes). + Removing stm32f10x_tim.o(i.TIM_DeInit), (488 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRClockMode1Config), (54 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRClockMode2Config), (32 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRConfig), (28 bytes). + Removing stm32f10x_tim.o(i.TIM_EncoderInterfaceConfig), (66 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC1Config), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC2Config), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC3Config), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC4Config), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_GenerateEvent), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture1), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture2), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture3), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture4), (8 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCounter), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetFlagStatus), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_GetPrescaler), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_ICInit), (172 bytes). + Removing stm32f10x_tim.o(i.TIM_ICStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_InternalClockConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1FastConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1Init), (152 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1NPolarityConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1PolarityConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1PreloadConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2FastConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2Init), (164 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2NPolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2PolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2PreloadConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3FastConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3Init), (160 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3NPolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3PolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3PreloadConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4FastConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4Init), (124 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4PolarityConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4PreloadConfig), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_OCStructInit), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_PWMIConfig), (124 bytes). + Removing stm32f10x_tim.o(i.TIM_PrescalerConfig), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectCCDMA), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectCOM), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectHallSensor), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectInputTrigger), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectMasterSlaveMode), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOCxM), (82 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOnePulseMode), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOutputTrigger), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectSlaveMode), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetAutoreload), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetClockDivision), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare1), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare2), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare3), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare4), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCounter), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC1Prescaler), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC2Prescaler), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC3Prescaler), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC4Prescaler), (26 bytes). + Removing stm32f10x_tim.o(i.TIM_TIxExternalClockConfig), (62 bytes). + Removing stm32f10x_tim.o(i.TIM_TimeBaseStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_UpdateDisableConfig), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_UpdateRequestConfig), (24 bytes). + Removing stm32f10x_iwdg.o(i.IWDG_GetFlagStatus), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_ClearFlag), (12 bytes). + Removing stm32f10x_flash.o(i.FLASH_EnableWriteProtection), (196 bytes). + Removing stm32f10x_flash.o(i.FLASH_EraseAllBank1Pages), (72 bytes). + Removing stm32f10x_flash.o(i.FLASH_EraseAllPages), (72 bytes). + Removing stm32f10x_flash.o(i.FLASH_EraseOptionBytes), (168 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetFlagStatus), (48 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetPrefetchBufferStatus), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetReadOutProtectionStatus), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetStatus), (52 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetUserOptionByte), (12 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetWriteProtectionOptionByte), (12 bytes). + Removing stm32f10x_flash.o(i.FLASH_HalfCycleAccessCmd), (28 bytes). + Removing stm32f10x_flash.o(i.FLASH_ITConfig), (32 bytes). + Removing stm32f10x_flash.o(i.FLASH_LockBank1), (20 bytes). + Removing stm32f10x_flash.o(i.FLASH_PrefetchBufferCmd), (28 bytes). + Removing stm32f10x_flash.o(i.FLASH_ProgramOptionByteData), (84 bytes). + Removing stm32f10x_flash.o(i.FLASH_ProgramWord), (108 bytes). + Removing stm32f10x_flash.o(i.FLASH_ReadOutProtection), (172 bytes). + Removing stm32f10x_flash.o(i.FLASH_SetLatency), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_UnlockBank1), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_UserOptionByteConfig), (104 bytes). + Removing stm32f10x_flash.o(i.FLASH_WaitForLastBank1Operation), (38 bytes). + Removing core_cm3.o(.emb_text), (32 bytes). + Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (160 bytes). + Removing system_stm32f10x.o(.data), (20 bytes). + Removing startup_stm32f10x_hd.o(HEAP), (512 bytes). + Removing dadd.o(.text), (334 bytes). + Removing dmul.o(.text), (228 bytes). + Removing ddiv.o(.text), (222 bytes). + Removing dfixul.o(.text), (48 bytes). + Removing cdrcmple.o(.text), (48 bytes). + Removing depilogue.o(.text), (186 bytes). + +241 unused section(s) (total 15096 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf2.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf1.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf3.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfb.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf0.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfa.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf8.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf7.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf6.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf5.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf4.o ABSOLUTE + ../clib/microlib/stdio/streams.c 0x00000000 Number 0 stdout.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpyb.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpya.o ABSOLUTE + ../clib/microlib/string/memset.c 0x00000000 Number 0 memseta.o ABSOLUTE + ../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 dadd.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 depilogue.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixul.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE + ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s 0x00000000 Number 0 startup_stm32f10x_hd.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c 0x00000000 Number 0 misc.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c 0x00000000 Number 0 stm32f10x_flash.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c 0x00000000 Number 0 stm32f10x_iwdg.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c 0x00000000 Number 0 stm32f10x_spi.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c 0x00000000 Number 0 stm32f10x_tim.o ABSOLUTE + ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c 0x00000000 Number 0 stm32f10x_usart.o ABSOLUTE + ..\Libraries\stm32f10x_it.c 0x00000000 Number 0 stm32f10x_it.o ABSOLUTE + ..\Libraries\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + ..\\Libraries\\CMSIS\\CM3\\CoreSupport\\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + ..\bsp\DataProc.c 0x00000000 Number 0 dataproc.o ABSOLUTE + ..\bsp\LCD.c 0x00000000 Number 0 lcd.o ABSOLUTE + ..\bsp\LED.c 0x00000000 Number 0 led.o ABSOLUTE + ..\bsp\USART2.c 0x00000000 Number 0 usart2.o ABSOLUTE + ..\bsp\delay.c 0x00000000 Number 0 delay.o ABSOLUTE + ..\bsp\flash.c 0x00000000 Number 0 flash.o ABSOLUTE + ..\bsp\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\bsp\nrf24L01.c 0x00000000 Number 0 nrf24l01.o ABSOLUTE + ..\bsp\printf.c 0x00000000 Number 0 printf.o ABSOLUTE + ..\bsp\spi.c 0x00000000 Number 0 spi.o ABSOLUTE + ..\bsp\tim.c 0x00000000 Number 0 tim.o ABSOLUTE + cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + RESET 0x08000000 Section 304 startup_stm32f10x_hd.o(RESET) + .ARM.Collect$$$$00000000 0x08000130 Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x08000130 Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x08000134 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x08000138 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x08000138 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000B 0x08000138 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) + .ARM.Collect$$$$0000000D 0x08000140 Section 0 entry10a.o(.ARM.Collect$$$$0000000D) + .ARM.Collect$$$$0000000F 0x08000140 Section 0 entry11a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00002712 0x08000140 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x08000140 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x08000144 Section 36 startup_stm32f10x_hd.o(.text) + .text 0x08000168 Section 0 memseta.o(.text) + .text 0x0800018c Section 36 init.o(.text) + i.BusFault_Handler 0x080001b0 Section 0 stm32f10x_it.o(i.BusFault_Handler) + i.CheckSum 0x080001b4 Section 0 dataproc.o(i.CheckSum) + i.DataProc_1356 0x080001d8 Section 0 dataproc.o(i.DataProc_1356) + i.DataProc_A0_WriteNum_SPI2 0x080002f8 Section 0 dataproc.o(i.DataProc_A0_WriteNum_SPI2) + i.DataProc_A4_nrf 0x0800053c Section 0 dataproc.o(i.DataProc_A4_nrf) + i.DataProc_USART1 0x080006ac Section 0 dataproc.o(i.DataProc_USART1) + i.Data_Init 0x08000cd0 Section 0 dataproc.o(i.Data_Init) + i.DebugMon_Handler 0x08000e10 Section 0 stm32f10x_it.o(i.DebugMon_Handler) + i.DegugPrintf 0x08000e12 Section 0 printf.o(i.DegugPrintf) + i.FLASH_ErasePage 0x08000e48 Section 0 stm32f10x_flash.o(i.FLASH_ErasePage) + i.FLASH_GetBank1Status 0x08000e94 Section 0 stm32f10x_flash.o(i.FLASH_GetBank1Status) + i.FLASH_Lock 0x08000ec8 Section 0 stm32f10x_flash.o(i.FLASH_Lock) + i.FLASH_ProgramHalfWord 0x08000edc Section 0 stm32f10x_flash.o(i.FLASH_ProgramHalfWord) + i.FLASH_Unlock 0x08000f1c Section 0 stm32f10x_flash.o(i.FLASH_Unlock) + i.FLASH_WaitForLastOperation 0x08000f34 Section 0 stm32f10x_flash.o(i.FLASH_WaitForLastOperation) + i.GPIO_Init 0x08000f5a Section 0 stm32f10x_gpio.o(i.GPIO_Init) + i.GPIO_ResetBits 0x08001070 Section 0 stm32f10x_gpio.o(i.GPIO_ResetBits) + i.GPIO_SetBits 0x08001074 Section 0 stm32f10x_gpio.o(i.GPIO_SetBits) + i.GetPara 0x08001078 Section 0 flash.o(i.GetPara) + i.HardFault_Handler 0x08001080 Section 0 stm32f10x_it.o(i.HardFault_Handler) + i.HexToAscii 0x08001084 Section 0 printf.o(i.HexToAscii) + i.IWDG_Enable 0x080010a4 Section 0 stm32f10x_iwdg.o(i.IWDG_Enable) + i.IWDG_Feed 0x080010b4 Section 0 main.o(i.IWDG_Feed) + i.IWDG_Init 0x080010bc Section 0 main.o(i.IWDG_Init) + i.IWDG_ReloadCounter 0x080010e0 Section 0 stm32f10x_iwdg.o(i.IWDG_ReloadCounter) + i.IWDG_SetPrescaler 0x080010f0 Section 0 stm32f10x_iwdg.o(i.IWDG_SetPrescaler) + i.IWDG_SetReload 0x080010fc Section 0 stm32f10x_iwdg.o(i.IWDG_SetReload) + i.IWDG_WriteAccessCmd 0x08001108 Section 0 stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd) + i.MemManage_Handler 0x08001114 Section 0 stm32f10x_it.o(i.MemManage_Handler) + i.NMI_Handler 0x08001118 Section 0 stm32f10x_it.o(i.NMI_Handler) + i.NRF24L01_Check 0x0800111c Section 0 nrf24l01.o(i.NRF24L01_Check) + i.NRF24L01_Init 0x08001174 Section 0 nrf24l01.o(i.NRF24L01_Init) + i.NRF24L01_RX_AHDX_CONFIG 0x08001270 Section 0 nrf24l01.o(i.NRF24L01_RX_AHDX_CONFIG) + i.NRF24L01_RX_AnHui_CONFIG 0x08001300 Section 0 nrf24l01.o(i.NRF24L01_RX_AnHui_CONFIG) + i.NRF24L01_RX_CQYD_CONFIG 0x08001390 Section 0 nrf24l01.o(i.NRF24L01_RX_CQYD_CONFIG) + i.NRF24L01_RX_DH_CONFIG 0x08001420 Section 0 nrf24l01.o(i.NRF24L01_RX_DH_CONFIG) + i.NRF24L01_RX_FJZZ_CONFIG 0x080014b0 Section 0 nrf24l01.o(i.NRF24L01_RX_FJZZ_CONFIG) + i.NRF24L01_RX_GSYD_CONFIG 0x08001540 Section 0 nrf24l01.o(i.NRF24L01_RX_GSYD_CONFIG) + i.NRF24L01_RX_GXYD_CONFIG 0x080015d0 Section 0 nrf24l01.o(i.NRF24L01_RX_GXYD_CONFIG) + i.NRF24L01_RX_GuiZhou_CONFIG 0x08001660 Section 0 nrf24l01.o(i.NRF24L01_RX_GuiZhou_CONFIG) + i.NRF24L01_RX_JiangXi_CONFIG 0x080016f0 Section 0 nrf24l01.o(i.NRF24L01_RX_JiangXi_CONFIG) + i.NRF24L01_RX_LIAO_NING_CONFIG 0x08001780 Section 0 nrf24l01.o(i.NRF24L01_RX_LIAO_NING_CONFIG) + i.NRF24L01_RX_Mode 0x08001810 Section 0 nrf24l01.o(i.NRF24L01_RX_Mode) + i.NRF24L01_RX_Mode_NOACK 0x080018c4 Section 0 nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) + i.NRF24L01_RX_NEW_LIAO_NING_CONFIG 0x080019d0 Section 0 nrf24l01.o(i.NRF24L01_RX_NEW_LIAO_NING_CONFIG) + i.NRF24L01_RX_NMGYD_CONFIG 0x08001a60 Section 0 nrf24l01.o(i.NRF24L01_RX_NMGYD_CONFIG) + i.NRF24L01_RX_NeiMengGu_CONFIG 0x08001af0 Section 0 nrf24l01.o(i.NRF24L01_RX_NeiMengGu_CONFIG) + i.NRF24L01_RX_SXYD_CONFIG 0x08001b80 Section 0 nrf24l01.o(i.NRF24L01_RX_SXYD_CONFIG) + i.NRF24L01_RX_SZML_CONFIG 0x08001c10 Section 0 nrf24l01.o(i.NRF24L01_RX_SZML_CONFIG) + i.NRF24L01_RX_ShanXiXinNuo_CONFIG 0x08001ca0 Section 0 nrf24l01.o(i.NRF24L01_RX_ShanXiXinNuo_CONFIG) + i.NRF24L01_RX_SiChuan_CONFIG 0x08001d30 Section 0 nrf24l01.o(i.NRF24L01_RX_SiChuan_CONFIG) + i.NRF24L01_RX_TP_CONFIG 0x08001dc0 Section 0 nrf24l01.o(i.NRF24L01_RX_TP_CONFIG) + i.NRF24L01_RX_TelPo_CONFIG 0x08001e50 Section 0 nrf24l01.o(i.NRF24L01_RX_TelPo_CONFIG) + i.NRF24L01_RX_VCM_CONFIG 0x08001ee0 Section 0 nrf24l01.o(i.NRF24L01_RX_VCM_CONFIG) + i.NRF24L01_RX_XDF_CONFIG 0x08001f70 Section 0 nrf24l01.o(i.NRF24L01_RX_XDF_CONFIG) + i.NRF24L01_RX_YunNan_CONFIG 0x08002000 Section 0 nrf24l01.o(i.NRF24L01_RX_YunNan_CONFIG) + i.NRF24L01_Read_Buf 0x08002090 Section 0 nrf24l01.o(i.NRF24L01_Read_Buf) + i.NRF24L01_Read_Reg 0x0800210c Section 0 nrf24l01.o(i.NRF24L01_Read_Reg) + i.NRF24L01_RxPacket 0x0800216c Section 0 nrf24l01.o(i.NRF24L01_RxPacket) + i.NRF24L01_Write_Buf 0x080021b0 Section 0 nrf24l01.o(i.NRF24L01_Write_Buf) + i.NRF24L01_Write_Reg 0x0800222c Section 0 nrf24l01.o(i.NRF24L01_Write_Reg) + i.NVIC_Configuration 0x08002290 Section 0 main.o(i.NVIC_Configuration) + i.NVIC_Init 0x0800230c Section 0 misc.o(i.NVIC_Init) + i.NVIC_PriorityGroupConfig 0x0800237c Section 0 misc.o(i.NVIC_PriorityGroupConfig) + i.PendSV_Handler 0x08002390 Section 0 stm32f10x_it.o(i.PendSV_Handler) + i.RCC_APB1PeriphClockCmd 0x08002394 Section 0 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + i.RCC_APB2PeriphClockCmd 0x080023b4 Section 0 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + i.RCC_Configuration 0x080023d4 Section 0 main.o(i.RCC_Configuration) + i.RCC_GetClocksFreq 0x08002444 Section 0 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + i.Readpara_from_flash 0x08002518 Section 0 flash.o(i.Readpara_from_flash) + i.Readstr_of_flash 0x08002554 Section 0 flash.o(i.Readstr_of_flash) + i.SPI1_Init 0x08002578 Section 0 spi.o(i.SPI1_Init) + i.SPI2_Init 0x080025fc Section 0 spi.o(i.SPI2_Init) + i.SPI_Cmd 0x08002688 Section 0 stm32f10x_spi.o(i.SPI_Cmd) + i.SPI_I2S_GetFlagStatus 0x080026a0 Section 0 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + i.SPI_I2S_ReceiveData 0x080026b2 Section 0 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + i.SPI_I2S_SendData 0x080026b8 Section 0 stm32f10x_spi.o(i.SPI_I2S_SendData) + i.SPI_Init 0x080026bc Section 0 stm32f10x_spi.o(i.SPI_Init) + i.SPI_ReadWriteByte 0x080026f8 Section 0 spi.o(i.SPI_ReadWriteByte) + i.SPI_SetSpeed 0x080027a0 Section 0 spi.o(i.SPI_SetSpeed) + i.SVC_Handler 0x080027f0 Section 0 stm32f10x_it.o(i.SVC_Handler) + i.SavePara 0x080027f2 Section 0 flash.o(i.SavePara) + i.SavePara_to_flash 0x08002804 Section 0 flash.o(i.SavePara_to_flash) + i.Savestr_to_flash 0x0800284c Section 0 flash.o(i.Savestr_to_flash) + i.SendConsoleData 0x08002874 Section 0 printf.o(i.SendConsoleData) + i.SendUSART2Byte 0x0800288c Section 0 printf.o(i.SendUSART2Byte) + i.SendUSART2Str 0x080028a0 Section 0 printf.o(i.SendUSART2Str) + i.SendUartByte 0x080028b4 Section 0 printf.o(i.SendUartByte) + i.SendUartData 0x080028d4 Section 0 printf.o(i.SendUartData) + i.SendUartStr 0x08002906 Section 0 printf.o(i.SendUartStr) + i.SetSysClock 0x08002942 Section 0 system_stm32f10x.o(i.SetSysClock) + SetSysClock 0x08002943 Thumb Code 8 system_stm32f10x.o(i.SetSysClock) + i.SetSysClockTo24 0x0800294c Section 0 system_stm32f10x.o(i.SetSysClockTo24) + SetSysClockTo24 0x0800294d Thumb Code 178 system_stm32f10x.o(i.SetSysClockTo24) + i.Startwritedata 0x08002a04 Section 0 flash.o(i.Startwritedata) + i.SysTick_CLKSourceConfig 0x08002a14 Section 0 misc.o(i.SysTick_CLKSourceConfig) + i.SysTick_Handler 0x08002a3c Section 0 stm32f10x_it.o(i.SysTick_Handler) + i.SystemInit 0x08002a40 Section 0 system_stm32f10x.o(i.SystemInit) + i.TIM3_IRQHandler 0x08002aa4 Section 0 dataproc.o(i.TIM3_IRQHandler) + i.TIM3_Int_Init 0x08002b4c Section 0 tim.o(i.TIM3_Int_Init) + i.TIM_ClearITPendingBit 0x08002b8c Section 0 stm32f10x_tim.o(i.TIM_ClearITPendingBit) + i.TIM_Cmd 0x08002b92 Section 0 stm32f10x_tim.o(i.TIM_Cmd) + i.TIM_GetITStatus 0x08002baa Section 0 stm32f10x_tim.o(i.TIM_GetITStatus) + i.TIM_ITConfig 0x08002bcc Section 0 stm32f10x_tim.o(i.TIM_ITConfig) + i.TIM_TimeBaseInit 0x08002be0 Section 0 stm32f10x_tim.o(i.TIM_TimeBaseInit) + i.USART1_IRQHandler 0x08002c84 Section 0 printf.o(i.USART1_IRQHandler) + i.USART2_IRQHandler 0x08002ce0 Section 0 usart2.o(i.USART2_IRQHandler) + i.USART2_Init 0x08002d3c Section 0 usart2.o(i.USART2_Init) + i.USART3_IRQHandler 0x08002dc4 Section 0 printf.o(i.USART3_IRQHandler) + i.USART_ClearFlag 0x08002e28 Section 0 stm32f10x_usart.o(i.USART_ClearFlag) + i.USART_ClearITPendingBit 0x08002e3a Section 0 stm32f10x_usart.o(i.USART_ClearITPendingBit) + i.USART_Cmd 0x08002e58 Section 0 stm32f10x_usart.o(i.USART_Cmd) + i.USART_Configuration 0x08002e70 Section 0 printf.o(i.USART_Configuration) + i.USART_GetFlagStatus 0x08002f8c Section 0 stm32f10x_usart.o(i.USART_GetFlagStatus) + i.USART_GetITStatus 0x08002fa6 Section 0 stm32f10x_usart.o(i.USART_GetITStatus) + i.USART_ITConfig 0x08002ffa Section 0 stm32f10x_usart.o(i.USART_ITConfig) + i.USART_Init 0x08003044 Section 0 stm32f10x_usart.o(i.USART_Init) + i.USART_ReceiveData 0x0800311c Section 0 stm32f10x_usart.o(i.USART_ReceiveData) + i.USART_SendData 0x08003126 Section 0 stm32f10x_usart.o(i.USART_SendData) + i.UsageFault_Handler 0x0800312e Section 0 stm32f10x_it.o(i.UsageFault_Handler) + i.Write_Complete 0x08003132 Section 0 flash.o(i.Write_Complete) + i.__0printf$bare 0x0800313c Section 0 printfb.o(i.__0printf$bare) + i.__scatterload_copy 0x0800314c Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x0800315a Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x0800315c Section 14 handlers.o(i.__scatterload_zeroinit) + i._printf_core 0x0800316a Section 0 printfb.o(i._printf_core) + _printf_core 0x0800316b Thumb Code 34 printfb.o(i._printf_core) + i.delay_ms 0x0800318c Section 0 delay.o(i.delay_ms) + i.fputc 0x080031b8 Section 0 printf.o(i.fputc) + i.led_init 0x080031dc Section 0 led.o(i.led_init) + i.main 0x08003234 Section 0 main.o(i.main) + .constdata 0x08003568 Section 135 nrf24l01.o(.constdata) + .data 0x20000000 Section 12 printf.o(.data) + .data 0x2000000c Section 128 dataproc.o(.data) + ResNum_1356 0x2000001b Data 5 dataproc.o(.data) + oldResNum_1356 0x20000020 Data 5 dataproc.o(.data) + .data 0x2000008c Section 4 usart2.o(.data) + .data 0x20000090 Section 20 stm32f10x_rcc.o(.data) + APBAHBPrescTable 0x20000090 Data 16 stm32f10x_rcc.o(.data) + ADCPrescTable 0x200000a0 Data 4 stm32f10x_rcc.o(.data) + .data 0x200000a4 Section 4 stdout.o(.data) + .bss 0x200000a8 Section 500 printf.o(.bss) + .bss 0x2000029c Section 600 dataproc.o(.bss) + .bss 0x200004f4 Section 64 usart2.o(.bss) + .bss 0x20000534 Section 40 flash.o(.bss) + STACK 0x20000560 Section 1024 startup_stm32f10x_hd.o(STACK) + .ARM.__AT_0x20001000 0x20001000 Section 20480 printf.o(.ARM.__AT_0x20001000) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __decompress - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_Size 0x00000130 Number 0 startup_stm32f10x_hd.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f10x_hd.o(RESET) + __Vectors_End 0x08000130 Data 0 startup_stm32f10x_hd.o(RESET) + __main 0x08000131 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x08000131 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x08000135 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x08000139 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x08000139 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x08000139 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x08000139 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_final_cpp 0x08000141 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x08000141 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + Reset_Handler 0x08000145 Thumb Code 8 startup_stm32f10x_hd.o(.text) + ADC1_2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + ADC3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_RX1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_SCE_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel6_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel7_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel4_5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI0_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI15_10_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI9_5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + FLASH_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + FSMC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_ER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_EV_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_ER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_EV_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + PVD_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RCC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTCAlarm_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SDIO_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI1_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI3_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TAMPER_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_BRK_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_CC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_TRG_COM_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_UP_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM2_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM6_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM7_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_BRK_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_CC_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_TRG_COM_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_UP_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + UART4_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + UART5_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USBWakeUp_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + USB_LP_CAN1_RX0_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + WWDG_IRQHandler 0x0800015f Thumb Code 0 startup_stm32f10x_hd.o(.text) + __aeabi_memset 0x08000169 Thumb Code 14 memseta.o(.text) + __aeabi_memset4 0x08000169 Thumb Code 0 memseta.o(.text) + __aeabi_memset8 0x08000169 Thumb Code 0 memseta.o(.text) + __aeabi_memclr 0x08000177 Thumb Code 4 memseta.o(.text) + __aeabi_memclr4 0x08000177 Thumb Code 0 memseta.o(.text) + __aeabi_memclr8 0x08000177 Thumb Code 0 memseta.o(.text) + _memset$wrapper 0x0800017b Thumb Code 18 memseta.o(.text) + __scatterload 0x0800018d Thumb Code 28 init.o(.text) + __scatterload_rt2 0x0800018d Thumb Code 0 init.o(.text) + BusFault_Handler 0x080001b1 Thumb Code 4 stm32f10x_it.o(i.BusFault_Handler) + CheckSum 0x080001b5 Thumb Code 36 dataproc.o(i.CheckSum) + DataProc_1356 0x080001d9 Thumb Code 248 dataproc.o(i.DataProc_1356) + DataProc_A0_WriteNum_SPI2 0x080002f9 Thumb Code 516 dataproc.o(i.DataProc_A0_WriteNum_SPI2) + DataProc_A4_nrf 0x0800053d Thumb Code 350 dataproc.o(i.DataProc_A4_nrf) + DataProc_USART1 0x080006ad Thumb Code 1512 dataproc.o(i.DataProc_USART1) + Data_Init 0x08000cd1 Thumb Code 298 dataproc.o(i.Data_Init) + DebugMon_Handler 0x08000e11 Thumb Code 2 stm32f10x_it.o(i.DebugMon_Handler) + DegugPrintf 0x08000e13 Thumb Code 52 printf.o(i.DegugPrintf) + FLASH_ErasePage 0x08000e49 Thumb Code 72 stm32f10x_flash.o(i.FLASH_ErasePage) + FLASH_GetBank1Status 0x08000e95 Thumb Code 48 stm32f10x_flash.o(i.FLASH_GetBank1Status) + FLASH_Lock 0x08000ec9 Thumb Code 14 stm32f10x_flash.o(i.FLASH_Lock) + FLASH_ProgramHalfWord 0x08000edd Thumb Code 60 stm32f10x_flash.o(i.FLASH_ProgramHalfWord) + FLASH_Unlock 0x08000f1d Thumb Code 12 stm32f10x_flash.o(i.FLASH_Unlock) + FLASH_WaitForLastOperation 0x08000f35 Thumb Code 38 stm32f10x_flash.o(i.FLASH_WaitForLastOperation) + GPIO_Init 0x08000f5b Thumb Code 278 stm32f10x_gpio.o(i.GPIO_Init) + GPIO_ResetBits 0x08001071 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_ResetBits) + GPIO_SetBits 0x08001075 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_SetBits) + GetPara 0x08001079 Thumb Code 8 flash.o(i.GetPara) + HardFault_Handler 0x08001081 Thumb Code 4 stm32f10x_it.o(i.HardFault_Handler) + HexToAscii 0x08001085 Thumb Code 32 printf.o(i.HexToAscii) + IWDG_Enable 0x080010a5 Thumb Code 10 stm32f10x_iwdg.o(i.IWDG_Enable) + IWDG_Feed 0x080010b5 Thumb Code 8 main.o(i.IWDG_Feed) + IWDG_Init 0x080010bd Thumb Code 36 main.o(i.IWDG_Init) + IWDG_ReloadCounter 0x080010e1 Thumb Code 10 stm32f10x_iwdg.o(i.IWDG_ReloadCounter) + IWDG_SetPrescaler 0x080010f1 Thumb Code 6 stm32f10x_iwdg.o(i.IWDG_SetPrescaler) + IWDG_SetReload 0x080010fd Thumb Code 6 stm32f10x_iwdg.o(i.IWDG_SetReload) + IWDG_WriteAccessCmd 0x08001109 Thumb Code 6 stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd) + MemManage_Handler 0x08001115 Thumb Code 4 stm32f10x_it.o(i.MemManage_Handler) + NMI_Handler 0x08001119 Thumb Code 2 stm32f10x_it.o(i.NMI_Handler) + NRF24L01_Check 0x0800111d Thumb Code 80 nrf24l01.o(i.NRF24L01_Check) + NRF24L01_Init 0x08001175 Thumb Code 232 nrf24l01.o(i.NRF24L01_Init) + NRF24L01_RX_AHDX_CONFIG 0x08001271 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_AHDX_CONFIG) + NRF24L01_RX_AnHui_CONFIG 0x08001301 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_AnHui_CONFIG) + NRF24L01_RX_CQYD_CONFIG 0x08001391 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_CQYD_CONFIG) + NRF24L01_RX_DH_CONFIG 0x08001421 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_DH_CONFIG) + NRF24L01_RX_FJZZ_CONFIG 0x080014b1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_FJZZ_CONFIG) + NRF24L01_RX_GSYD_CONFIG 0x08001541 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_GSYD_CONFIG) + NRF24L01_RX_GXYD_CONFIG 0x080015d1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_GXYD_CONFIG) + NRF24L01_RX_GuiZhou_CONFIG 0x08001661 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_GuiZhou_CONFIG) + NRF24L01_RX_JiangXi_CONFIG 0x080016f1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_JiangXi_CONFIG) + NRF24L01_RX_LIAO_NING_CONFIG 0x08001781 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_LIAO_NING_CONFIG) + NRF24L01_RX_Mode 0x08001811 Thumb Code 166 nrf24l01.o(i.NRF24L01_RX_Mode) + NRF24L01_RX_Mode_NOACK 0x080018c5 Thumb Code 262 nrf24l01.o(i.NRF24L01_RX_Mode_NOACK) + NRF24L01_RX_NEW_LIAO_NING_CONFIG 0x080019d1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_NEW_LIAO_NING_CONFIG) + NRF24L01_RX_NMGYD_CONFIG 0x08001a61 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_NMGYD_CONFIG) + NRF24L01_RX_NeiMengGu_CONFIG 0x08001af1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_NeiMengGu_CONFIG) + NRF24L01_RX_SXYD_CONFIG 0x08001b81 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_SXYD_CONFIG) + NRF24L01_RX_SZML_CONFIG 0x08001c11 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_SZML_CONFIG) + NRF24L01_RX_ShanXiXinNuo_CONFIG 0x08001ca1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_ShanXiXinNuo_CONFIG) + NRF24L01_RX_SiChuan_CONFIG 0x08001d31 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_SiChuan_CONFIG) + NRF24L01_RX_TP_CONFIG 0x08001dc1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_TP_CONFIG) + NRF24L01_RX_TelPo_CONFIG 0x08001e51 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_TelPo_CONFIG) + NRF24L01_RX_VCM_CONFIG 0x08001ee1 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_VCM_CONFIG) + NRF24L01_RX_XDF_CONFIG 0x08001f71 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_XDF_CONFIG) + NRF24L01_RX_YunNan_CONFIG 0x08002001 Thumb Code 140 nrf24l01.o(i.NRF24L01_RX_YunNan_CONFIG) + NRF24L01_Read_Buf 0x08002091 Thumb Code 114 nrf24l01.o(i.NRF24L01_Read_Buf) + NRF24L01_Read_Reg 0x0800210d Thumb Code 78 nrf24l01.o(i.NRF24L01_Read_Reg) + NRF24L01_RxPacket 0x0800216d Thumb Code 66 nrf24l01.o(i.NRF24L01_RxPacket) + NRF24L01_Write_Buf 0x080021b1 Thumb Code 114 nrf24l01.o(i.NRF24L01_Write_Buf) + NRF24L01_Write_Reg 0x0800222d Thumb Code 84 nrf24l01.o(i.NRF24L01_Write_Reg) + NVIC_Configuration 0x08002291 Thumb Code 124 main.o(i.NVIC_Configuration) + NVIC_Init 0x0800230d Thumb Code 100 misc.o(i.NVIC_Init) + NVIC_PriorityGroupConfig 0x0800237d Thumb Code 10 misc.o(i.NVIC_PriorityGroupConfig) + PendSV_Handler 0x08002391 Thumb Code 2 stm32f10x_it.o(i.PendSV_Handler) + RCC_APB1PeriphClockCmd 0x08002395 Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + RCC_APB2PeriphClockCmd 0x080023b5 Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + RCC_Configuration 0x080023d5 Thumb Code 98 main.o(i.RCC_Configuration) + RCC_GetClocksFreq 0x08002445 Thumb Code 190 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + Readpara_from_flash 0x08002519 Thumb Code 52 flash.o(i.Readpara_from_flash) + Readstr_of_flash 0x08002555 Thumb Code 36 flash.o(i.Readstr_of_flash) + SPI1_Init 0x08002579 Thumb Code 122 spi.o(i.SPI1_Init) + SPI2_Init 0x080025fd Thumb Code 132 spi.o(i.SPI2_Init) + SPI_Cmd 0x08002689 Thumb Code 24 stm32f10x_spi.o(i.SPI_Cmd) + SPI_I2S_GetFlagStatus 0x080026a1 Thumb Code 18 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + SPI_I2S_ReceiveData 0x080026b3 Thumb Code 6 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + SPI_I2S_SendData 0x080026b9 Thumb Code 4 stm32f10x_spi.o(i.SPI_I2S_SendData) + SPI_Init 0x080026bd Thumb Code 60 stm32f10x_spi.o(i.SPI_Init) + SPI_ReadWriteByte 0x080026f9 Thumb Code 158 spi.o(i.SPI_ReadWriteByte) + SPI_SetSpeed 0x080027a1 Thumb Code 72 spi.o(i.SPI_SetSpeed) + SVC_Handler 0x080027f1 Thumb Code 2 stm32f10x_it.o(i.SVC_Handler) + SavePara 0x080027f3 Thumb Code 16 flash.o(i.SavePara) + SavePara_to_flash 0x08002805 Thumb Code 62 flash.o(i.SavePara_to_flash) + Savestr_to_flash 0x0800284d Thumb Code 40 flash.o(i.Savestr_to_flash) + SendConsoleData 0x08002875 Thumb Code 18 printf.o(i.SendConsoleData) + SendUSART2Byte 0x0800288d Thumb Code 14 printf.o(i.SendUSART2Byte) + SendUSART2Str 0x080028a1 Thumb Code 14 printf.o(i.SendUSART2Str) + SendUartByte 0x080028b5 Thumb Code 32 printf.o(i.SendUartByte) + SendUartData 0x080028d5 Thumb Code 50 printf.o(i.SendUartData) + SendUartStr 0x08002907 Thumb Code 60 printf.o(i.SendUartStr) + Startwritedata 0x08002a05 Thumb Code 16 flash.o(i.Startwritedata) + SysTick_CLKSourceConfig 0x08002a15 Thumb Code 40 misc.o(i.SysTick_CLKSourceConfig) + SysTick_Handler 0x08002a3d Thumb Code 2 stm32f10x_it.o(i.SysTick_Handler) + SystemInit 0x08002a41 Thumb Code 82 system_stm32f10x.o(i.SystemInit) + TIM3_IRQHandler 0x08002aa5 Thumb Code 134 dataproc.o(i.TIM3_IRQHandler) + TIM3_Int_Init 0x08002b4d Thumb Code 60 tim.o(i.TIM3_Int_Init) + TIM_ClearITPendingBit 0x08002b8d Thumb Code 6 stm32f10x_tim.o(i.TIM_ClearITPendingBit) + TIM_Cmd 0x08002b93 Thumb Code 24 stm32f10x_tim.o(i.TIM_Cmd) + TIM_GetITStatus 0x08002bab Thumb Code 34 stm32f10x_tim.o(i.TIM_GetITStatus) + TIM_ITConfig 0x08002bcd Thumb Code 18 stm32f10x_tim.o(i.TIM_ITConfig) + TIM_TimeBaseInit 0x08002be1 Thumb Code 122 stm32f10x_tim.o(i.TIM_TimeBaseInit) + USART1_IRQHandler 0x08002c85 Thumb Code 78 printf.o(i.USART1_IRQHandler) + USART2_IRQHandler 0x08002ce1 Thumb Code 78 usart2.o(i.USART2_IRQHandler) + USART2_Init 0x08002d3d Thumb Code 126 usart2.o(i.USART2_Init) + USART3_IRQHandler 0x08002dc5 Thumb Code 88 printf.o(i.USART3_IRQHandler) + USART_ClearFlag 0x08002e29 Thumb Code 18 stm32f10x_usart.o(i.USART_ClearFlag) + USART_ClearITPendingBit 0x08002e3b Thumb Code 30 stm32f10x_usart.o(i.USART_ClearITPendingBit) + USART_Cmd 0x08002e59 Thumb Code 24 stm32f10x_usart.o(i.USART_Cmd) + USART_Configuration 0x08002e71 Thumb Code 266 printf.o(i.USART_Configuration) + USART_GetFlagStatus 0x08002f8d Thumb Code 26 stm32f10x_usart.o(i.USART_GetFlagStatus) + USART_GetITStatus 0x08002fa7 Thumb Code 84 stm32f10x_usart.o(i.USART_GetITStatus) + USART_ITConfig 0x08002ffb Thumb Code 74 stm32f10x_usart.o(i.USART_ITConfig) + USART_Init 0x08003045 Thumb Code 210 stm32f10x_usart.o(i.USART_Init) + USART_ReceiveData 0x0800311d Thumb Code 10 stm32f10x_usart.o(i.USART_ReceiveData) + USART_SendData 0x08003127 Thumb Code 8 stm32f10x_usart.o(i.USART_SendData) + UsageFault_Handler 0x0800312f Thumb Code 4 stm32f10x_it.o(i.UsageFault_Handler) + Write_Complete 0x08003133 Thumb Code 8 flash.o(i.Write_Complete) + __0printf$bare 0x0800313d Thumb Code 8 printfb.o(i.__0printf$bare) + __1printf$bare 0x0800313d Thumb Code 0 printfb.o(i.__0printf$bare) + __2printf 0x0800313d Thumb Code 0 printfb.o(i.__0printf$bare) + __scatterload_copy 0x0800314d Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x0800315b Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x0800315d Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + delay_ms 0x0800318d Thumb Code 42 delay.o(i.delay_ms) + fputc 0x080031b9 Thumb Code 32 printf.o(i.fputc) + led_init 0x080031dd Thumb Code 84 led.o(i.led_init) + main 0x08003235 Thumb Code 402 main.o(i.main) + TX_ADDRESS 0x08003568 Data 5 nrf24l01.o(.constdata) + RX_ADDRESS 0x0800356d Data 5 nrf24l01.o(.constdata) + addr 0x08003572 Data 5 nrf24l01.o(.constdata) + Jiang_Xi 0x08003577 Data 5 nrf24l01.o(.constdata) + TEL_PO 0x0800357c Data 5 nrf24l01.o(.constdata) + YUN_NAN 0x08003581 Data 5 nrf24l01.o(.constdata) + GUI_ZHOU 0x08003586 Data 5 nrf24l01.o(.constdata) + SI_CHUAN 0x0800358b Data 5 nrf24l01.o(.constdata) + NEI_MENG_GU 0x08003590 Data 5 nrf24l01.o(.constdata) + AN_HUI 0x08003595 Data 5 nrf24l01.o(.constdata) + SHAN_XI_XIN_NUO 0x0800359a Data 5 nrf24l01.o(.constdata) + VCM 0x0800359f Data 5 nrf24l01.o(.constdata) + LIAO_NING 0x080035a4 Data 5 nrf24l01.o(.constdata) + NEW_LIAO_NING 0x080035a9 Data 5 nrf24l01.o(.constdata) + TP 0x080035ae Data 5 nrf24l01.o(.constdata) + NEI_MENG_GU_YI_DONG 0x080035b3 Data 5 nrf24l01.o(.constdata) + GUANG_XI_YI_DONG 0x080035b8 Data 5 nrf24l01.o(.constdata) + LIAO_NING_DIAN_XI 0x080035bd Data 5 nrf24l01.o(.constdata) + FU_JIAN_ZHEN_ZHUO 0x080035c2 Data 5 nrf24l01.o(.constdata) + SU_ZHOU_MU_LANG 0x080035c7 Data 5 nrf24l01.o(.constdata) + CHONG_QIN_YI_DONG 0x080035cc Data 5 nrf24l01.o(.constdata) + SHAN_XI_YI_DONG 0x080035d1 Data 5 nrf24l01.o(.constdata) + QUAN_TONG 0x080035d6 Data 5 nrf24l01.o(.constdata) + GAN_SU_YI_DONG 0x080035db Data 5 nrf24l01.o(.constdata) + XDF 0x080035e0 Data 5 nrf24l01.o(.constdata) + DH 0x080035e5 Data 5 nrf24l01.o(.constdata) + ANHUI_DIANXIN 0x080035ea Data 5 nrf24l01.o(.constdata) + Region$$Table$$Base 0x080035f0 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08003610 Number 0 anon$$obj.o(Region$$Table) + UARTtoConsole_RxBufferWr 0x20000000 Data 1 printf.o(.data) + UARTtoConsole_RxBufferRd 0x20000001 Data 1 printf.o(.data) + USART1_TX_CNT 0x20000002 Data 1 printf.o(.data) + USART1_RX_CNT 0x20000003 Data 1 printf.o(.data) + USART1_REC_Status 0x20000004 Data 2 printf.o(.data) + USART_APP_RX 0x20000006 Data 2 printf.o(.data) + USART3_TX_CNT 0x20000008 Data 1 printf.o(.data) + USART3_RX_CNT 0x20000009 Data 1 printf.o(.data) + USART3_REC_Status 0x2000000a Data 2 printf.o(.data) + CheckData_1356 0x2000000c Data 10 dataproc.o(.data) + GetNum_1356 0x20000016 Data 5 dataproc.o(.data) + count 0x20000026 Data 2 dataproc.o(.data) + count_num 0x20000028 Data 2 dataproc.o(.data) + flag_1ms 0x2000002a Data 1 dataproc.o(.data) + first_clear_flag 0x2000002b Data 1 dataproc.o(.data) + HW_Open 0x2000002c Data 1 dataproc.o(.data) + HW_OpenCount 0x2000002e Data 2 dataproc.o(.data) + Flag_update 0x20000030 Data 1 dataproc.o(.data) + WriteOKFlag 0x20000031 Data 1 dataproc.o(.data) + protocol_config_flg 0x20000032 Data 1 dataproc.o(.data) + CmdRspBufferWr_Rx 0x20000033 Data 1 dataproc.o(.data) + idBuf 0x20000034 Data 5 dataproc.o(.data) + count_A34 0x2000003a Data 2 dataproc.o(.data) + idResA3Buf 0x2000003c Data 5 dataproc.o(.data) + ReadAttenID 0x20000041 Data 5 dataproc.o(.data) + newIdFlag 0x20000046 Data 1 dataproc.o(.data) + recFlag 0x20000047 Data 1 dataproc.o(.data) + rspFlag_A3 0x20000048 Data 1 dataproc.o(.data) + read1356flag 0x20000049 Data 1 dataproc.o(.data) + txBuf 0x2000004a Data 32 dataproc.o(.data) + txA3Buf 0x2000006a Data 32 dataproc.o(.data) + rspFlag 0x2000008a Data 1 dataproc.o(.data) + wrNumFlag 0x2000008b Data 1 dataproc.o(.data) + USART2_TX_CNT 0x2000008c Data 1 usart2.o(.data) + USART2_RX_CNT 0x2000008d Data 1 usart2.o(.data) + USART2_REC_Status 0x2000008e Data 2 usart2.o(.data) + __stdout 0x200000a4 Data 4 stdout.o(.data) + UARTtoConsole_RxBuffer 0x200000a8 Data 100 printf.o(.bss) + USART1_RX_BUF 0x2000010c Data 200 printf.o(.bss) + USART3_RX_BUF 0x200001d4 Data 200 printf.o(.bss) + uartSendData 0x2000029c Data 100 dataproc.o(.bss) + uartRecData 0x20000300 Data 100 dataproc.o(.bss) + uartSendRdNumData 0x20000364 Data 100 dataproc.o(.bss) + uartSendWrNumOkData 0x200003c8 Data 100 dataproc.o(.bss) + uartSendConfigKaoQinData 0x2000042c Data 100 dataproc.o(.bss) + CmdRspBuffer 0x20000490 Data 100 dataproc.o(.bss) + USART2_RX_BUF 0x200004f4 Data 64 usart2.o(.bss) + StoreBuffer 0x20000534 Data 20 flash.o(.bss) + Save_Buffer 0x20000548 Data 20 flash.o(.bss) + __initial_sp 0x20000960 Data 0 startup_stm32f10x_hd.o(STACK) + USART1_RX_DAT 0x20001000 Data 20480 printf.o(.ARM.__AT_0x20001000) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000131 + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x000036b8, Max: 0x00040000, ABSOLUTE) + + Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x00003610, Max: 0x00040000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x00000130 Data RO 2544 RESET startup_stm32f10x_hd.o + 0x08000130 0x00000000 Code RO 2549 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x08000130 0x00000004 Code RO 2818 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x08000134 0x00000004 Code RO 2821 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x08000138 0x00000000 Code RO 2823 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x08000138 0x00000000 Code RO 2825 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x08000138 0x00000008 Code RO 2826 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x08000140 0x00000000 Code RO 2828 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o) + 0x08000140 0x00000000 Code RO 2830 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o) + 0x08000140 0x00000004 Code RO 2819 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000144 0x00000024 Code RO 2545 .text startup_stm32f10x_hd.o + 0x08000168 0x00000024 Code RO 2554 .text mc_w.l(memseta.o) + 0x0800018c 0x00000024 Code RO 2848 .text mc_w.l(init.o) + 0x080001b0 0x00000004 Code RO 881 i.BusFault_Handler stm32f10x_it.o + 0x080001b4 0x00000024 Code RO 598 i.CheckSum dataproc.o + 0x080001d8 0x00000120 Code RO 599 i.DataProc_1356 dataproc.o + 0x080002f8 0x00000244 Code RO 600 i.DataProc_A0_WriteNum_SPI2 dataproc.o + 0x0800053c 0x00000170 Code RO 602 i.DataProc_A4_nrf dataproc.o + 0x080006ac 0x00000624 Code RO 606 i.DataProc_USART1 dataproc.o + 0x08000cd0 0x00000140 Code RO 607 i.Data_Init dataproc.o + 0x08000e10 0x00000002 Code RO 882 i.DebugMon_Handler stm32f10x_it.o + 0x08000e12 0x00000034 Code RO 1 i.DegugPrintf printf.o + 0x08000e46 0x00000002 PAD + 0x08000e48 0x0000004c Code RO 2325 i.FLASH_ErasePage stm32f10x_flash.o + 0x08000e94 0x00000034 Code RO 2326 i.FLASH_GetBank1Status stm32f10x_flash.o + 0x08000ec8 0x00000014 Code RO 2335 i.FLASH_Lock stm32f10x_flash.o + 0x08000edc 0x00000040 Code RO 2338 i.FLASH_ProgramHalfWord stm32f10x_flash.o + 0x08000f1c 0x00000018 Code RO 2343 i.FLASH_Unlock stm32f10x_flash.o + 0x08000f34 0x00000026 Code RO 2347 i.FLASH_WaitForLastOperation stm32f10x_flash.o + 0x08000f5a 0x00000116 Code RO 1469 i.GPIO_Init stm32f10x_gpio.o + 0x08001070 0x00000004 Code RO 1476 i.GPIO_ResetBits stm32f10x_gpio.o + 0x08001074 0x00000004 Code RO 1477 i.GPIO_SetBits stm32f10x_gpio.o + 0x08001078 0x00000008 Code RO 706 i.GetPara flash.o + 0x08001080 0x00000004 Code RO 883 i.HardFault_Handler stm32f10x_it.o + 0x08001084 0x00000020 Code RO 2 i.HexToAscii printf.o + 0x080010a4 0x00000010 Code RO 2278 i.IWDG_Enable stm32f10x_iwdg.o + 0x080010b4 0x00000008 Code RO 225 i.IWDG_Feed main.o + 0x080010bc 0x00000024 Code RO 226 i.IWDG_Init main.o + 0x080010e0 0x00000010 Code RO 2280 i.IWDG_ReloadCounter stm32f10x_iwdg.o + 0x080010f0 0x0000000c Code RO 2281 i.IWDG_SetPrescaler stm32f10x_iwdg.o + 0x080010fc 0x0000000c Code RO 2282 i.IWDG_SetReload stm32f10x_iwdg.o + 0x08001108 0x0000000c Code RO 2283 i.IWDG_WriteAccessCmd stm32f10x_iwdg.o + 0x08001114 0x00000004 Code RO 884 i.MemManage_Handler stm32f10x_it.o + 0x08001118 0x00000002 Code RO 885 i.NMI_Handler stm32f10x_it.o + 0x0800111a 0x00000002 PAD + 0x0800111c 0x00000058 Code RO 319 i.NRF24L01_Check nrf24l01.o + 0x08001174 0x000000fc Code RO 321 i.NRF24L01_Init nrf24l01.o + 0x08001270 0x00000090 Code RO 322 i.NRF24L01_RX_AHDX_CONFIG nrf24l01.o + 0x08001300 0x00000090 Code RO 323 i.NRF24L01_RX_AnHui_CONFIG nrf24l01.o + 0x08001390 0x00000090 Code RO 324 i.NRF24L01_RX_CQYD_CONFIG nrf24l01.o + 0x08001420 0x00000090 Code RO 325 i.NRF24L01_RX_DH_CONFIG nrf24l01.o + 0x080014b0 0x00000090 Code RO 326 i.NRF24L01_RX_FJZZ_CONFIG nrf24l01.o + 0x08001540 0x00000090 Code RO 327 i.NRF24L01_RX_GSYD_CONFIG nrf24l01.o + 0x080015d0 0x00000090 Code RO 328 i.NRF24L01_RX_GXYD_CONFIG nrf24l01.o + 0x08001660 0x00000090 Code RO 329 i.NRF24L01_RX_GuiZhou_CONFIG nrf24l01.o + 0x080016f0 0x00000090 Code RO 330 i.NRF24L01_RX_JiangXi_CONFIG nrf24l01.o + 0x08001780 0x00000090 Code RO 331 i.NRF24L01_RX_LIAO_NING_CONFIG nrf24l01.o + 0x08001810 0x000000b4 Code RO 332 i.NRF24L01_RX_Mode nrf24l01.o + 0x080018c4 0x0000010c Code RO 333 i.NRF24L01_RX_Mode_NOACK nrf24l01.o + 0x080019d0 0x00000090 Code RO 335 i.NRF24L01_RX_NEW_LIAO_NING_CONFIG nrf24l01.o + 0x08001a60 0x00000090 Code RO 336 i.NRF24L01_RX_NMGYD_CONFIG nrf24l01.o + 0x08001af0 0x00000090 Code RO 337 i.NRF24L01_RX_NeiMengGu_CONFIG nrf24l01.o + 0x08001b80 0x00000090 Code RO 338 i.NRF24L01_RX_SXYD_CONFIG nrf24l01.o + 0x08001c10 0x00000090 Code RO 339 i.NRF24L01_RX_SZML_CONFIG nrf24l01.o + 0x08001ca0 0x00000090 Code RO 340 i.NRF24L01_RX_ShanXiXinNuo_CONFIG nrf24l01.o + 0x08001d30 0x00000090 Code RO 341 i.NRF24L01_RX_SiChuan_CONFIG nrf24l01.o + 0x08001dc0 0x00000090 Code RO 342 i.NRF24L01_RX_TP_CONFIG nrf24l01.o + 0x08001e50 0x00000090 Code RO 343 i.NRF24L01_RX_TelPo_CONFIG nrf24l01.o + 0x08001ee0 0x00000090 Code RO 344 i.NRF24L01_RX_VCM_CONFIG nrf24l01.o + 0x08001f70 0x00000090 Code RO 345 i.NRF24L01_RX_XDF_CONFIG nrf24l01.o + 0x08002000 0x00000090 Code RO 346 i.NRF24L01_RX_YunNan_CONFIG nrf24l01.o + 0x08002090 0x0000007c Code RO 347 i.NRF24L01_Read_Buf nrf24l01.o + 0x0800210c 0x00000060 Code RO 348 i.NRF24L01_Read_Reg nrf24l01.o + 0x0800216c 0x00000042 Code RO 349 i.NRF24L01_RxPacket nrf24l01.o + 0x080021ae 0x00000002 PAD + 0x080021b0 0x0000007c Code RO 352 i.NRF24L01_Write_Buf nrf24l01.o + 0x0800222c 0x00000064 Code RO 353 i.NRF24L01_Write_Reg nrf24l01.o + 0x08002290 0x0000007c Code RO 230 i.NVIC_Configuration main.o + 0x0800230c 0x00000070 Code RO 1424 i.NVIC_Init misc.o + 0x0800237c 0x00000014 Code RO 1425 i.NVIC_PriorityGroupConfig misc.o + 0x08002390 0x00000002 Code RO 886 i.PendSV_Handler stm32f10x_it.o + 0x08002392 0x00000002 PAD + 0x08002394 0x00000020 Code RO 965 i.RCC_APB1PeriphClockCmd stm32f10x_rcc.o + 0x080023b4 0x00000020 Code RO 967 i.RCC_APB2PeriphClockCmd stm32f10x_rcc.o + 0x080023d4 0x00000070 Code RO 231 i.RCC_Configuration main.o + 0x08002444 0x000000d4 Code RO 975 i.RCC_GetClocksFreq stm32f10x_rcc.o + 0x08002518 0x0000003c Code RO 707 i.Readpara_from_flash flash.o + 0x08002554 0x00000024 Code RO 708 i.Readstr_of_flash flash.o + 0x08002578 0x00000084 Code RO 556 i.SPI1_Init spi.o + 0x080025fc 0x0000008c Code RO 557 i.SPI2_Init spi.o + 0x08002688 0x00000018 Code RO 1585 i.SPI_Cmd stm32f10x_spi.o + 0x080026a0 0x00000012 Code RO 1593 i.SPI_I2S_GetFlagStatus stm32f10x_spi.o + 0x080026b2 0x00000006 Code RO 1596 i.SPI_I2S_ReceiveData stm32f10x_spi.o + 0x080026b8 0x00000004 Code RO 1597 i.SPI_I2S_SendData stm32f10x_spi.o + 0x080026bc 0x0000003c Code RO 1598 i.SPI_Init stm32f10x_spi.o + 0x080026f8 0x000000a8 Code RO 558 i.SPI_ReadWriteByte spi.o + 0x080027a0 0x00000050 Code RO 559 i.SPI_SetSpeed spi.o + 0x080027f0 0x00000002 Code RO 887 i.SVC_Handler stm32f10x_it.o + 0x080027f2 0x00000010 Code RO 709 i.SavePara flash.o + 0x08002802 0x00000002 PAD + 0x08002804 0x00000048 Code RO 710 i.SavePara_to_flash flash.o + 0x0800284c 0x00000028 Code RO 711 i.Savestr_to_flash flash.o + 0x08002874 0x00000018 Code RO 4 i.SendConsoleData printf.o + 0x0800288c 0x00000014 Code RO 6 i.SendUSART2Byte printf.o + 0x080028a0 0x00000014 Code RO 7 i.SendUSART2Str printf.o + 0x080028b4 0x00000020 Code RO 8 i.SendUartByte printf.o + 0x080028d4 0x00000032 Code RO 9 i.SendUartData printf.o + 0x08002906 0x0000003c Code RO 11 i.SendUartStr printf.o + 0x08002942 0x00000008 Code RO 2508 i.SetSysClock system_stm32f10x.o + 0x0800294a 0x00000002 PAD + 0x0800294c 0x000000b8 Code RO 2509 i.SetSysClockTo24 system_stm32f10x.o + 0x08002a04 0x00000010 Code RO 712 i.Startwritedata flash.o + 0x08002a14 0x00000028 Code RO 1428 i.SysTick_CLKSourceConfig misc.o + 0x08002a3c 0x00000002 Code RO 888 i.SysTick_Handler stm32f10x_it.o + 0x08002a3e 0x00000002 PAD + 0x08002a40 0x00000064 Code RO 2511 i.SystemInit system_stm32f10x.o + 0x08002aa4 0x000000a8 Code RO 608 i.TIM3_IRQHandler dataproc.o + 0x08002b4c 0x00000040 Code RO 544 i.TIM3_Int_Init tim.o + 0x08002b8c 0x00000006 Code RO 1738 i.TIM_ClearITPendingBit stm32f10x_tim.o + 0x08002b92 0x00000018 Code RO 1743 i.TIM_Cmd stm32f10x_tim.o + 0x08002baa 0x00000022 Code RO 1764 i.TIM_GetITStatus stm32f10x_tim.o + 0x08002bcc 0x00000012 Code RO 1768 i.TIM_ITConfig stm32f10x_tim.o + 0x08002bde 0x00000002 PAD + 0x08002be0 0x000000a4 Code RO 1814 i.TIM_TimeBaseInit stm32f10x_tim.o + 0x08002c84 0x0000005c Code RO 12 i.USART1_IRQHandler printf.o + 0x08002ce0 0x0000005c Code RO 684 i.USART2_IRQHandler usart2.o + 0x08002d3c 0x00000088 Code RO 685 i.USART2_Init usart2.o + 0x08002dc4 0x00000064 Code RO 13 i.USART3_IRQHandler printf.o + 0x08002e28 0x00000012 Code RO 1238 i.USART_ClearFlag stm32f10x_usart.o + 0x08002e3a 0x0000001e Code RO 1239 i.USART_ClearITPendingBit stm32f10x_usart.o + 0x08002e58 0x00000018 Code RO 1242 i.USART_Cmd stm32f10x_usart.o + 0x08002e70 0x0000011c Code RO 14 i.USART_Configuration printf.o + 0x08002f8c 0x0000001a Code RO 1245 i.USART_GetFlagStatus stm32f10x_usart.o + 0x08002fa6 0x00000054 Code RO 1246 i.USART_GetITStatus stm32f10x_usart.o + 0x08002ffa 0x0000004a Code RO 1248 i.USART_ITConfig stm32f10x_usart.o + 0x08003044 0x000000d8 Code RO 1249 i.USART_Init stm32f10x_usart.o + 0x0800311c 0x0000000a Code RO 1256 i.USART_ReceiveData stm32f10x_usart.o + 0x08003126 0x00000008 Code RO 1259 i.USART_SendData stm32f10x_usart.o + 0x0800312e 0x00000004 Code RO 889 i.UsageFault_Handler stm32f10x_it.o + 0x08003132 0x00000008 Code RO 713 i.Write_Complete flash.o + 0x0800313a 0x00000002 PAD + 0x0800313c 0x00000010 Code RO 2559 i.__0printf$bare mc_w.l(printfb.o) + 0x0800314c 0x0000000e Code RO 2860 i.__scatterload_copy mc_w.l(handlers.o) + 0x0800315a 0x00000002 Code RO 2861 i.__scatterload_null mc_w.l(handlers.o) + 0x0800315c 0x0000000e Code RO 2862 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x0800316a 0x00000022 Code RO 2566 i._printf_core mc_w.l(printfb.o) + 0x0800318c 0x0000002a Code RO 205 i.delay_ms delay.o + 0x080031b6 0x00000002 PAD + 0x080031b8 0x00000024 Code RO 16 i.fputc printf.o + 0x080031dc 0x00000058 Code RO 586 i.led_init led.o + 0x08003234 0x00000334 Code RO 232 i.main main.o + 0x08003568 0x00000087 Data RO 355 .constdata nrf24l01.o + 0x080035ef 0x00000001 PAD + 0x080035f0 0x00000020 Data RO 2858 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x00006000, Max: 0x00006000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x0000000c Data RW 19 .data printf.o + 0x2000000c 0x00000080 Data RW 610 .data dataproc.o + 0x2000008c 0x00000004 Data RW 687 .data usart2.o + 0x20000090 0x00000014 Data RW 996 .data stm32f10x_rcc.o + 0x200000a4 0x00000004 Data RW 2832 .data mc_w.l(stdout.o) + 0x200000a8 0x000001f4 Zero RW 18 .bss printf.o + 0x2000029c 0x00000258 Zero RW 609 .bss dataproc.o + 0x200004f4 0x00000040 Zero RW 686 .bss usart2.o + 0x20000534 0x00000028 Zero RW 714 .bss flash.o + 0x2000055c 0x00000004 PAD + 0x20000560 0x00000400 Zero RW 2542 STACK startup_stm32f10x_hd.o + 0x20000960 0x000006a0 PAD + 0x20001000 0x00005000 Zero RW 17 .ARM.__AT_0x20001000 printf.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 0 0 0 0 0 32 core_cm3.o + 3332 324 0 128 600 24976 dataproc.o + 42 0 0 0 0 603 delay.o + 256 18 0 0 40 5405 flash.o + 88 4 0 0 0 547 led.o + 1100 456 0 0 0 19347 main.o + 172 22 0 0 0 4329 misc.o + 4466 214 135 0 0 22452 nrf24l01.o + 802 66 0 12 20980 262356 printf.o + 520 36 0 0 0 2711 spi.o + 36 8 304 0 1024 928 startup_stm32f10x_hd.o + 274 30 0 0 0 10546 stm32f10x_flash.o + 286 0 0 0 0 11992 stm32f10x_gpio.o + 26 0 0 0 0 4406 stm32f10x_it.o + 68 30 0 0 0 2942 stm32f10x_iwdg.o + 276 34 0 20 0 15278 stm32f10x_rcc.o + 112 0 0 0 0 11534 stm32f10x_spi.o + 246 42 0 0 0 23474 stm32f10x_tim.o + 490 6 0 0 0 24781 stm32f10x_usart.o + 292 24 0 0 0 2153 system_stm32f10x.o + 64 4 0 0 0 636 tim.o + 228 24 0 4 64 2020 usart2.o + + ---------------------------------------------------------------------- + 13196 1342 472 164 24408 453448 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 20 0 1 0 1700 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 8 4 0 0 0 0 entry9a.o + 30 0 0 0 0 0 handlers.o + 36 8 0 0 0 68 init.o + 36 0 0 0 0 108 memseta.o + 50 8 0 0 0 152 printfb.o + 0 0 0 4 0 0 stdout.o + + ---------------------------------------------------------------------- + 172 24 0 4 0 328 Library Totals + 0 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 172 24 0 4 0 328 mc_w.l + + ---------------------------------------------------------------------- + 172 24 0 4 0 328 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 13368 1366 472 168 24408 447636 Grand Totals + 13368 1366 472 168 24408 447636 ELF Image Totals + 13368 1366 472 168 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 13840 ( 13.52kB) + Total RW Size (RW Data + ZI Data) 24576 ( 24.00kB) + Total ROM Size (Code + RO Data + RW Data) 14008 ( 13.68kB) + +============================================================================== + diff --git a/RVMDK/List/startup_stm32f10x_hd.lst b/RVMDK/List/startup_stm32f10x_hd.lst new file mode 100644 index 0000000..8abfbf8 --- /dev/null +++ b/RVMDK/List/startup_stm32f10x_hd.lst @@ -0,0 +1,1697 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2010 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f10x_hd.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V3.4.0 + 5 00000000 ;* Date : 10/15/2010 + 6 00000000 ;* Description : STM32F10x High Density Devices v + ector table for MDK-ARM + 7 00000000 ;* toolchain. + 8 00000000 ;* This module performs: + 9 00000000 ;* - Set the initial SP + 10 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 11 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 12 00000000 ;* - Configure the clock system and + also configure the external + 13 00000000 ;* SRAM mounted on STM3210E-EVAL + board to be used as data + 14 00000000 ;* memory (optional, to be enable + d by user) + 15 00000000 ;* - Branches to __main in the C li + brary (which eventually + 16 00000000 ;* calls main()). + 17 00000000 ;* After Reset the CortexM3 process + or is in Thread mode, + 18 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 19 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 20 00000000 ;******************************************************* + ************************ + 21 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A + T PROVIDING CUSTOMERS + 22 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR + DER FOR THEM TO SAVE TIME. + 23 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB + LE FOR ANY DIRECT, + 24 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY + CLAIMS ARISING FROM THE + 25 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM + ERS OF THE CODING + 26 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR + PRODUCTS. + 27 00000000 ;******************************************************* + ************************ + 28 00000000 + 29 00000000 ; Amount of memory (in bytes) allocated for Stack + 30 00000000 ; Tailor this value to your application needs + 31 00000000 ; Stack Configuration + 32 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 33 00000000 ; + 34 00000000 + 35 00000000 00000400 + Stack_Size + EQU 0x00000400 + 36 00000000 + 37 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 38 00000000 Stack_Mem + + + +ARM Macro Assembler Page 2 + + + SPACE Stack_Size + 39 00000400 __initial_sp + 40 00000400 + 41 00000400 ; Heap Configuration + 42 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 43 00000400 ; + 44 00000400 + 45 00000400 00000200 + Heap_Size + EQU 0x00000200 + 46 00000400 + 47 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 48 00000000 __heap_base + 49 00000000 Heap_Mem + SPACE Heap_Size + 50 00000200 __heap_limit + 51 00000200 + 52 00000200 PRESERVE8 + 53 00000200 THUMB + 54 00000200 + 55 00000200 + 56 00000200 ; Vector Table Mapped to Address 0 at Reset + 57 00000200 AREA RESET, DATA, READONLY + 58 00000000 EXPORT __Vectors + 59 00000000 EXPORT __Vectors_End + 60 00000000 EXPORT __Vectors_Size + 61 00000000 + 62 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 63 00000004 00000000 DCD Reset_Handler ; Reset Handler + 64 00000008 00000000 DCD NMI_Handler ; NMI Handler + 65 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 66 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 67 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 68 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 69 0000001C 00000000 DCD 0 ; Reserved + 70 00000020 00000000 DCD 0 ; Reserved + 71 00000024 00000000 DCD 0 ; Reserved + 72 00000028 00000000 DCD 0 ; Reserved + 73 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 74 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 75 00000034 00000000 DCD 0 ; Reserved + 76 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 77 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 78 00000040 + 79 00000040 ; External Interrupts + 80 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + + + +ARM Macro Assembler Page 3 + + + 81 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + 82 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper + 83 0000004C 00000000 DCD RTC_IRQHandler ; RTC + 84 00000050 00000000 DCD FLASH_IRQHandler ; Flash + 85 00000054 00000000 DCD RCC_IRQHandler ; RCC + 86 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 + 87 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 + 88 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 + 89 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 + 90 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 + 91 0000006C 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 92 00000070 00000000 DCD DMA1_Channel2_IRQHandler + ; DMA1 Channel 2 + 93 00000074 00000000 DCD DMA1_Channel3_IRQHandler + ; DMA1 Channel 3 + 94 00000078 00000000 DCD DMA1_Channel4_IRQHandler + ; DMA1 Channel 4 + 95 0000007C 00000000 DCD DMA1_Channel5_IRQHandler + ; DMA1 Channel 5 + 96 00000080 00000000 DCD DMA1_Channel6_IRQHandler + ; DMA1 Channel 6 + 97 00000084 00000000 DCD DMA1_Channel7_IRQHandler + ; DMA1 Channel 7 + 98 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + + 99 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB + High Priority or C + AN1 TX + 100 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US + B Low Priority or + CAN1 RX0 + 101 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + 102 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + 103 0000009C 00000000 DCD EXTI9_5_IRQHandler + ; EXTI Line 9..5 + 104 000000A0 00000000 DCD TIM1_BRK_IRQHandler + ; TIM1 Break + 105 000000A4 00000000 DCD TIM1_UP_IRQHandler + ; TIM1 Update + 106 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 + Trigger and Commuta + tion + 107 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 108 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + 109 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + 110 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + 111 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + 112 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + 113 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + 114 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + 115 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + 116 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + + + +ARM Macro Assembler Page 4 + + + 117 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + 118 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + 119 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + 120 000000E0 00000000 DCD EXTI15_10_IRQHandler + ; EXTI Line 15..10 + 121 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm + through EXTI Line + 122 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake + up from suspend + 123 000000EC 00000000 DCD TIM8_BRK_IRQHandler + ; TIM8 Break + 124 000000F0 00000000 DCD TIM8_UP_IRQHandler + ; TIM8 Update + 125 000000F4 00000000 DCD TIM8_TRG_COM_IRQHandler ; TIM8 + Trigger and Commuta + tion + 126 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu + re Compare + 127 000000FC 00000000 DCD ADC3_IRQHandler ; ADC3 + 128 00000100 00000000 DCD FSMC_IRQHandler ; FSMC + 129 00000104 00000000 DCD SDIO_IRQHandler ; SDIO + 130 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 + 131 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 + 132 00000110 00000000 DCD UART4_IRQHandler ; UART4 + 133 00000114 00000000 DCD UART5_IRQHandler ; UART5 + 134 00000118 00000000 DCD TIM6_IRQHandler ; TIM6 + 135 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7 + 136 00000120 00000000 DCD DMA2_Channel1_IRQHandler + ; DMA2 Channel1 + 137 00000124 00000000 DCD DMA2_Channel2_IRQHandler + ; DMA2 Channel2 + 138 00000128 00000000 DCD DMA2_Channel3_IRQHandler + ; DMA2 Channel3 + 139 0000012C 00000000 DCD DMA2_Channel4_5_IRQHandler ; DM + A2 Channel4 & Chann + el5 + 140 00000130 __Vectors_End + 141 00000130 + 142 00000130 00000130 + __Vectors_Size + EQU __Vectors_End - __Vectors + 143 00000130 + 144 00000130 AREA |.text|, CODE, READONLY + 145 00000000 + 146 00000000 ; Reset handler + 147 00000000 Reset_Handler + PROC + 148 00000000 EXPORT Reset_Handler [WEAK +] + 149 00000000 IMPORT __main + 150 00000000 IMPORT SystemInit + 151 00000000 4806 LDR R0, =SystemInit + 152 00000002 4780 BLX R0 + 153 00000004 4806 LDR R0, =__main + 154 00000006 4700 BX R0 + 155 00000008 ENDP + 156 00000008 + 157 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + + + +ARM Macro Assembler Page 5 + + + 158 00000008 + 159 00000008 NMI_Handler + PROC + 160 00000008 EXPORT NMI_Handler [WEA +K] + 161 00000008 E7FE B . + 162 0000000A ENDP + 164 0000000A HardFault_Handler + PROC + 165 0000000A EXPORT HardFault_Handler [WEA +K] + 166 0000000A E7FE B . + 167 0000000C ENDP + 169 0000000C MemManage_Handler + PROC + 170 0000000C EXPORT MemManage_Handler [WEA +K] + 171 0000000C E7FE B . + 172 0000000E ENDP + 174 0000000E BusFault_Handler + PROC + 175 0000000E EXPORT BusFault_Handler [WEA +K] + 176 0000000E E7FE B . + 177 00000010 ENDP + 179 00000010 UsageFault_Handler + PROC + 180 00000010 EXPORT UsageFault_Handler [WEA +K] + 181 00000010 E7FE B . + 182 00000012 ENDP + 183 00000012 SVC_Handler + PROC + 184 00000012 EXPORT SVC_Handler [WEA +K] + 185 00000012 E7FE B . + 186 00000014 ENDP + 188 00000014 DebugMon_Handler + PROC + 189 00000014 EXPORT DebugMon_Handler [WEA +K] + 190 00000014 E7FE B . + 191 00000016 ENDP + 192 00000016 PendSV_Handler + PROC + 193 00000016 EXPORT PendSV_Handler [WEA +K] + 194 00000016 E7FE B . + 195 00000018 ENDP + 196 00000018 SysTick_Handler + PROC + 197 00000018 EXPORT SysTick_Handler [WEA +K] + 198 00000018 E7FE B . + 199 0000001A ENDP + 200 0000001A + 201 0000001A Default_Handler + PROC + 202 0000001A + + + +ARM Macro Assembler Page 6 + + + 203 0000001A EXPORT WWDG_IRQHandler [WEA +K] + 204 0000001A EXPORT PVD_IRQHandler [WEA +K] + 205 0000001A EXPORT TAMPER_IRQHandler [WEA +K] + 206 0000001A EXPORT RTC_IRQHandler [WEA +K] + 207 0000001A EXPORT FLASH_IRQHandler [WEA +K] + 208 0000001A EXPORT RCC_IRQHandler [WEA +K] + 209 0000001A EXPORT EXTI0_IRQHandler [WEA +K] + 210 0000001A EXPORT EXTI1_IRQHandler [WEA +K] + 211 0000001A EXPORT EXTI2_IRQHandler [WEA +K] + 212 0000001A EXPORT EXTI3_IRQHandler [WEA +K] + 213 0000001A EXPORT EXTI4_IRQHandler [WEA +K] + 214 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA +K] + 215 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA +K] + 216 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA +K] + 217 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA +K] + 218 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA +K] + 219 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA +K] + 220 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA +K] + 221 0000001A EXPORT ADC1_2_IRQHandler [WEA +K] + 222 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA +K] + 223 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA +K] + 224 0000001A EXPORT CAN1_RX1_IRQHandler [WEA +K] + 225 0000001A EXPORT CAN1_SCE_IRQHandler [WEA +K] + 226 0000001A EXPORT EXTI9_5_IRQHandler [WEA +K] + 227 0000001A EXPORT TIM1_BRK_IRQHandler [WEA +K] + 228 0000001A EXPORT TIM1_UP_IRQHandler [WEA +K] + 229 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA +K] + 230 0000001A EXPORT TIM1_CC_IRQHandler [WEA +K] + 231 0000001A EXPORT TIM2_IRQHandler [WEA +K] + 232 0000001A EXPORT TIM3_IRQHandler [WEA + + + +ARM Macro Assembler Page 7 + + +K] + 233 0000001A EXPORT TIM4_IRQHandler [WEA +K] + 234 0000001A EXPORT I2C1_EV_IRQHandler [WEA +K] + 235 0000001A EXPORT I2C1_ER_IRQHandler [WEA +K] + 236 0000001A EXPORT I2C2_EV_IRQHandler [WEA +K] + 237 0000001A EXPORT I2C2_ER_IRQHandler [WEA +K] + 238 0000001A EXPORT SPI1_IRQHandler [WEA +K] + 239 0000001A EXPORT SPI2_IRQHandler [WEA +K] + 240 0000001A EXPORT USART1_IRQHandler [WEA +K] + 241 0000001A EXPORT USART2_IRQHandler [WEA +K] + 242 0000001A EXPORT USART3_IRQHandler [WEA +K] + 243 0000001A EXPORT EXTI15_10_IRQHandler [WEA +K] + 244 0000001A EXPORT RTCAlarm_IRQHandler [WEA +K] + 245 0000001A EXPORT USBWakeUp_IRQHandler [WEA +K] + 246 0000001A EXPORT TIM8_BRK_IRQHandler [WEA +K] + 247 0000001A EXPORT TIM8_UP_IRQHandler [WEA +K] + 248 0000001A EXPORT TIM8_TRG_COM_IRQHandler [WEA +K] + 249 0000001A EXPORT TIM8_CC_IRQHandler [WEA +K] + 250 0000001A EXPORT ADC3_IRQHandler [WEA +K] + 251 0000001A EXPORT FSMC_IRQHandler [WEA +K] + 252 0000001A EXPORT SDIO_IRQHandler [WEA +K] + 253 0000001A EXPORT TIM5_IRQHandler [WEA +K] + 254 0000001A EXPORT SPI3_IRQHandler [WEA +K] + 255 0000001A EXPORT UART4_IRQHandler [WEA +K] + 256 0000001A EXPORT UART5_IRQHandler [WEA +K] + 257 0000001A EXPORT TIM6_IRQHandler [WEA +K] + 258 0000001A EXPORT TIM7_IRQHandler [WEA +K] + 259 0000001A EXPORT DMA2_Channel1_IRQHandler [WEA +K] + 260 0000001A EXPORT DMA2_Channel2_IRQHandler [WEA +K] + 261 0000001A EXPORT DMA2_Channel3_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 8 + + + 262 0000001A EXPORT DMA2_Channel4_5_IRQHandler [WEA +K] + 263 0000001A + 264 0000001A WWDG_IRQHandler + 265 0000001A PVD_IRQHandler + 266 0000001A TAMPER_IRQHandler + 267 0000001A RTC_IRQHandler + 268 0000001A FLASH_IRQHandler + 269 0000001A RCC_IRQHandler + 270 0000001A EXTI0_IRQHandler + 271 0000001A EXTI1_IRQHandler + 272 0000001A EXTI2_IRQHandler + 273 0000001A EXTI3_IRQHandler + 274 0000001A EXTI4_IRQHandler + 275 0000001A DMA1_Channel1_IRQHandler + 276 0000001A DMA1_Channel2_IRQHandler + 277 0000001A DMA1_Channel3_IRQHandler + 278 0000001A DMA1_Channel4_IRQHandler + 279 0000001A DMA1_Channel5_IRQHandler + 280 0000001A DMA1_Channel6_IRQHandler + 281 0000001A DMA1_Channel7_IRQHandler + 282 0000001A ADC1_2_IRQHandler + 283 0000001A USB_HP_CAN1_TX_IRQHandler + 284 0000001A USB_LP_CAN1_RX0_IRQHandler + 285 0000001A CAN1_RX1_IRQHandler + 286 0000001A CAN1_SCE_IRQHandler + 287 0000001A EXTI9_5_IRQHandler + 288 0000001A TIM1_BRK_IRQHandler + 289 0000001A TIM1_UP_IRQHandler + 290 0000001A TIM1_TRG_COM_IRQHandler + 291 0000001A TIM1_CC_IRQHandler + 292 0000001A TIM2_IRQHandler + 293 0000001A TIM3_IRQHandler + 294 0000001A TIM4_IRQHandler + 295 0000001A I2C1_EV_IRQHandler + 296 0000001A I2C1_ER_IRQHandler + 297 0000001A I2C2_EV_IRQHandler + 298 0000001A I2C2_ER_IRQHandler + 299 0000001A SPI1_IRQHandler + 300 0000001A SPI2_IRQHandler + 301 0000001A USART1_IRQHandler + 302 0000001A USART2_IRQHandler + 303 0000001A USART3_IRQHandler + 304 0000001A EXTI15_10_IRQHandler + 305 0000001A RTCAlarm_IRQHandler + 306 0000001A USBWakeUp_IRQHandler + 307 0000001A TIM8_BRK_IRQHandler + 308 0000001A TIM8_UP_IRQHandler + 309 0000001A TIM8_TRG_COM_IRQHandler + 310 0000001A TIM8_CC_IRQHandler + 311 0000001A ADC3_IRQHandler + 312 0000001A FSMC_IRQHandler + 313 0000001A SDIO_IRQHandler + 314 0000001A TIM5_IRQHandler + 315 0000001A SPI3_IRQHandler + 316 0000001A UART4_IRQHandler + 317 0000001A UART5_IRQHandler + 318 0000001A TIM6_IRQHandler + 319 0000001A TIM7_IRQHandler + + + +ARM Macro Assembler Page 9 + + + 320 0000001A DMA2_Channel1_IRQHandler + 321 0000001A DMA2_Channel2_IRQHandler + 322 0000001A DMA2_Channel3_IRQHandler + 323 0000001A DMA2_Channel4_5_IRQHandler + 324 0000001A E7FE B . + 325 0000001C + 326 0000001C ENDP + 327 0000001C + 328 0000001C ALIGN + 329 0000001C + 330 0000001C ;******************************************************* + ************************ + 331 0000001C ; User Stack and Heap initialization + 332 0000001C ;******************************************************* + ************************ + 333 0000001C IF :DEF:__MICROLIB + 334 0000001C + 335 0000001C EXPORT __initial_sp + 336 0000001C EXPORT __heap_base + 337 0000001C EXPORT __heap_limit + 338 0000001C + 339 0000001C ELSE + 354 ENDIF + 355 0000001C + 356 0000001C END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\obj\startup_stm32f10x_hd.d -o.\obj\startup_stm32f10x_hd.o -IE:\s +vn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð +\RVMDK\RTE -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -IC:\Keil_v5\A +RM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include --predefine="__MICROLIB SETA 1" + --predefine="__UVISION_VERSION SETA 518" --predefine="_RTE_ SETA 1" --predefin +e="STM32F10X_HD_VL SETA 1" --list=.\list\startup_stm32f10x_hd.lst ..\Libraries\ +CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 37 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 38 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 39 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + At line 62 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 335 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 47 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 49 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 48 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + At line 336 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s +Comment: __heap_base used once +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 50 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + At line 337 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 57 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 62 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + At line 58 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 142 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +__Vectors_End 00000130 + +Symbol: __Vectors_End + Definitions + At line 140 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 59 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 142 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 144 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + None +Comment: .text unused +ADC1_2_IRQHandler 0000001A + +Symbol: ADC1_2_IRQHandler + Definitions + At line 282 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 98 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 221 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +ADC3_IRQHandler 0000001A + +Symbol: ADC3_IRQHandler + Definitions + At line 311 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 127 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 250 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 174 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 67 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 175 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 285 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 101 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 224 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +CAN1_SCE_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 286 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 102 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 225 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 275 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 91 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 214 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 276 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 92 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 215 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA1_Channel3_IRQHandler 0000001A + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 277 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 93 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 216 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 278 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 94 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 217 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA1_Channel5_IRQHandler 0000001A + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: DMA1_Channel5_IRQHandler + Definitions + At line 279 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 95 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 218 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA1_Channel6_IRQHandler 0000001A + +Symbol: DMA1_Channel6_IRQHandler + Definitions + At line 280 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 96 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 219 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA1_Channel7_IRQHandler 0000001A + +Symbol: DMA1_Channel7_IRQHandler + Definitions + At line 281 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 97 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 220 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA2_Channel1_IRQHandler 0000001A + +Symbol: DMA2_Channel1_IRQHandler + Definitions + At line 320 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 136 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 259 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA2_Channel2_IRQHandler 0000001A + +Symbol: DMA2_Channel2_IRQHandler + Definitions + At line 321 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 137 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 260 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + +DMA2_Channel3_IRQHandler 0000001A + +Symbol: DMA2_Channel3_IRQHandler + Definitions + At line 322 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 138 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 261 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DMA2_Channel4_5_IRQHandler 0000001A + +Symbol: DMA2_Channel4_5_IRQHandler + Definitions + At line 323 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 139 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 262 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 188 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 74 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 189 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 201 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + None +Comment: Default_Handler unused +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 270 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 86 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 209 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +EXTI15_10_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 304 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 120 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 243 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 271 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 87 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 210 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 272 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 88 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 211 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 273 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 89 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 212 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 274 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 90 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 213 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +EXTI9_5_IRQHandler 0000001A + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 287 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 103 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 226 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + At line 268 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 84 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 207 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +FSMC_IRQHandler 0000001A + +Symbol: FSMC_IRQHandler + Definitions + At line 312 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 128 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 251 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 164 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 65 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 165 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 296 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 112 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 235 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 295 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 111 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 234 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +I2C2_ER_IRQHandler 0000001A + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 298 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 114 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 237 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + At line 297 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 113 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 236 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 169 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 66 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 170 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 159 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 64 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 160 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 265 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 81 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 204 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 192 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 76 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 193 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +RCC_IRQHandler 0000001A + +Symbol: RCC_IRQHandler + Definitions + At line 269 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 85 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 208 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +RTCAlarm_IRQHandler 0000001A + +Symbol: RTCAlarm_IRQHandler + Definitions + At line 305 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 121 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 244 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 267 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 83 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 206 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + +rtup\arm\startup_stm32f10x_hd.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 147 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 63 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 148 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +SDIO_IRQHandler 0000001A + +Symbol: SDIO_IRQHandler + Definitions + At line 313 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 129 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 252 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 299 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 115 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 238 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 300 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 116 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 239 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +SPI3_IRQHandler 0000001A + +Symbol: SPI3_IRQHandler + Definitions + At line 315 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 131 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + + At line 254 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 183 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 73 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 184 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 196 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 77 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 197 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 266 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 82 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 205 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM1_BRK_IRQHandler 0000001A + +Symbol: TIM1_BRK_IRQHandler + Definitions + At line 288 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 104 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 227 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 291 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 107 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + +rtup\arm\startup_stm32f10x_hd.s + At line 230 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM1_TRG_COM_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_IRQHandler + Definitions + At line 290 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 106 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 229 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM1_UP_IRQHandler 0000001A + +Symbol: TIM1_UP_IRQHandler + Definitions + At line 289 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 105 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 228 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 292 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 108 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 231 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 293 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 109 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 232 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM4_IRQHandler 0000001A + +Symbol: TIM4_IRQHandler + Definitions + At line 294 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + At line 110 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 233 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM5_IRQHandler 0000001A + +Symbol: TIM5_IRQHandler + Definitions + At line 314 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 130 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 253 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM6_IRQHandler 0000001A + +Symbol: TIM6_IRQHandler + Definitions + At line 318 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 134 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 257 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM7_IRQHandler 0000001A + +Symbol: TIM7_IRQHandler + Definitions + At line 319 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 135 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 258 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM8_BRK_IRQHandler 0000001A + +Symbol: TIM8_BRK_IRQHandler + Definitions + At line 307 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 123 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 246 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM8_CC_IRQHandler 0000001A + +Symbol: TIM8_CC_IRQHandler + Definitions + At line 310 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 13 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 126 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 249 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM8_TRG_COM_IRQHandler 0000001A + +Symbol: TIM8_TRG_COM_IRQHandler + Definitions + At line 309 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 125 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 248 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +TIM8_UP_IRQHandler 0000001A + +Symbol: TIM8_UP_IRQHandler + Definitions + At line 308 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 124 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 247 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + At line 316 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 132 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 255 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +UART5_IRQHandler 0000001A + +Symbol: UART5_IRQHandler + Definitions + At line 317 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 133 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 256 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 301 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta + + + +ARM Macro Assembler Page 14 Alphabetic symbol ordering +Relocatable symbols + +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 117 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 240 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 302 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 118 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 241 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 303 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 119 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 242 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +USBWakeUp_IRQHandler 0000001A + +Symbol: USBWakeUp_IRQHandler + Definitions + At line 306 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 122 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 245 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +USB_HP_CAN1_TX_IRQHandler 0000001A + +Symbol: USB_HP_CAN1_TX_IRQHandler + Definitions + At line 283 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 99 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 222 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +USB_LP_CAN1_RX0_IRQHandler 0000001A + +Symbol: USB_LP_CAN1_RX0_IRQHandler + Definitions + + + +ARM Macro Assembler Page 15 Alphabetic symbol ordering +Relocatable symbols + + At line 284 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 100 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + At line 223 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 179 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 68 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 180 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + Definitions + At line 264 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 80 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + At line 203 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + +72 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 45 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + At line 49 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s +Comment: Heap_Size used once +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 35 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s + Uses + At line 38 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s +Comment: Stack_Size used once +__Vectors_Size 00000130 + +Symbol: __Vectors_Size + Definitions + At line 142 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 60 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\star +tup\arm\startup_stm32f10x_hd.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 150 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s + Uses + At line 151 in file ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\sta +rtup\arm\startup_stm32f10x_hd.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 149 in file 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+:10369000000000000000000000000000000000002A +:1036A00000000000010203040102030406070809E8 +:0836B0000204060800000000FE +:0400000508000131BD +:00000001FF diff --git a/RVMDK/Obj/24r01.crf b/RVMDK/Obj/24r01.crf new file mode 100644 index 0000000..c5e3337 Binary files /dev/null and b/RVMDK/Obj/24r01.crf differ diff --git a/RVMDK/Obj/24r01.d b/RVMDK/Obj/24r01.d new file mode 100644 index 0000000..2cf923a --- /dev/null +++ b/RVMDK/Obj/24r01.d @@ -0,0 +1,31 @@ +.\obj\24r01.o: ..\bsp\24R01.c +.\obj\24r01.o: ..\bsp\24R01.h +.\obj\24r01.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h +.\obj\24r01.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h +.\obj\24r01.o: C:\Program Files (x86)\keil 5\ARM\ARMCC\bin\..\include\stdint.h +.\obj\24r01.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h +.\obj\24r01.o: ..\Libraries\stm32f10x_conf.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h +.\obj\24r01.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h +.\obj\24r01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h diff --git a/RVMDK/Obj/ExtDll.iex b/RVMDK/Obj/ExtDll.iex new file mode 100644 index 0000000..6c0896e --- /dev/null +++ b/RVMDK/Obj/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/RVMDK/Obj/Printf.axf b/RVMDK/Obj/Printf.axf new file mode 100644 index 0000000..ef08e9c Binary files /dev/null and b/RVMDK/Obj/Printf.axf differ diff --git a/RVMDK/Obj/Printf.bin b/RVMDK/Obj/Printf.bin new file mode 100644 index 0000000..a3abaf7 Binary files /dev/null and b/RVMDK/Obj/Printf.bin differ diff --git a/RVMDK/Obj/Printf.build_log.htm b/RVMDK/Obj/Printf.build_log.htm new file mode 100644 index 0000000..c33d056 --- /dev/null +++ b/RVMDK/Obj/Printf.build_log.htm @@ -0,0 +1,73 @@ + + +
+
Vision Build Log

+
Project:

+E:\code\003\д빤\д빤ߣԶдţ\RVMDK\Printf.uvproj
+Project File Date:  06/09/2017
+
+
Output:

+Build target 'CreativeST_VC'
+compiling stm32f10x_tim.c...
+linking...
+Program Size: Code=7752 RO-data=348 RW-data=100 ZI-data=2092  
+FromELF: creating hex file...
+".\Obj\Printf_AUTO.axf" - 0 Error(s), 0 Warning(s).
+
+ + + +.\Obj\Printf_AUTO.axf: Error: L6218E: Undefined symbol TIM_Cmd (referred from tim.o). +.\Obj\Printf_AUTO.axf: Error: L6218E: Undefined symbol TIM_ITConfig (referred from tim.o). +.\Obj\Printf_AUTO.axf: Error: L6218E: Undefined symbol TIM_TimeBaseInit (referred from tim.o). +Not enough information to list image symbols. +Finished: 1 information, 0 warning and 5 error messages. +".\Obj\Printf_AUTO.axf" - 5 Error(s), 0 Warning(s). +Target not created +compiling DataProc.c... +..\bsp\DataProc.c(273): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(buffer,RX_PLOAD_WIDTH); // +..\bsp\DataProc.c(287): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendWrNumOkData,14); //ԣظPC +..\bsp\DataProc.c(592): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendRdNumData,30); //ԣظPC +..\bsp\DataProc.c: 3 warnings, 0 errors +"..\bsp\DataProc.c" - 0 Error(s), 3 Warning(s). +ata,30); //ԣظPC +..\bsp\DataProc.c: 3 warnings, 0 errors +"..\bsp\DataProc.c" - 0 Error(s), 3 Warning(s). +compiling DataProc.c... +..\bsp\DataProc.c(268): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(buffer,RX_PLOAD_WIDTH); // +..\bsp\DataProc.c(281): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendWrNumOkData,14); //ԣظPC +..\bsp\DataProc.c(583): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendRdNumData,30); //ԣظPC +..\bsp\DataProc.c: 3 warnings, 0 errors +"..\bsp\DataProc.c" - 0 Error(s), 3 Warning(s). +compiling tim.c... +"..\bsp\tim.c" - 0 Error(s), 0 Warning(s). +compiling tim.c... +"..\bsp\tim.c" - 0 Error(s), 0 Warning(s). +compiling main.c... +"..\bsp\main.c" - 0 Error(s), 0 Warning(s). +compiling main.c... +"..\bsp\main.c" - 0 Error(s), 0 Warning(s). +compiling DataProc.c... +..\bsp\DataProc.c(271): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(buffer,RX_PLOAD_WIDTH); // +..\bsp\DataProc.c(284): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendWrNumOkData,14); //ԣظPC +..\bsp\DataProc.c(586): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendRdNumData,30); //ԣظPC +..\bsp\DataProc.c: 3 warnings, 0 errors +"..\bsp\DataProc.c" - 0 Error(s), 3 Warning(s). +compiling DataProc.c... +..\bsp\DataProc.c(273): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(buffer,RX_PLOAD_WIDTH); // +..\bsp\DataProc.c(287): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendWrNumOkData,14); //ԣظPC +..\bsp\DataProc.c(592): warning: #167-D: argument of type "u8 *" is incompatible with parameter of type "char *" + SendConsoleData(uartSendRdNumData,30); //ԣظPC +..\bsp\DataProc.c: 3 warnings, 0 errors +"..\bsp\DataProc.c" - 0 Error(s), 3 Warning(s). diff --git a/RVMDK/Obj/Printf.hex b/RVMDK/Obj/Printf.hex new file mode 100644 index 0000000..2f68828 --- /dev/null +++ b/RVMDK/Obj/Printf.hex @@ -0,0 +1,485 @@ +:020000040800F2 +:100000008808002045010008510A0008490A000834 +:100010004D0A00088D010008E71B000800000000E1 +:100020000000000000000000000000008115000832 +:100030002D09000800000000E10F0008E916000883 +:100040005F0100085F0100085F0100085F01000810 +:100050005F0100085F0100085F0100085F01000800 +:100060005F0100085F0100085F0100085F010008F0 +:100070005F0100085F0100085F0100085F010008E0 +:100080005F0100085F0100085F0100085F010008D0 +:100090005F0100085F0100085F0100085F010008C0 +:1000A0005F0100085F0100085F0100085F010008B0 +:1000B0005F0100085F0100085F0100085F010008A0 +:1000C0005F0100085F0100085F0100085F01000890 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+:101DB000201E000860000020280800000C1C0008FD +:101DC0000000000000000000000000000000D1D171 +:101DD000E0D000000000D2D200000000000031324C +:101DE000333435363738393132333435363738399C +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000010203040102C5 +:101E10000304060708090204060800000000000089 +:0400000508000131BD +:00000001FF diff --git a/RVMDK/Obj/Printf.htm b/RVMDK/Obj/Printf.htm new file mode 100644 index 0000000..5cd635e --- /dev/null +++ b/RVMDK/Obj/Printf.htm @@ -0,0 +1,924 @@ + + +Static Call Graph - [.\Obj\Printf.axf] +
+

Static Call Graph for image .\Obj\Printf.axf

+

#<CALLGRAPH># ARM Linker, 5.03 [Build 76]: Last Updated: Thu Jun 15 22:21:19 2017 +

+

Maximum Stack Usage = 112 bytes + Unknown(Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+main ⇒ DataProc_Nrf24l01 ⇒ NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte +

+

+Mutually Recursive functions +

  • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
    + +

    +

    +Function Pointers +

      +
    • ADC1_2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • ADC3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • BusFault_Handler from stm32f10x_it.o(i.BusFault_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • CAN1_RX1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • CAN1_SCE_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel4_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DebugMon_Handler from stm32f10x_it.o(i.DebugMon_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI0_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI15_10_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI9_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • FLASH_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • FSMC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • HardFault_Handler from stm32f10x_it.o(i.HardFault_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C1_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C1_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C2_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C2_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • MemManage_Handler from stm32f10x_it.o(i.MemManage_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • NMI_Handler from stm32f10x_it.o(i.NMI_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • PVD_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • PendSV_Handler from stm32f10x_it.o(i.PendSV_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • RCC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • RTCAlarm_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • RTC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • Reset_Handler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SDIO_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SPI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SPI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SPI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SVC_Handler from stm32f10x_it.o(i.SVC_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • SysTick_Handler from stm32f10x_it.o(i.SysTick_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_hd.o(.text) +
    • TAMPER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • UART4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • UART5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • USART1_IRQHandler from printf.o(i.USART1_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • USART2_IRQHandler from usart2.o(i.USART2_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • USART3_IRQHandler from printf.o(i.USART3_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • USBWakeUp_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • UsageFault_Handler from stm32f10x_it.o(i.UsageFault_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • WWDG_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_hd.o(.text) +
    • fputc from printf.o(i.fputc) referenced from printfb.o(i.__0printf$bare) +
    • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(.text) +
    +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) + +

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Calls]

    • >>   __scatterload +
    + +

    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Called By]

    • >>   __scatterload +
    + +

    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) + +

    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) + +

    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) + +

    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D)) + +

    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F)) + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +

    [Calls]

    • >>   ADC1_2_IRQHandler +
    +
    [Called By]
    • >>   ADC1_2_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    ADC3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel4_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    FSMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) +

    [Calls]

    • >>   __main_after_scatterload +
    +
    [Called By]
    • >>   _main_scatterload +
    + +

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) + +

    BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.BusFault_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    CheckSum (Thumb, 36 bytes, Stack size 8 bytes, dataproc.o(i.CheckSum)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = CheckSum +
    +
    [Called By]
    • >>   DataProc_Nrf24l01 +
    + +

    DataProc_1356 (Thumb, 216 bytes, Stack size 8 bytes, dataproc.o(i.DataProc_1356)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = DataProc_1356 ⇒ delay_ms +
    +
    [Calls]
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    • >>   delay_ms +
    +
    [Called By]
    • >>   main +
    + +

    DataProc_Nrf24l01 (Thumb, 288 bytes, Stack size 40 bytes, dataproc.o(i.DataProc_Nrf24l01)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = DataProc_Nrf24l01 ⇒ NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   CheckSum +
    • >>   NRF24L01_Write_Reg +
    • >>   NRF24L01_Write_Buf +
    • >>   NRF24L01_RxPacket +
    • >>   NRF24L01_RX_Mode +
    • >>   SendConsoleData +
    • >>   SendConsoleByte +
    +
    [Called By]
    • >>   main +
    + +

    DataProc_USART1 (Thumb, 834 bytes, Stack size 8 bytes, dataproc.o(i.DataProc_USART1)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = DataProc_USART1 ⇒ SendConsoleData ⇒ SendUartData ⇒ SendUartByte +
    +
    [Calls]
    • >>   SendConsoleData +
    • >>   __2printf +
    +
    [Called By]
    • >>   main +
    + +

    Data_Init (Thumb, 240 bytes, Stack size 0 bytes, dataproc.o(i.Data_Init)) +

    [Called By]

    • >>   main +
    + +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.DebugMon_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    GPIO_Init (Thumb, 274 bytes, Stack size 24 bytes, stm32f10x_gpio.o(i.GPIO_Init)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = GPIO_Init +
    +
    [Called By]
    • >>   SPI2_Init +
    • >>   SPI1_Init +
    • >>   led_init +
    • >>   USART_Configuration +
    • >>   USART2_Init +
    • >>   NRF24L01_Init +
    + +

    GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ResetBits)) +

    [Called By]

    • >>   led_init +
    • >>   DataProc_1356 +
    + +

    GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_SetBits)) +

    [Called By]

    • >>   SPI2_Init +
    • >>   SPI1_Init +
    • >>   led_init +
    • >>   NRF24L01_Init +
    • >>   DataProc_1356 +
    + +

    HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.HardFault_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.MemManage_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.NMI_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    NRF24L01_Check (Thumb, 80 bytes, Stack size 24 bytes, nrf24l01.o(i.NRF24L01_Check)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = NRF24L01_Check ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   SPI_SetSpeed +
    • >>   NRF24L01_Write_Buf +
    • >>   NRF24L01_Read_Buf +
    +
    [Called By]
    • >>   main +
    + +

    NRF24L01_Init (Thumb, 228 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_Init)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = NRF24L01_Init ⇒ SPI2_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   SPI2_Init +
    • >>   SPI1_Init +
    • >>   GPIO_SetBits +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    +
    [Called By]
    • >>   main +
    + +

    NRF24L01_RX_Mode (Thumb, 166 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_Mode)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = NRF24L01_RX_Mode ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   NRF24L01_Write_Reg +
    • >>   NRF24L01_Write_Buf +
    +
    [Called By]
    • >>   DataProc_Nrf24l01 +
    + +

    NRF24L01_Read_Buf (Thumb, 114 bytes, Stack size 32 bytes, nrf24l01.o(i.NRF24L01_Read_Buf)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   SPI_ReadWriteByte +
    +
    [Called By]
    • >>   NRF24L01_RxPacket +
    • >>   NRF24L01_Check +
    + +

    NRF24L01_Read_Reg (Thumb, 78 bytes, Stack size 16 bytes, nrf24l01.o(i.NRF24L01_Read_Reg)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = NRF24L01_Read_Reg ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   SPI_ReadWriteByte +
    +
    [Called By]
    • >>   NRF24L01_RxPacket +
    + +

    NRF24L01_RxPacket (Thumb, 66 bytes, Stack size 16 bytes, nrf24l01.o(i.NRF24L01_RxPacket)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   SPI_SetSpeed +
    • >>   NRF24L01_Write_Reg +
    • >>   NRF24L01_Read_Reg +
    • >>   NRF24L01_Read_Buf +
    +
    [Called By]
    • >>   DataProc_Nrf24l01 +
    + +

    NRF24L01_TX_Mode (Thumb, 136 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_TX_Mode)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = NRF24L01_TX_Mode ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   NRF24L01_Write_Reg +
    • >>   NRF24L01_Write_Buf +
    +
    [Called By]
    • >>   main +
    + +

    NRF24L01_Write_Buf (Thumb, 114 bytes, Stack size 32 bytes, nrf24l01.o(i.NRF24L01_Write_Buf)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   SPI_ReadWriteByte +
    +
    [Called By]
    • >>   NRF24L01_RX_Mode +
    • >>   NRF24L01_TX_Mode +
    • >>   NRF24L01_Check +
    • >>   DataProc_Nrf24l01 +
    + +

    NRF24L01_Write_Reg (Thumb, 84 bytes, Stack size 24 bytes, nrf24l01.o(i.NRF24L01_Write_Reg)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = NRF24L01_Write_Reg ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   SPI_ReadWriteByte +
    +
    [Called By]
    • >>   NRF24L01_RxPacket +
    • >>   NRF24L01_RX_Mode +
    • >>   NRF24L01_TX_Mode +
    • >>   DataProc_Nrf24l01 +
    + +

    NVIC_Configuration (Thumb, 96 bytes, Stack size 8 bytes, main.o(i.NVIC_Configuration)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = NVIC_Configuration ⇒ NVIC_Init +
    +
    [Calls]
    • >>   NVIC_PriorityGroupConfig +
    • >>   NVIC_Init +
    +
    [Called By]
    • >>   main +
    + +

    NVIC_Init (Thumb, 102 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = NVIC_Init +
    +
    [Called By]
    • >>   NVIC_Configuration +
    + +

    NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig)) +

    [Called By]

    • >>   NVIC_Configuration +
    + +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.PendSV_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd)) +

    [Called By]

    • >>   SPI2_Init +
    • >>   USART_Configuration +
    • >>   USART2_Init +
    • >>   RCC_Configuration +
    + +

    RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)) +

    [Called By]

    • >>   SPI2_Init +
    • >>   SPI1_Init +
    • >>   led_init +
    • >>   USART_Configuration +
    • >>   USART2_Init +
    • >>   NRF24L01_Init +
    • >>   RCC_Configuration +
    + +

    RCC_Configuration (Thumb, 106 bytes, Stack size 8 bytes, main.o(i.RCC_Configuration)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = RCC_Configuration ⇒ RCC_WaitForHSEStartUp ⇒ RCC_GetFlagStatus +
    +
    [Calls]
    • >>   RCC_WaitForHSEStartUp +
    • >>   RCC_SYSCLKConfig +
    • >>   RCC_PLLConfig +
    • >>   RCC_PLLCmd +
    • >>   RCC_PCLK2Config +
    • >>   RCC_PCLK1Config +
    • >>   RCC_HSEConfig +
    • >>   RCC_HCLKConfig +
    • >>   RCC_GetSYSCLKSource +
    • >>   RCC_GetFlagStatus +
    • >>   RCC_DeInit +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   RCC_APB1PeriphClockCmd +
    +
    [Called By]
    • >>   main +
    + +

    RCC_DeInit (Thumb, 64 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_DeInit)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_GetClocksFreq (Thumb, 192 bytes, Stack size 12 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = RCC_GetClocksFreq +
    +
    [Called By]
    • >>   USART_Init +
    + +

    RCC_GetFlagStatus (Thumb, 56 bytes, Stack size 8 bytes, stm32f10x_rcc.o(i.RCC_GetFlagStatus)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = RCC_GetFlagStatus +
    +
    [Called By]
    • >>   RCC_WaitForHSEStartUp +
    • >>   RCC_Configuration +
    + +

    RCC_GetSYSCLKSource (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_GetSYSCLKSource)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_HCLKConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_HCLKConfig)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_HSEConfig (Thumb, 70 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_HSEConfig)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_PCLK1Config (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PCLK1Config)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_PCLK2Config (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PCLK2Config)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_PLLCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PLLCmd)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_PLLConfig (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PLLConfig)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_SYSCLKConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_SYSCLKConfig)) +

    [Called By]

    • >>   RCC_Configuration +
    + +

    RCC_WaitForHSEStartUp (Thumb, 56 bytes, Stack size 16 bytes, stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = RCC_WaitForHSEStartUp ⇒ RCC_GetFlagStatus +
    +
    [Calls]
    • >>   RCC_GetFlagStatus +
    +
    [Called By]
    • >>   RCC_Configuration +
    + +

    SPI1_Init (Thumb, 122 bytes, Stack size 32 bytes, spi.o(i.SPI1_Init)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = SPI1_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   SPI_Init +
    • >>   SPI_Cmd +
    • >>   GPIO_SetBits +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    +
    [Called By]
    • >>   NRF24L01_Init +
    + +

    SPI2_Init (Thumb, 132 bytes, Stack size 32 bytes, spi.o(i.SPI2_Init)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = SPI2_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   SPI_Init +
    • >>   SPI_Cmd +
    • >>   GPIO_SetBits +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   RCC_APB1PeriphClockCmd +
    +
    [Called By]
    • >>   NRF24L01_Init +
    + +

    SPI_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_Cmd)) +

    [Called By]

    • >>   SPI_SetSpeed +
    • >>   SPI2_Init +
    • >>   SPI1_Init +
    + +

    SPI_I2S_GetFlagStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus)) +

    [Called By]

    • >>   SPI_ReadWriteByte +
    + +

    SPI_I2S_ReceiveData (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_ReceiveData)) +

    [Called By]

    • >>   SPI_ReadWriteByte +
    + +

    SPI_I2S_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_SendData)) +

    [Called By]

    • >>   SPI_ReadWriteByte +
    + +

    SPI_Init (Thumb, 60 bytes, Stack size 8 bytes, stm32f10x_spi.o(i.SPI_Init)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = SPI_Init +
    +
    [Called By]
    • >>   SPI2_Init +
    • >>   SPI1_Init +
    + +

    SPI_ReadWriteByte (Thumb, 158 bytes, Stack size 24 bytes, spi.o(i.SPI_ReadWriteByte)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = SPI_ReadWriteByte +
    +
    [Calls]
    • >>   SPI_I2S_SendData +
    • >>   SPI_I2S_ReceiveData +
    • >>   SPI_I2S_GetFlagStatus +
    +
    [Called By]
    • >>   NRF24L01_Write_Reg +
    • >>   NRF24L01_Write_Buf +
    • >>   NRF24L01_Read_Reg +
    • >>   NRF24L01_Read_Buf +
    + +

    SPI_SetSpeed (Thumb, 72 bytes, Stack size 16 bytes, spi.o(i.SPI_SetSpeed)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SPI_SetSpeed +
    +
    [Calls]
    • >>   SPI_Cmd +
    +
    [Called By]
    • >>   NRF24L01_RxPacket +
    • >>   NRF24L01_Check +
    + +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SVC_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SendConsoleByte (Thumb, 14 bytes, Stack size 8 bytes, printf.o(i.SendConsoleByte)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = SendConsoleByte ⇒ SendUartByte +
    +
    [Calls]
    • >>   SendUartByte +
    +
    [Called By]
    • >>   DataProc_Nrf24l01 +
    + +

    SendConsoleData (Thumb, 18 bytes, Stack size 16 bytes, printf.o(i.SendConsoleData)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = SendConsoleData ⇒ SendUartData ⇒ SendUartByte +
    +
    [Calls]
    • >>   SendUartData +
    +
    [Called By]
    • >>   DataProc_USART1 +
    • >>   DataProc_Nrf24l01 +
    + +

    SendUartByte (Thumb, 32 bytes, Stack size 16 bytes, printf.o(i.SendUartByte)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SendUartByte +
    +
    [Calls]
    • >>   USART_SendData +
    • >>   USART_GetFlagStatus +
    +
    [Called By]
    • >>   SendUartData +
    • >>   SendConsoleByte +
    + +

    SendUartData (Thumb, 50 bytes, Stack size 24 bytes, printf.o(i.SendUartData)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = SendUartData ⇒ SendUartByte +
    +
    [Calls]
    • >>   SendUartByte +
    +
    [Called By]
    • >>   SendConsoleData +
    + +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SysTick_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72 +
    +
    [Calls]
    • >>   SetSysClock +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(.text) +
    +

    USART1_IRQHandler (Thumb, 60 bytes, Stack size 8 bytes, printf.o(i.USART1_IRQHandler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART1_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_SendData +
    • >>   USART_ReceiveData +
    • >>   USART_GetITStatus +
    • >>   USART_ClearITPendingBit +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 78 bytes, Stack size 8 bytes, usart2.o(i.USART2_IRQHandler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART2_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_ReceiveData +
    • >>   USART_GetITStatus +
    • >>   USART_GetFlagStatus +
    • >>   USART_ClearITPendingBit +
    • >>   USART_ClearFlag +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    USART2_Init (Thumb, 126 bytes, Stack size 32 bytes, usart2.o(i.USART2_Init)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = USART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   RCC_APB1PeriphClockCmd +
    +
    [Called By]
    • >>   main +
    + +

    USART3_IRQHandler (Thumb, 88 bytes, Stack size 8 bytes, printf.o(i.USART3_IRQHandler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART3_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_ReceiveData +
    • >>   USART_GetITStatus +
    • >>   USART_GetFlagStatus +
    • >>   USART_ClearITPendingBit +
    • >>   USART_ClearFlag +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    USART_ClearFlag (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ClearFlag)) +

    [Called By]

    • >>   USART2_IRQHandler +
    • >>   USART3_IRQHandler +
    • >>   USART_Configuration +
    + +

    USART_ClearITPendingBit (Thumb, 30 bytes, Stack size 8 bytes, stm32f10x_usart.o(i.USART_ClearITPendingBit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = USART_ClearITPendingBit +
    +
    [Called By]
    • >>   USART2_IRQHandler +
    • >>   USART3_IRQHandler +
    • >>   USART1_IRQHandler +
    + +

    USART_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_Cmd)) +

    [Called By]

    • >>   USART_Configuration +
    • >>   USART2_Init +
    + +

    USART_Configuration (Thumb, 266 bytes, Stack size 24 bytes, printf.o(i.USART_Configuration)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = USART_Configuration ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   USART_ClearFlag +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   RCC_APB1PeriphClockCmd +
    +
    [Called By]
    • >>   main +
    + +

    USART_GetFlagStatus (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_GetFlagStatus)) +

    [Called By]

    • >>   USART2_IRQHandler +
    • >>   fputc +
    • >>   USART3_IRQHandler +
    • >>   SendUartByte +
    + +

    USART_GetITStatus (Thumb, 84 bytes, Stack size 16 bytes, stm32f10x_usart.o(i.USART_GetITStatus)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = USART_GetITStatus +
    +
    [Called By]
    • >>   USART2_IRQHandler +
    • >>   USART3_IRQHandler +
    • >>   USART1_IRQHandler +
    + +

    USART_ITConfig (Thumb, 74 bytes, Stack size 20 bytes, stm32f10x_usart.o(i.USART_ITConfig)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = USART_ITConfig +
    +
    [Called By]
    • >>   USART_Configuration +
    • >>   USART2_Init +
    + +

    USART_Init (Thumb, 210 bytes, Stack size 56 bytes, stm32f10x_usart.o(i.USART_Init)) +

    [Stack]

    • Max Depth = 68
    • Call Chain = USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   RCC_GetClocksFreq +
    +
    [Called By]
    • >>   USART_Configuration +
    • >>   USART2_Init +
    + +

    USART_ReceiveData (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ReceiveData)) +

    [Called By]

    • >>   USART2_IRQHandler +
    • >>   USART3_IRQHandler +
    • >>   USART1_IRQHandler +
    + +

    USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_SendData)) +

    [Called By]

    • >>   USART1_IRQHandler +
    • >>   SendUartByte +
    + +

    UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.UsageFault_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    __0printf$bare (Thumb, 8 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare), UNUSED) +

    [Calls]

    • >>   _printf_core +
    + +

    __1printf$bare (Thumb, 0 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare), UNUSED) + +

    __2printf (Thumb, 0 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare)) +

    [Called By]

    • >>   DataProc_USART1 +
    • >>   main +
    + +

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) + +

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) + +

    delay_ms (Thumb, 42 bytes, Stack size 8 bytes, delay.o(i.delay_ms)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = delay_ms +
    +
    [Called By]
    • >>   DataProc_1356 +
    • >>   main +
    + +

    fputc (Thumb, 32 bytes, Stack size 16 bytes, printf.o(i.fputc)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = fputc +
    +
    [Calls]
    • >>   USART_GetFlagStatus +
    +
    [Address Reference Count : 1]
    • printfb.o(i.__0printf$bare) +
    +

    led_init (Thumb, 84 bytes, Stack size 8 bytes, led.o(i.led_init)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = led_init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    +
    [Called By]
    • >>   main +
    + +

    main (Thumb, 132 bytes, Stack size 0 bytes, main.o(i.main)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = main ⇒ DataProc_Nrf24l01 ⇒ NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte +
    +
    [Calls]
    • >>   led_init +
    • >>   delay_ms +
    • >>   USART_Configuration +
    • >>   USART2_Init +
    • >>   NRF24L01_TX_Mode +
    • >>   NRF24L01_Init +
    • >>   NRF24L01_Check +
    • >>   Data_Init +
    • >>   DataProc_USART1 +
    • >>   DataProc_Nrf24l01 +
    • >>   DataProc_1356 +
    • >>   RCC_Configuration +
    • >>   NVIC_Configuration +
    • >>   __2printf +
    +
    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B) +

    +

    +Local Symbols +

    +

    SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = SetSysClock ⇒ SetSysClockTo72 +
    +
    [Calls]
    • >>   SetSysClockTo72 +
    +
    [Called By]
    • >>   SystemInit +
    + +

    SetSysClockTo72 (Thumb, 212 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = SetSysClockTo72 +
    +
    [Called By]
    • >>   SetSysClock +
    + +

    _printf_core (Thumb, 34 bytes, Stack size 24 bytes, printfb.o(i._printf_core), UNUSED) +

    [Called By]

    • >>   __0printf$bare +
    +

    +

    +Undefined Global Symbols +

    diff --git a/RVMDK/Obj/Printf.lnp b/RVMDK/Obj/Printf.lnp new file mode 100644 index 0000000..eab581f --- /dev/null +++ b/RVMDK/Obj/Printf.lnp @@ -0,0 +1,22 @@ +--cpu Cortex-M3 +".\obj\main.o" +".\obj\printf.o" +".\obj\delay.o" +".\obj\led.o" +".\obj\usart2.o" +".\obj\nrf24l01.o" +".\obj\spi.o" +".\obj\dataproc.o" +".\obj\stm32f10x_it.o" +".\obj\stm32f10x_rcc.o" +".\obj\stm32f10x_usart.o" +".\obj\misc.o" +".\obj\stm32f10x_gpio.o" +".\obj\stm32f10x_spi.o" +".\obj\core_cm3.o" +".\obj\system_stm32f10x.o" +".\obj\startup_stm32f10x_hd.o" +--library_type=microlib --strict --scatter ".\Obj\Printf.sct" +--summary_stderr --info summarysizes --map --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\List\Printf.map" -o .\Obj\Printf.axf \ No newline at end of file diff --git a/RVMDK/Obj/Printf.plg b/RVMDK/Obj/Printf.plg new file mode 100644 index 0000000..bff2d19 --- /dev/null +++ b/RVMDK/Obj/Printf.plg @@ -0,0 +1,10 @@ + + +
    +
    Vision Build Log
    
+
    Project:
    
+E:\code\003\д\RVMDK\Printf.uvproj
+Project File Date:  06/08/2017
+
+
    Output:
    
+Load "E:\\code\\003\\д\\RVMDK\\Obj\\Printf.AXF" 
diff --git a/RVMDK/Obj/Printf.sct b/RVMDK/Obj/Printf.sct
new file mode 100644
index 0000000..fd82337
--- /dev/null
+++ b/RVMDK/Obj/Printf.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x0000C000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/RVMDK/Obj/Printf.tra b/RVMDK/Obj/Printf.tra
new file mode 100644
index 0000000..168b28c
--- /dev/null
+++ b/RVMDK/Obj/Printf.tra
@@ -0,0 +1,28 @@
+*** Creating Trace Output File '.\Obj\Printf.tra' Ok.
+### Preparing for ADS-LD.
+### Creating ADS-LD Command Line
+### List of Objects: adding '".\obj\stm32f10x_it.o"'
+### List of Objects: adding '".\obj\main.o"'
+### List of Objects: adding '".\obj\printf.o"'
+### List of Objects: adding '".\obj\stm32f10x_rcc.o"'
+### List of Objects: adding '".\obj\stm32f10x_usart.o"'
+### List of Objects: adding '".\obj\misc.o"'
+### List of Objects: adding '".\obj\stm32f10x_gpio.o"'
+### List of Objects: adding '".\obj\system_stm32f10x.o"'
+### List of Objects: adding '".\obj\core_cm3.o"'
+### List of Objects: adding '".\obj\startup_stm32f10x_hd.o"'
+### ADS-LD Command completed:
+--cpu Cortex-M3 ".\obj\stm32f10x_it.o" ".\obj\main.o" ".\obj\printf.o" ".\obj\stm32f10x_rcc.o" ".\obj\stm32f10x_usart.o" ".\obj\misc.o" ".\obj\stm32f10x_gpio.o" ".\obj\system_stm32f10x.o" ".\obj\core_cm3.o" ".\obj\startup_stm32f10x_hd.o" --library_type=microlib --strict --scatter ".\Obj\Printf.sct" 

+--autoat --summary_stderr --info summarysizes --map --xref --callgraph --symbols 

+--info sizes --info totals --info unused --info veneers 

+ --list ".\List\Printf.map" -o ".\Obj\Printf.axf"### Preparing Environment (PrepEnvAds)
+### ADS-LD Output File: '.\Obj\Printf.axf'
+### ADS-LD Command File: '.\Obj\Printf.lnp'
+### Checking for dirty Components...
+### Creating CmdFile '.\Obj\Printf.lnp', Handle=0x00000158
+### Writing '.lnp' file
+### ADS-LD Command file '.\Obj\Printf.lnp' is ready.
+### ADS-LD: About to start ADS-LD Thread.
+### ADS-LD: executed with 0 errors
+### Updating obj list
+### LDADS_file() completed.
diff --git a/RVMDK/Obj/Printf_AUTO.axf b/RVMDK/Obj/Printf_AUTO.axf
new file mode 100644
index 0000000..319749d
Binary files /dev/null and b/RVMDK/Obj/Printf_AUTO.axf differ
diff --git a/RVMDK/Obj/Printf_AUTO.build_log.htm b/RVMDK/Obj/Printf_AUTO.build_log.htm
new file mode 100644
index 0000000..db974dd
--- /dev/null
+++ b/RVMDK/Obj/Printf_AUTO.build_log.htm
@@ -0,0 +1,49 @@
+
+
+
    +
    Vision Build Log
    
+
    Project:
    
+E:\code\003\д빤\д빤ߣPCдţ 20170619\д빤ߣPC\RVMDK\Printf.uvproj
+Project File Date:  06/15/2017
+
+
    Output:
    
+Build target 'CreativeST_VC'
+linking...
+Program Size: Code=7692 RO-data=348 RW-data=100 ZI-data=2092  
+FromELF: creating hex file...
+".\Obj\Printf_PC.axf" - 0 Error(s), 0 Warning(s).
+
    
+
+
+a(uartSendWrNumOkData,14);   //ԣظPC
+..\bsp\DataProc.c(313): warning:  #167-D: argument of type "u8 *" is incompatible with parameter of type "char *"
+              SendConsoleData(uartSendWrNumOkData,14);   //ԣظPC
+..\bsp\DataProc.c(606): warning:  #167-D: argument of type "u8 *" is incompatible with parameter of type "char *"
+                      SendConsoleData(uartSendRdNumData,30);   //ԣظPC
+..\bsp\DataProc.c: 3 warnings, 0 errors
+linking...
+Program Size: Code=7692 RO-data=348 RW-data=100 ZI-data=2092  
+FromELF: creating hex file...
+".\Obj\Printf_PC.axf" - 0 Error(s), 3 Warning(s).
+Load "E:\\code\\003\\д빤\\д빤ߣPCдţ 20170619\\д빤ߣPC\\RVMDK\\Obj\\Printf_PC.axf" 
+Erase Done.
+Programming Done.
+Verify OK.
+Application running ...
+Load "E:\\code\\003\\д빤\\д빤ߣPCдţ 20170619\\д빤ߣPC\\RVMDK\\Obj\\Printf_PC.axf" 
+Erase Done.
+Programming Done.
+Verify OK.
+Application running ...
+Load "E:\\code\\003\\д빤\\д빤ߣPCдţ 20170619\\д빤ߣPC\\RVMDK\\Obj\\Printf_PC.axf" 
+Erase Done.
+Programming Done.
+Verify OK.
+Application running ...
+compiling tim.c...
+"..\bsp\tim.c" - 0 Error(s), 0 Warning(s).
+PC
+..\bsp\DataProc.c(605): warning:  #167-D: argument of type "u8 *" is incompatible with parameter of type "char *"
+                      SendConsoleData(uartSendRdNumData,30);   //ԣظPC
+..\bsp\DataProc.c: 4 warnings, 0 errors
+"..\bsp\DataProc.c" - 0 Error(s), 4 Warning(s).
diff --git a/RVMDK/Obj/Printf_AUTO.hex b/RVMDK/Obj/Printf_AUTO.hex
new file mode 100644
index 0000000..0fdc945
--- /dev/null
+++ b/RVMDK/Obj/Printf_AUTO.hex
@@ -0,0 +1,513 @@
+:020000040800F2
+:100000009008002045010008950A00088D0A0008A4
+:10001000910A00088D010008B31D000800000000CF
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diff --git a/RVMDK/Obj/Printf_AUTO.htm b/RVMDK/Obj/Printf_AUTO.htm
new file mode 100644
index 0000000..09b97dd
--- /dev/null
+++ b/RVMDK/Obj/Printf_AUTO.htm
@@ -0,0 +1,964 @@
+
+
+Static Call Graph - [.\Obj\Printf_AUTO.axf]
+
    
+
    Static Call Graph for image .\Obj\Printf_AUTO.axf
    
+
    #<CALLGRAPH># ARM Linker, 5.03 [Build 76]: Last Updated: Mon Jun 19 10:37:48 2017
+
    
+
    Maximum Stack Usage =        112 bytes + Unknown(Cycles, Untraceable Function Pointers)
    
+Call chain for Maximum Stack Depth:
    
+main ⇒ DataProc_Nrf24l01 ⇒ NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    
+Mutually Recursive functions
+
     
  • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
    
+
+
    
+
    
+Function Pointers
+
      
+ 
    • ADC1_2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • ADC3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • BusFault_Handler from stm32f10x_it.o(i.BusFault_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • CAN1_RX1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • CAN1_SCE_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel4_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DebugMon_Handler from stm32f10x_it.o(i.DebugMon_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI0_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI15_10_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI9_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • FLASH_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • FSMC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • HardFault_Handler from stm32f10x_it.o(i.HardFault_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C1_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C1_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C2_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C2_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • MemManage_Handler from stm32f10x_it.o(i.MemManage_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • NMI_Handler from stm32f10x_it.o(i.NMI_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • PVD_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • PendSV_Handler from stm32f10x_it.o(i.PendSV_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • RCC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • RTCAlarm_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • RTC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • Reset_Handler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SDIO_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SPI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SPI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SPI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SVC_Handler from stm32f10x_it.o(i.SVC_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SysTick_Handler from stm32f10x_it.o(i.SysTick_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_hd.o(.text)
+ 
    • TAMPER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM3_IRQHandler from dataproc.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • UART4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • UART5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USART1_IRQHandler from printf.o(i.USART1_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USART2_IRQHandler from usart2.o(i.USART2_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USART3_IRQHandler from printf.o(i.USART3_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USBWakeUp_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • UsageFault_Handler from stm32f10x_it.o(i.UsageFault_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • WWDG_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_hd.o(.text)
+ 
    • fputc from printf.o(i.fputc) referenced from printfb.o(i.__0printf$bare)
+ 
    • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
+
    
+
    
+
    
+Global Symbols
+
    
+
    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(.text)
+
    
+
    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
+
+
    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+

    [Calls]
    • >>   __scatterload
+
    
+
+
    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+

    [Called By]
    • >>   __scatterload
+
    
+
+
    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
+
+
    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
+
+
    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
+
+
    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
+
+
    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
+
+
    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+

    [Calls]
    • >>   ADC1_2_IRQHandler
+
    
+
    [Called By]
    • >>   ADC1_2_IRQHandler
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    ADC3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel4_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    FSMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
+

    [Calls]
    • >>   __main_after_scatterload
+
    
+
    [Called By]
    • >>   _main_scatterload
+
    
+
+
    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
+
+
    BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.BusFault_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    CheckSum (Thumb, 36 bytes, Stack size 8 bytes, dataproc.o(i.CheckSum))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = CheckSum
+
    
+
    [Called By]
    • >>   DataProc_Nrf24l01
+
    
+
+
    DataProc_1356 (Thumb, 210 bytes, Stack size 8 bytes, dataproc.o(i.DataProc_1356))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = DataProc_1356 ⇒ delay_ms
+
    
+
    [Calls]
    • >>   GPIO_SetBits
+
    • >>   GPIO_ResetBits
+
    • >>   delay_ms
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    DataProc_Nrf24l01 (Thumb, 352 bytes, Stack size 40 bytes, dataproc.o(i.DataProc_Nrf24l01))
+

    [Stack]
    • Max Depth = 112
    • Call Chain = DataProc_Nrf24l01 ⇒ NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   CheckSum
+
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_RX_Mode
+
    • >>   SendConsoleData
+
    • >>   SendConsoleByte
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    DataProc_USART1 (Thumb, 838 bytes, Stack size 8 bytes, dataproc.o(i.DataProc_USART1))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = DataProc_USART1 ⇒ SendConsoleData ⇒ SendUartData ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendConsoleData
+
    • >>   __2printf
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    Data_Init (Thumb, 240 bytes, Stack size 0 bytes, dataproc.o(i.Data_Init))
+

    [Called By]
    • >>   main
+
    
+
+
    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.DebugMon_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    GPIO_Init (Thumb, 274 bytes, Stack size 24 bytes, stm32f10x_gpio.o(i.GPIO_Init))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = GPIO_Init
+
    
+
    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   led_init
+
    • >>   USART_Configuration
+
    • >>   USART2_Init
+
    • >>   NRF24L01_Init
+
    
+
+
    GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ResetBits))
+

    [Called By]
    • >>   led_init
+
    • >>   DataProc_1356
+
    
+
+
    GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_SetBits))
+

    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   led_init
+
    • >>   NRF24L01_Init
+
    • >>   DataProc_1356
+
    
+
+
    HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.HardFault_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.MemManage_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.NMI_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    NRF24L01_Check (Thumb, 80 bytes, Stack size 24 bytes, nrf24l01.o(i.NRF24L01_Check))
+

    [Stack]
    • Max Depth = 80
    • Call Chain = NRF24L01_Check ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_SetSpeed
+
    • >>   NRF24L01_Write_Buf
+
    • >>   NRF24L01_Read_Buf
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    NRF24L01_Init (Thumb, 228 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_Init))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_Init ⇒ SPI2_Init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   GPIO_SetBits
+
    • >>   GPIO_Init
+
    • >>   RCC_APB2PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    NRF24L01_RX_Mode (Thumb, 166 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_Mode))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_Mode ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   DataProc_Nrf24l01
+
    
+
+
    NRF24L01_Read_Buf (Thumb, 114 bytes, Stack size 32 bytes, nrf24l01.o(i.NRF24L01_Read_Buf))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_Check
+
    
+
+
    NRF24L01_Read_Reg (Thumb, 78 bytes, Stack size 16 bytes, nrf24l01.o(i.NRF24L01_Read_Reg))
+

    [Stack]
    • Max Depth = 40
    • Call Chain = NRF24L01_Read_Reg ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   NRF24L01_RxPacket
+
    
+
+
    NRF24L01_RxPacket (Thumb, 66 bytes, Stack size 16 bytes, nrf24l01.o(i.NRF24L01_RxPacket))
+

    [Stack]
    • Max Depth = 72
    • Call Chain = NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_SetSpeed
+
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Read_Reg
+
    • >>   NRF24L01_Read_Buf
+
    
+
    [Called By]
    • >>   DataProc_Nrf24l01
+
    
+
+
    NRF24L01_TX_Mode (Thumb, 136 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_TX_Mode))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_TX_Mode ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    NRF24L01_Write_Buf (Thumb, 114 bytes, Stack size 32 bytes, nrf24l01.o(i.NRF24L01_Write_Buf))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode
+
    • >>   NRF24L01_TX_Mode
+
    • >>   NRF24L01_Check
+
    • >>   DataProc_Nrf24l01
+
    
+
+
    NRF24L01_Write_Reg (Thumb, 84 bytes, Stack size 24 bytes, nrf24l01.o(i.NRF24L01_Write_Reg))
+

    [Stack]
    • Max Depth = 48
    • Call Chain = NRF24L01_Write_Reg ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_RX_Mode
+
    • >>   NRF24L01_TX_Mode
+
    • >>   DataProc_Nrf24l01
+
    
+
+
    NVIC_Configuration (Thumb, 124 bytes, Stack size 8 bytes, main.o(i.NVIC_Configuration))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = NVIC_Configuration ⇒ NVIC_Init
+
    
+
    [Calls]
    • >>   NVIC_PriorityGroupConfig
+
    • >>   NVIC_Init
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    NVIC_Init (Thumb, 102 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = NVIC_Init
+
    
+
    [Called By]
    • >>   NVIC_Configuration
+
    
+
+
    NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig))
+

    [Called By]
    • >>   NVIC_Configuration
+
    
+
+
    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.PendSV_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd))
+

    [Called By]
    • >>   SPI2_Init
+
    • >>   USART_Configuration
+
    • >>   USART2_Init
+
    • >>   TIM3_Int_Init
+
    • >>   RCC_Configuration
+
    
+
+
    RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd))
+

    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   led_init
+
    • >>   USART_Configuration
+
    • >>   USART2_Init
+
    • >>   NRF24L01_Init
+
    • >>   RCC_Configuration
+
    
+
+
    RCC_Configuration (Thumb, 106 bytes, Stack size 8 bytes, main.o(i.RCC_Configuration))
+

    [Stack]
    • Max Depth = 32
    • Call Chain = RCC_Configuration ⇒ RCC_WaitForHSEStartUp ⇒ RCC_GetFlagStatus
+
    
+
    [Calls]
    • >>   RCC_WaitForHSEStartUp
+
    • >>   RCC_SYSCLKConfig
+
    • >>   RCC_PLLConfig
+
    • >>   RCC_PLLCmd
+
    • >>   RCC_PCLK2Config
+
    • >>   RCC_PCLK1Config
+
    • >>   RCC_HSEConfig
+
    • >>   RCC_HCLKConfig
+
    • >>   RCC_GetSYSCLKSource
+
    • >>   RCC_GetFlagStatus
+
    • >>   RCC_DeInit
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    RCC_DeInit (Thumb, 64 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_DeInit))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_GetClocksFreq (Thumb, 192 bytes, Stack size 12 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq))
+

    [Stack]
    • Max Depth = 12
    • Call Chain = RCC_GetClocksFreq
+
    
+
    [Called By]
    • >>   USART_Init
+
    
+
+
    RCC_GetFlagStatus (Thumb, 56 bytes, Stack size 8 bytes, stm32f10x_rcc.o(i.RCC_GetFlagStatus))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = RCC_GetFlagStatus
+
    
+
    [Called By]
    • >>   RCC_WaitForHSEStartUp
+
    • >>   RCC_Configuration
+
    
+
+
    RCC_GetSYSCLKSource (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_GetSYSCLKSource))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_HCLKConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_HCLKConfig))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_HSEConfig (Thumb, 70 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_HSEConfig))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_PCLK1Config (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PCLK1Config))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_PCLK2Config (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PCLK2Config))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_PLLCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PLLCmd))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_PLLConfig (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PLLConfig))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_SYSCLKConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_SYSCLKConfig))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    RCC_WaitForHSEStartUp (Thumb, 56 bytes, Stack size 16 bytes, stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = RCC_WaitForHSEStartUp ⇒ RCC_GetFlagStatus
+
    
+
    [Calls]
    • >>   RCC_GetFlagStatus
+
    
+
    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    SPI1_Init (Thumb, 122 bytes, Stack size 32 bytes, spi.o(i.SPI1_Init))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = SPI1_Init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   SPI_Init
+
    • >>   SPI_Cmd
+
    • >>   GPIO_SetBits
+
    • >>   GPIO_Init
+
    • >>   RCC_APB2PeriphClockCmd
+
    
+
    [Called By]
    • >>   NRF24L01_Init
+
    
+
+
    SPI2_Init (Thumb, 132 bytes, Stack size 32 bytes, spi.o(i.SPI2_Init))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = SPI2_Init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   SPI_Init
+
    • >>   SPI_Cmd
+
    • >>   GPIO_SetBits
+
    • >>   GPIO_Init
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    
+
    [Called By]
    • >>   NRF24L01_Init
+
    
+
+
    SPI_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_Cmd))
+

    [Called By]
    • >>   SPI_SetSpeed
+
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    
+
+
    SPI_I2S_GetFlagStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus))
+

    [Called By]
    • >>   SPI_ReadWriteByte
+
    
+
+
    SPI_I2S_ReceiveData (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_ReceiveData))
+

    [Called By]
    • >>   SPI_ReadWriteByte
+
    
+
+
    SPI_I2S_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_SendData))
+

    [Called By]
    • >>   SPI_ReadWriteByte
+
    
+
+
    SPI_Init (Thumb, 60 bytes, Stack size 8 bytes, stm32f10x_spi.o(i.SPI_Init))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = SPI_Init
+
    
+
    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    
+
+
    SPI_ReadWriteByte (Thumb, 158 bytes, Stack size 24 bytes, spi.o(i.SPI_ReadWriteByte))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_I2S_SendData
+
    • >>   SPI_I2S_ReceiveData
+
    • >>   SPI_I2S_GetFlagStatus
+
    
+
    [Called By]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    • >>   NRF24L01_Read_Reg
+
    • >>   NRF24L01_Read_Buf
+
    
+
+
    SPI_SetSpeed (Thumb, 72 bytes, Stack size 16 bytes, spi.o(i.SPI_SetSpeed))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = SPI_SetSpeed
+
    
+
    [Calls]
    • >>   SPI_Cmd
+
    
+
    [Called By]
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_Check
+
    
+
+
    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SVC_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SendConsoleByte (Thumb, 14 bytes, Stack size 8 bytes, printf.o(i.SendConsoleByte))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = SendConsoleByte ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartByte
+
    
+
    [Called By]
    • >>   DataProc_Nrf24l01
+
    
+
+
    SendConsoleData (Thumb, 18 bytes, Stack size 16 bytes, printf.o(i.SendConsoleData))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = SendConsoleData ⇒ SendUartData ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartData
+
    
+
    [Called By]
    • >>   DataProc_USART1
+
    • >>   DataProc_Nrf24l01
+
    
+
+
    SendUartByte (Thumb, 32 bytes, Stack size 16 bytes, printf.o(i.SendUartByte))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = SendUartByte
+
    
+
    [Calls]
    • >>   USART_SendData
+
    • >>   USART_GetFlagStatus
+
    
+
    [Called By]
    • >>   SendUartData
+
    • >>   SendConsoleByte
+
    
+
+
    SendUartData (Thumb, 50 bytes, Stack size 24 bytes, printf.o(i.SendUartData))
+

    [Stack]
    • Max Depth = 40
    • Call Chain = SendUartData ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartByte
+
    
+
    [Called By]
    • >>   SendConsoleData
+
    
+
+
    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SysTick_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
+

    [Stack]
    • Max Depth = 28
    • Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
+
    
+
    [Calls]
    • >>   SetSysClock
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(.text)
+
    
+
    TIM3_IRQHandler (Thumb, 38 bytes, Stack size 8 bytes, dataproc.o(i.TIM3_IRQHandler))
+

    [Stack]
    • Max Depth = 20
    • Call Chain = TIM3_IRQHandler ⇒ TIM_GetITStatus
+
    
+
    [Calls]
    • >>   TIM_GetITStatus
+
    • >>   TIM_ClearITPendingBit
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM3_Int_Init (Thumb, 60 bytes, Stack size 24 bytes, tim.o(i.TIM3_Int_Init))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = TIM3_Int_Init
+
    
+
    [Calls]
    • >>   TIM_TimeBaseInit
+
    • >>   TIM_ITConfig
+
    • >>   TIM_Cmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    TIM_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ClearITPendingBit))
+

    [Called By]
    • >>   TIM3_IRQHandler
+
    
+
+
    TIM_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_Cmd))
+

    [Called By]
    • >>   TIM3_Int_Init
+
    
+
+
    TIM_GetITStatus (Thumb, 34 bytes, Stack size 12 bytes, stm32f10x_tim.o(i.TIM_GetITStatus))
+

    [Stack]
    • Max Depth = 12
    • Call Chain = TIM_GetITStatus
+
    
+
    [Called By]
    • >>   TIM3_IRQHandler
+
    
+
+
    TIM_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ITConfig))
+

    [Called By]
    • >>   TIM3_Int_Init
+
    
+
+
    TIM_TimeBaseInit (Thumb, 122 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_TimeBaseInit))
+

    [Called By]
    • >>   TIM3_Int_Init
+
    
+
+
    USART1_IRQHandler (Thumb, 60 bytes, Stack size 8 bytes, printf.o(i.USART1_IRQHandler))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = USART1_IRQHandler ⇒ USART_GetITStatus
+
    
+
    [Calls]
    • >>   USART_SendData
+
    • >>   USART_ReceiveData
+
    • >>   USART_GetITStatus
+
    • >>   USART_ClearITPendingBit
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USART2_IRQHandler (Thumb, 78 bytes, Stack size 8 bytes, usart2.o(i.USART2_IRQHandler))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = USART2_IRQHandler ⇒ USART_GetITStatus
+
    
+
    [Calls]
    • >>   USART_ReceiveData
+
    • >>   USART_GetITStatus
+
    • >>   USART_GetFlagStatus
+
    • >>   USART_ClearITPendingBit
+
    • >>   USART_ClearFlag
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USART2_Init (Thumb, 126 bytes, Stack size 32 bytes, usart2.o(i.USART2_Init))
+

    [Stack]
    • Max Depth = 100
    • Call Chain = USART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
    
+
    [Calls]
    • >>   USART_Init
+
    • >>   USART_ITConfig
+
    • >>   USART_Cmd
+
    • >>   GPIO_Init
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    USART3_IRQHandler (Thumb, 88 bytes, Stack size 8 bytes, printf.o(i.USART3_IRQHandler))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = USART3_IRQHandler ⇒ USART_GetITStatus
+
    
+
    [Calls]
    • >>   USART_ReceiveData
+
    • >>   USART_GetITStatus
+
    • >>   USART_GetFlagStatus
+
    • >>   USART_ClearITPendingBit
+
    • >>   USART_ClearFlag
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USART_ClearFlag (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ClearFlag))
+

    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART3_IRQHandler
+
    • >>   USART_Configuration
+
    
+
+
    USART_ClearITPendingBit (Thumb, 30 bytes, Stack size 8 bytes, stm32f10x_usart.o(i.USART_ClearITPendingBit))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = USART_ClearITPendingBit
+
    
+
    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    
+
+
    USART_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_Cmd))
+

    [Called By]
    • >>   USART_Configuration
+
    • >>   USART2_Init
+
    
+
+
    USART_Configuration (Thumb, 266 bytes, Stack size 24 bytes, printf.o(i.USART_Configuration))
+

    [Stack]
    • Max Depth = 92
    • Call Chain = USART_Configuration ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
    
+
    [Calls]
    • >>   USART_Init
+
    • >>   USART_ITConfig
+
    • >>   USART_Cmd
+
    • >>   USART_ClearFlag
+
    • >>   GPIO_Init
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    USART_GetFlagStatus (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_GetFlagStatus))
+

    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   fputc
+
    • >>   USART3_IRQHandler
+
    • >>   SendUartByte
+
    
+
+
    USART_GetITStatus (Thumb, 84 bytes, Stack size 16 bytes, stm32f10x_usart.o(i.USART_GetITStatus))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = USART_GetITStatus
+
    
+
    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    
+
+
    USART_ITConfig (Thumb, 74 bytes, Stack size 20 bytes, stm32f10x_usart.o(i.USART_ITConfig))
+

    [Stack]
    • Max Depth = 20
    • Call Chain = USART_ITConfig
+
    
+
    [Called By]
    • >>   USART_Configuration
+
    • >>   USART2_Init
+
    
+
+
    USART_Init (Thumb, 210 bytes, Stack size 56 bytes, stm32f10x_usart.o(i.USART_Init))
+

    [Stack]
    • Max Depth = 68
    • Call Chain = USART_Init ⇒ RCC_GetClocksFreq
+
    
+
    [Calls]
    • >>   RCC_GetClocksFreq
+
    
+
    [Called By]
    • >>   USART_Configuration
+
    • >>   USART2_Init
+
    
+
+
    USART_ReceiveData (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ReceiveData))
+

    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    
+
+
    USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_SendData))
+

    [Called By]
    • >>   USART1_IRQHandler
+
    • >>   SendUartByte
+
    
+
+
    UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.UsageFault_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    __0printf$bare (Thumb, 8 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare), UNUSED)
+

    [Calls]
    • >>   _printf_core
+
    
+
+
    __1printf$bare (Thumb, 0 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare), UNUSED)
+
+
    __2printf (Thumb, 0 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare))
+

    [Called By]
    • >>   DataProc_USART1
+
    • >>   main
+
    
+
+
    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
+
+
    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
+
+
    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
+
+
    delay_ms (Thumb, 42 bytes, Stack size 8 bytes, delay.o(i.delay_ms))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = delay_ms
+
    
+
    [Called By]
    • >>   DataProc_1356
+
    • >>   main
+
    
+
+
    fputc (Thumb, 32 bytes, Stack size 16 bytes, printf.o(i.fputc))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = fputc
+
    
+
    [Calls]
    • >>   USART_GetFlagStatus
+
    
+
    [Address Reference Count : 1]
    •  printfb.o(i.__0printf$bare)
+
    
+
    led_init (Thumb, 84 bytes, Stack size 8 bytes, led.o(i.led_init))
+

    [Stack]
    • Max Depth = 32
    • Call Chain = led_init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   GPIO_SetBits
+
    • >>   GPIO_ResetBits
+
    • >>   GPIO_Init
+
    • >>   RCC_APB2PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    main (Thumb, 136 bytes, Stack size 0 bytes, main.o(i.main))
+

    [Stack]
    • Max Depth = 112
    • Call Chain = main ⇒ DataProc_Nrf24l01 ⇒ NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   led_init
+
    • >>   delay_ms
+
    • >>   USART_Configuration
+
    • >>   USART2_Init
+
    • >>   TIM3_Int_Init
+
    • >>   NRF24L01_TX_Mode
+
    • >>   NRF24L01_Init
+
    • >>   NRF24L01_Check
+
    • >>   Data_Init
+
    • >>   DataProc_USART1
+
    • >>   DataProc_Nrf24l01
+
    • >>   DataProc_1356
+
    • >>   RCC_Configuration
+
    • >>   NVIC_Configuration
+
    • >>   __2printf
+
    
+
    [Address Reference Count : 1]
    •  entry9a.o(.ARM.Collect$$$$0000000B)
+
    
+
    
+Local Symbols
+
    
+
    SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
+

    [Stack]
    • Max Depth = 20
    • Call Chain = SetSysClock ⇒ SetSysClockTo72
+
    
+
    [Calls]
    • >>   SetSysClockTo72
+
    
+
    [Called By]
    • >>   SystemInit
+
    
+
+
    SetSysClockTo72 (Thumb, 212 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
+

    [Stack]
    • Max Depth = 12
    • Call Chain = SetSysClockTo72
+
    
+
    [Called By]
    • >>   SetSysClock
+
    
+
+
    _printf_core (Thumb, 34 bytes, Stack size 24 bytes, printfb.o(i._printf_core), UNUSED)
+

    [Called By]
    • >>   __0printf$bare
+
    
+
    
+
    
+Undefined Global Symbols
+
    
diff --git a/RVMDK/Obj/Printf_AUTO.lnp b/RVMDK/Obj/Printf_AUTO.lnp
new file mode 100644
index 0000000..7e5bb58
--- /dev/null
+++ b/RVMDK/Obj/Printf_AUTO.lnp
@@ -0,0 +1,24 @@
+--cpu Cortex-M3
+".\obj\main.o"
+".\obj\printf.o"
+".\obj\delay.o"
+".\obj\led.o"
+".\obj\usart2.o"
+".\obj\nrf24l01.o"
+".\obj\spi.o"
+".\obj\dataproc.o"
+".\obj\tim.o"
+".\obj\stm32f10x_it.o"
+".\obj\stm32f10x_rcc.o"
+".\obj\stm32f10x_usart.o"
+".\obj\misc.o"
+".\obj\stm32f10x_gpio.o"
+".\obj\stm32f10x_spi.o"
+".\obj\stm32f10x_tim.o"
+".\obj\core_cm3.o"
+".\obj\system_stm32f10x.o"
+".\obj\startup_stm32f10x_hd.o"
+--library_type=microlib --strict --scatter ".\Obj\Printf_AUTO.sct"
+--summary_stderr --info summarysizes --map --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\List\Printf_AUTO.map" -o .\Obj\Printf_AUTO.axf
\ No newline at end of file
diff --git a/RVMDK/Obj/Printf_AUTO.sct b/RVMDK/Obj/Printf_AUTO.sct
new file mode 100644
index 0000000..fd82337
--- /dev/null
+++ b/RVMDK/Obj/Printf_AUTO.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x0000C000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/RVMDK/Obj/Printf_CreativeST_VC.dep b/RVMDK/Obj/Printf_CreativeST_VC.dep
new file mode 100644
index 0000000..963c5a1
--- /dev/null
+++ b/RVMDK/Obj/Printf_CreativeST_VC.dep
@@ -0,0 +1,658 @@
+Dependencies for Project 'Printf', Target 'CreativeST_VC': (DO NOT MODIFY !)
+F (..\bsp\printf.c)(0x5B813229)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\printf.o --omf_browse .\obj\printf.crf --depend .\obj\printf.d)
+I (..\bsp\printf.h)(0x5CA2BD8A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x569DEA3A)
+F (..\bsp\delay.c)(0x5AAF6F3E)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\delay.o --omf_browse .\obj\delay.crf --depend .\obj\delay.d)
+I (..\bsp\delay.h)(0x5A547551)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\main.c)(0x5DCBC7D2)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\main.o --omf_browse .\obj\main.crf --depend .\obj\main.d)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\printf.h)(0x5CA2BD8A)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x569DEA3A)
+I (..\bsp\USART2.h)(0x59926A43)
+I (..\bsp\LED.h)(0x59926A43)
+I (..\bsp\delay.h)(0x5A547551)
+I (..\bsp\nrf24L01.h)(0x5A559D9D)
+I (..\bsp\nrf_gpio.h)(0x5AB2098B)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\bsp\DataProc.h)(0x59C34BC1)
+I (..\bsp\stmflash.h)(0x59C5CBBC)
+I (..\bsp\tim.h)(0x59926A43)
+I (..\bsp\flash.h)(0x598BC710)
+I (..\bsp\LCD.h)(0x5D283C49)
+F (..\bsp\nrf24L01.c)(0x5DCBC7A1)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\nrf24l01.o --omf_browse .\obj\nrf24l01.crf --depend .\obj\nrf24l01.d)
+I (..\bsp\nrf24L01.h)(0x5A559D9D)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\nrf_gpio.h)(0x5AB2098B)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\bsp\printf.h)(0x5CA2BD8A)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x569DEA3A)
+I (..\bsp\delay.h)(0x5A547551)
+F (..\bsp\tim.c)(0x59926A43)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\tim.o --omf_browse .\obj\tim.crf --depend .\obj\tim.d)
+I (..\bsp\tim.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\spi.c)(0x59C4A827)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\spi.o --omf_browse .\obj\spi.crf --depend .\obj\spi.d)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\LED.c)(0x59926A43)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\led.o --omf_browse .\obj\led.crf --depend .\obj\led.d)
+I (..\bsp\LED.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\DataProc.c)(0x5D70BBFC)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\dataproc.o --omf_browse .\obj\dataproc.crf --depend .\obj\dataproc.d)
+I (..\bsp\DataProc.h)(0x59C34BC1)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\nrf24L01.h)(0x5A559D9D)
+I (..\bsp\nrf_gpio.h)(0x5AB2098B)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\bsp\printf.h)(0x5CA2BD8A)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x569DEA3A)
+I (..\bsp\delay.h)(0x5A547551)
+I (..\bsp\led.h)(0x59926A43)
+I (..\bsp\USART2.h)(0x59926A43)
+I (..\bsp\stmflash.h)(0x59C5CBBC)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x569DEA3A)
+I (..\bsp\flash.h)(0x598BC710)
+I (..\bsp\LCD.h)(0x5D283C49)
+F (..\bsp\USART2.c)(0x59926A43)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\usart2.o --omf_browse .\obj\usart2.crf --depend .\obj\usart2.d)
+I (..\bsp\USART2.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\flash.c)(0x59C5BD9B)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\flash.o --omf_browse .\obj\flash.crf --depend .\obj\flash.d)
+I (..\bsp\flash.h)(0x598BC710)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\printf.h)(0x5CA2BD8A)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x569DEA3A)
+F (..\bsp\LCD.c)(0x5AC11D8A)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\lcd.o --omf_browse .\obj\lcd.crf --depend .\obj\lcd.d)
+I (..\bsp\LCD.h)(0x5D283C49)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\stm32f10x_it.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_it.o --omf_browse .\obj\stm32f10x_it.crf --depend .\obj\stm32f10x_it.d)
+I (..\Libraries\stm32f10x_it.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c)(0x5AA93522)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_rcc.o --omf_browse .\obj\stm32f10x_rcc.crf --depend .\obj\stm32f10x_rcc.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_usart.o --omf_browse .\obj\stm32f10x_usart.crf --depend .\obj\stm32f10x_usart.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\misc.o --omf_browse .\obj\misc.crf --depend .\obj\misc.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_gpio.o --omf_browse .\obj\stm32f10x_gpio.crf --depend .\obj\stm32f10x_gpio.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_spi.o --omf_browse .\obj\stm32f10x_spi.crf --depend .\obj\stm32f10x_spi.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_tim.o --omf_browse .\obj\stm32f10x_tim.crf --depend .\obj\stm32f10x_tim.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c)(0x59E1E338)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_iwdg.o --omf_browse .\obj\stm32f10x_iwdg.crf --depend .\obj\stm32f10x_iwdg.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c)(0x59C5CC1A)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_flash.o --omf_browse .\obj\stm32f10x_flash.crf --depend .\obj\stm32f10x_flash.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c)(0x59926A40)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\core_cm3.o --omf_browse .\obj\core_cm3.crf --depend .\obj\core_cm3.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+F (..\Libraries\system_stm32f10x.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\ -I ..\Libraries\CMSIS\CM3\CoreSupport -I ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I ..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\bsp -I ..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="518" -D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\system_stm32f10x.o --omf_browse .\obj\system_stm32f10x.crf --depend .\obj\system_stm32f10x.d)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x569DEA3A)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s)(0x5A535F2C)(--cpu Cortex-M3 -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

--pd "__UVISION_VERSION SETA 518" --pd "_RTE_ SETA 1" --pd "STM32F10X_HD_VL SETA 1"

--list .\list\startup_stm32f10x_hd.lst --xref -o .\obj\startup_stm32f10x_hd.o --depend .\obj\startup_stm32f10x_hd.d)
+F (..\˵.txt)(0x59926A43)()
diff --git a/RVMDK/Obj/Printf_PC.axf b/RVMDK/Obj/Printf_PC.axf
new file mode 100644
index 0000000..4aa8bd1
Binary files /dev/null and b/RVMDK/Obj/Printf_PC.axf differ
diff --git a/RVMDK/Obj/Printf_PC.bin b/RVMDK/Obj/Printf_PC.bin
new file mode 100644
index 0000000..d4a0c46
Binary files /dev/null and b/RVMDK/Obj/Printf_PC.bin differ
diff --git a/RVMDK/Obj/Printf_PC.build_log.htm b/RVMDK/Obj/Printf_PC.build_log.htm
new file mode 100644
index 0000000..b2be7a0
--- /dev/null
+++ b/RVMDK/Obj/Printf_PC.build_log.htm
@@ -0,0 +1,53 @@
+
+
+
    +
    Vision Build Log
    
+
    Tool Versions:
    
+IDE-Version: Vision V5.18.0.0
+Copyright (C) 2016 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: zhan FS_BJB150, Microsoft, LIC=3UUCX-H9VU4-KSLYM-X6IH1-UGX9A-6T7DG
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Professional  Version: 5.18
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 1 (build 61)
+Assembler:       Armasm.exe V5.06 update 1 (build 61)
+Linker/Locator:  ArmLink.exe V5.06 update 1 (build 61)
+Library Manager: ArmAr.exe V5.06 update 1 (build 61)
+Hex Converter:   FromElf.exe V5.06 update 1 (build 61)
+CPU DLL:         SARMCM3.DLL V5.18
+Dialog DLL:      DCM.DLL V1.13.6.0
+Target DLL:      Segger\JL2CM3.dll V2.99.18.0
+Dialog DLL:      TCM.DLL V1.14.8.0
+ 
+
    Project:
    
+E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\Printf.uvprojx
+Project File Date:  07/12/2019
+
+
    Output:
    
+*** Using Compiler 'V5.06 update 1 (build 61)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'CreativeST_VC'
+FromELF: creating hex file...
+After Build - User command #1: "C:\Keil_v5\ARM\ARMCC\bin\fromelf.exe" --bin -o  ..\RVMDK\obj\Printf_PC.bin  ..\RVMDK\obj\Printf_PC.axf
+".\Obj\Printf_PC.axf" - 0 Error(s), 0 Warning(s).
+
+
    Software Packages used:
    
+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.4.5.0.pack
+                ARM::CMSIS:CORE:4.3.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 4.3.0
+
+
    Collection of Component include folders:
    
+  E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE
+  C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include
+  C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
+
+
    Collection of Component Files used:
    
+
+   * Component: ARM::CMSIS:CORE:4.3.0
+Build Time Elapsed:  00:00:03
+
    
+
+
diff --git a/RVMDK/Obj/Printf_PC.hex b/RVMDK/Obj/Printf_PC.hex
new file mode 100644
index 0000000..425703e
--- /dev/null
+++ b/RVMDK/Obj/Printf_PC.hex
@@ -0,0 +1,879 @@
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+:10364000000000000000000000000000000000007A
+:103650000000000000000000000031323334353635
+:1036600037383931323334353637383900000000D5
+:103670000000000000000000000031323334353615
+:1036800037383931323334353637383900000000B5
+:10369000000000000000000000000000000000002A
+:1036A00000000000010203040102030406070809E8
+:0836B0000204060800000000FE
+:0400000508000131BD
+:00000001FF
diff --git a/RVMDK/Obj/Printf_PC.htm b/RVMDK/Obj/Printf_PC.htm
new file mode 100644
index 0000000..96b2276
--- /dev/null
+++ b/RVMDK/Obj/Printf_PC.htm
@@ -0,0 +1,1408 @@
+
+
+Static Call Graph - [.\Obj\Printf_PC.axf]
+
    
+
    Static Call Graph for image .\Obj\Printf_PC.axf
    
+
    #<CALLGRAPH># ARM Linker, 5060061: Last Updated: Wed Nov 13 17:08:26 2019
+
    
+
    Maximum Stack Usage =        128 bytes + Unknown(Cycles, Untraceable Function Pointers)
    
+Call chain for Maximum Stack Depth:
    
+main ⇒ DataProc_USART1 ⇒ DataProc_A0_WriteNum_SPI2 ⇒ NRF24L01_RX_Mode_NOACK ⇒ NRF24L01_RX_YunNan_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    
+Mutually Recursive functions
+
     
  • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
    
+
+
    
+
    
+Function Pointers
+
      
+ 
    • ADC1_2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • ADC3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • BusFault_Handler from stm32f10x_it.o(i.BusFault_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • CAN1_RX1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • CAN1_SCE_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA1_Channel7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DMA2_Channel4_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • DebugMon_Handler from stm32f10x_it.o(i.DebugMon_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI0_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI15_10_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • EXTI9_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • FLASH_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • FSMC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • HardFault_Handler from stm32f10x_it.o(i.HardFault_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C1_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C1_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C2_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • I2C2_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • MemManage_Handler from stm32f10x_it.o(i.MemManage_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • NMI_Handler from stm32f10x_it.o(i.NMI_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • PVD_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • PendSV_Handler from stm32f10x_it.o(i.PendSV_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • RCC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • RTCAlarm_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • RTC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • Reset_Handler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SDIO_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SPI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SPI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SPI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SVC_Handler from stm32f10x_it.o(i.SVC_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SysTick_Handler from stm32f10x_it.o(i.SysTick_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_hd.o(.text)
+ 
    • TAMPER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM1_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM3_IRQHandler from dataproc.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • TIM8_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • UART4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • UART5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USART1_IRQHandler from printf.o(i.USART1_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USART2_IRQHandler from usart2.o(i.USART2_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USART3_IRQHandler from printf.o(i.USART3_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USBWakeUp_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • UsageFault_Handler from stm32f10x_it.o(i.UsageFault_Handler) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • WWDG_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
+ 
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_hd.o(.text)
+ 
    • fputc from printf.o(i.fputc) referenced from printfb.o(i.__0printf$bare)
+ 
    • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
+
    
+
    
+
    
+Global Symbols
+
    
+
    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(.text)
+
    
+
    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
+
+
    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+

    [Calls]
    • >>   __scatterload
+
    
+
+
    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
+

    [Called By]
    • >>   __scatterload
+
    
+
+
    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
+
+
    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
+
+
    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
+
+
    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
+
+
    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
+
+
    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+

    [Calls]
    • >>   ADC1_2_IRQHandler
+
    
+
    [Called By]
    • >>   ADC1_2_IRQHandler
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    ADC3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DMA2_Channel4_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    FSMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM8_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    __aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text))
+

    [Called By]
    • >>   _memset$wrapper
+
    • >>   __aeabi_memclr
+
    
+
+
    __aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
    __aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
    __aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text))
+

    [Calls]
    • >>   __aeabi_memset
+
    
+
    [Called By]
    • >>   DataProc_1356
+
    
+
+
    __aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
+

    [Called By]
    • >>   SavePara_to_flash
+
    • >>   Readpara_from_flash
+
    
+
+
    __aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
+
+
    _memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
+

    [Calls]
    • >>   __aeabi_memset
+
    
+
+
    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
+

    [Calls]
    • >>   __main_after_scatterload
+
    
+
    [Called By]
    • >>   _main_scatterload
+
    
+
+
    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
+
+
    BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.BusFault_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    CheckSum (Thumb, 36 bytes, Stack size 8 bytes, dataproc.o(i.CheckSum))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = CheckSum
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    
+
+
    DataProc_1356 (Thumb, 248 bytes, Stack size 32 bytes, dataproc.o(i.DataProc_1356))
+

    [Stack]
    • Max Depth = 40
    • Call Chain = DataProc_1356 ⇒ IWDG_Feed
+
    
+
    [Calls]
    • >>   IWDG_Feed
+
    • >>   __aeabi_memclr
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    DataProc_A0_WriteNum_SPI2 (Thumb, 516 bytes, Stack size 40 bytes, dataproc.o(i.DataProc_A0_WriteNum_SPI2))
+

    [Stack]
    • Max Depth = 120
    • Call Chain = DataProc_A0_WriteNum_SPI2 ⇒ NRF24L01_RX_Mode_NOACK ⇒ NRF24L01_RX_YunNan_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   CheckSum
+
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_RX_Mode_NOACK
+
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    • >>   NRF24L01_RX_Mode
+
    • >>   IWDG_Feed
+
    • >>   SendUSART2Str
+
    • >>   SendUSART2Byte
+
    • >>   SendConsoleData
+
    • >>   DegugPrintf
+
    
+
    [Called By]
    • >>   DataProc_USART1
+
    
+
+
    DataProc_A4_nrf (Thumb, 350 bytes, Stack size 40 bytes, dataproc.o(i.DataProc_A4_nrf))
+

    [Stack]
    • Max Depth = 112
    • Call Chain = DataProc_A4_nrf ⇒ NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_RxPacket
+
    • >>   IWDG_Feed
+
    
+
    [Called By]
    • >>   DataProc_USART1
+
    
+
+
    DataProc_USART1 (Thumb, 1512 bytes, Stack size 8 bytes, dataproc.o(i.DataProc_USART1))
+

    [Stack]
    • Max Depth = 128
    • Call Chain = DataProc_USART1 ⇒ DataProc_A0_WriteNum_SPI2 ⇒ NRF24L01_RX_Mode_NOACK ⇒ NRF24L01_RX_YunNan_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SavePara_to_flash
+
    • >>   DataProc_A4_nrf
+
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   NRF24L01_RX_Mode_NOACK
+
    • >>   NRF24L01_RX_Mode
+
    • >>   IWDG_Feed
+
    • >>   delay_ms
+
    • >>   SendUSART2Str
+
    • >>   SendConsoleData
+
    • >>   DegugPrintf
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    Data_Init (Thumb, 298 bytes, Stack size 0 bytes, dataproc.o(i.Data_Init))
+

    [Called By]
    • >>   main
+
    
+
+
    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.DebugMon_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    DegugPrintf (Thumb, 52 bytes, Stack size 24 bytes, printf.o(i.DegugPrintf))
+

    [Stack]
    • Max Depth = 48
    • Call Chain = DegugPrintf ⇒ SendUSART2Byte ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUSART2Byte
+
    • >>   HexToAscii
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   DataProc_USART1
+
    • >>   main
+
    
+
+
    FLASH_ErasePage (Thumb, 72 bytes, Stack size 12 bytes, stm32f10x_flash.o(i.FLASH_ErasePage))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = FLASH_ErasePage ⇒ FLASH_WaitForLastOperation
+
    
+
    [Calls]
    • >>   FLASH_WaitForLastOperation
+
    
+
    [Called By]
    • >>   Startwritedata
+
    
+
+
    FLASH_GetBank1Status (Thumb, 48 bytes, Stack size 0 bytes, stm32f10x_flash.o(i.FLASH_GetBank1Status))
+

    [Called By]
    • >>   FLASH_WaitForLastOperation
+
    
+
+
    FLASH_Lock (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_flash.o(i.FLASH_Lock))
+

    [Called By]
    • >>   Write_Complete
+
    
+
+
    FLASH_ProgramHalfWord (Thumb, 60 bytes, Stack size 16 bytes, stm32f10x_flash.o(i.FLASH_ProgramHalfWord))
+

    [Stack]
    • Max Depth = 20
    • Call Chain = FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation
+
    
+
    [Calls]
    • >>   FLASH_WaitForLastOperation
+
    
+
    [Called By]
    • >>   SavePara
+
    
+
+
    FLASH_Unlock (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_flash.o(i.FLASH_Unlock))
+

    [Called By]
    • >>   Startwritedata
+
    
+
+
    FLASH_WaitForLastOperation (Thumb, 38 bytes, Stack size 4 bytes, stm32f10x_flash.o(i.FLASH_WaitForLastOperation))
+

    [Stack]
    • Max Depth = 4
    • Call Chain = FLASH_WaitForLastOperation
+
    
+
    [Calls]
    • >>   FLASH_GetBank1Status
+
    
+
    [Called By]
    • >>   FLASH_ProgramHalfWord
+
    • >>   FLASH_ErasePage
+
    
+
+
    GPIO_Init (Thumb, 278 bytes, Stack size 24 bytes, stm32f10x_gpio.o(i.GPIO_Init))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = GPIO_Init
+
    
+
    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   led_init
+
    • >>   USART2_Init
+
    • >>   NRF24L01_Init
+
    • >>   USART_Configuration
+
    
+
+
    GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ResetBits))
+

    [Called By]
    • >>   TIM3_IRQHandler
+
    • >>   led_init
+
    
+
+
    GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_SetBits))
+

    [Called By]
    • >>   TIM3_IRQHandler
+
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   led_init
+
    • >>   NRF24L01_Init
+
    
+
+
    GetPara (Thumb, 8 bytes, Stack size 0 bytes, flash.o(i.GetPara))
+

    [Called By]
    • >>   Readstr_of_flash
+
    
+
+
    HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.HardFault_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    HexToAscii (Thumb, 32 bytes, Stack size 0 bytes, printf.o(i.HexToAscii))
+

    [Called By]
    • >>   DegugPrintf
+
    
+
+
    IWDG_Enable (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_Enable))
+

    [Called By]
    • >>   IWDG_Init
+
    
+
+
    IWDG_Feed (Thumb, 8 bytes, Stack size 8 bytes, main.o(i.IWDG_Feed))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = IWDG_Feed
+
    
+
    [Calls]
    • >>   IWDG_ReloadCounter
+
    
+
    [Called By]
    • >>   DataProc_A4_nrf
+
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   DataProc_USART1
+
    • >>   DataProc_1356
+
    • >>   main
+
    
+
+
    IWDG_Init (Thumb, 36 bytes, Stack size 16 bytes, main.o(i.IWDG_Init))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = IWDG_Init
+
    
+
    [Calls]
    • >>   IWDG_WriteAccessCmd
+
    • >>   IWDG_SetReload
+
    • >>   IWDG_SetPrescaler
+
    • >>   IWDG_ReloadCounter
+
    • >>   IWDG_Enable
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    IWDG_ReloadCounter (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_ReloadCounter))
+

    [Called By]
    • >>   IWDG_Init
+
    • >>   IWDG_Feed
+
    
+
+
    IWDG_SetPrescaler (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_SetPrescaler))
+

    [Called By]
    • >>   IWDG_Init
+
    
+
+
    IWDG_SetReload (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_SetReload))
+

    [Called By]
    • >>   IWDG_Init
+
    
+
+
    IWDG_WriteAccessCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd))
+

    [Called By]
    • >>   IWDG_Init
+
    
+
+
    MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.MemManage_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.NMI_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    NRF24L01_Check (Thumb, 80 bytes, Stack size 24 bytes, nrf24l01.o(i.NRF24L01_Check))
+

    [Stack]
    • Max Depth = 80
    • Call Chain = NRF24L01_Check ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_SetSpeed
+
    • >>   NRF24L01_Write_Buf
+
    • >>   NRF24L01_Read_Buf
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    NRF24L01_Init (Thumb, 232 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_Init))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_Init ⇒ SPI2_Init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   GPIO_SetBits
+
    • >>   SPI_SetSpeed
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   GPIO_Init
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    NRF24L01_RX_AHDX_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_AHDX_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_AHDX_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_AnHui_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_AnHui_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_AnHui_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_CQYD_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_CQYD_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_CQYD_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_DH_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_DH_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_DH_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_FJZZ_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_FJZZ_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_FJZZ_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_GSYD_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_GSYD_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_GSYD_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_GXYD_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_GXYD_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_GXYD_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_GuiZhou_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_GuiZhou_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_GuiZhou_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_JiangXi_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_JiangXi_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_JiangXi_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_LIAO_NING_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_LIAO_NING_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_LIAO_NING_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_Mode (Thumb, 166 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_Mode))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_Mode ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   DataProc_USART1
+
    • >>   main
+
    
+
+
    NRF24L01_RX_Mode_NOACK (Thumb, 262 bytes, Stack size 16 bytes, nrf24l01.o(i.NRF24L01_RX_Mode_NOACK))
+

    [Stack]
    • Max Depth = 80
    • Call Chain = NRF24L01_RX_Mode_NOACK ⇒ NRF24L01_RX_YunNan_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_RX_YunNan_CONFIG
+
    • >>   NRF24L01_RX_XDF_CONFIG
+
    • >>   NRF24L01_RX_VCM_CONFIG
+
    • >>   NRF24L01_RX_TelPo_CONFIG
+
    • >>   NRF24L01_RX_TP_CONFIG
+
    • >>   NRF24L01_RX_SiChuan_CONFIG
+
    • >>   NRF24L01_RX_ShanXiXinNuo_CONFIG
+
    • >>   NRF24L01_RX_SZML_CONFIG
+
    • >>   NRF24L01_RX_SXYD_CONFIG
+
    • >>   NRF24L01_RX_NeiMengGu_CONFIG
+
    • >>   NRF24L01_RX_NMGYD_CONFIG
+
    • >>   NRF24L01_RX_NEW_LIAO_NING_CONFIG
+
    • >>   NRF24L01_RX_LIAO_NING_CONFIG
+
    • >>   NRF24L01_RX_JiangXi_CONFIG
+
    • >>   NRF24L01_RX_GuiZhou_CONFIG
+
    • >>   NRF24L01_RX_GXYD_CONFIG
+
    • >>   NRF24L01_RX_GSYD_CONFIG
+
    • >>   NRF24L01_RX_FJZZ_CONFIG
+
    • >>   NRF24L01_RX_DH_CONFIG
+
    • >>   NRF24L01_RX_CQYD_CONFIG
+
    • >>   NRF24L01_RX_AnHui_CONFIG
+
    • >>   NRF24L01_RX_AHDX_CONFIG
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   DataProc_USART1
+
    
+
+
    NRF24L01_RX_NEW_LIAO_NING_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_NEW_LIAO_NING_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_NEW_LIAO_NING_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_NMGYD_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_NMGYD_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_NMGYD_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_NeiMengGu_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_NeiMengGu_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_NeiMengGu_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_SXYD_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_SXYD_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_SXYD_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_SZML_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_SZML_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_SZML_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_ShanXiXinNuo_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_ShanXiXinNuo_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_ShanXiXinNuo_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_SiChuan_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_SiChuan_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_SiChuan_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_TP_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_TP_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_TP_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_TelPo_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_TelPo_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_TelPo_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_VCM_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_VCM_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_VCM_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_XDF_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_XDF_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_XDF_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_RX_YunNan_CONFIG (Thumb, 140 bytes, Stack size 8 bytes, nrf24l01.o(i.NRF24L01_RX_YunNan_CONFIG))
+

    [Stack]
    • Max Depth = 64
    • Call Chain = NRF24L01_RX_YunNan_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    
+
    [Called By]
    • >>   NRF24L01_RX_Mode_NOACK
+
    
+
+
    NRF24L01_Read_Buf (Thumb, 114 bytes, Stack size 32 bytes, nrf24l01.o(i.NRF24L01_Read_Buf))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_Check
+
    
+
+
    NRF24L01_Read_Reg (Thumb, 78 bytes, Stack size 16 bytes, nrf24l01.o(i.NRF24L01_Read_Reg))
+

    [Stack]
    • Max Depth = 40
    • Call Chain = NRF24L01_Read_Reg ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   NRF24L01_RxPacket
+
    
+
+
    NRF24L01_RxPacket (Thumb, 66 bytes, Stack size 16 bytes, nrf24l01.o(i.NRF24L01_RxPacket))
+

    [Stack]
    • Max Depth = 72
    • Call Chain = NRF24L01_RxPacket ⇒ NRF24L01_Read_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_SetSpeed
+
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Read_Reg
+
    • >>   NRF24L01_Read_Buf
+
    
+
    [Called By]
    • >>   DataProc_A4_nrf
+
    • >>   DataProc_A0_WriteNum_SPI2
+
    
+
+
    NRF24L01_Write_Buf (Thumb, 114 bytes, Stack size 32 bytes, nrf24l01.o(i.NRF24L01_Write_Buf))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   NRF24L01_RX_YunNan_CONFIG
+
    • >>   NRF24L01_RX_XDF_CONFIG
+
    • >>   NRF24L01_RX_VCM_CONFIG
+
    • >>   NRF24L01_RX_TelPo_CONFIG
+
    • >>   NRF24L01_RX_TP_CONFIG
+
    • >>   NRF24L01_RX_SiChuan_CONFIG
+
    • >>   NRF24L01_RX_ShanXiXinNuo_CONFIG
+
    • >>   NRF24L01_RX_SZML_CONFIG
+
    • >>   NRF24L01_RX_SXYD_CONFIG
+
    • >>   NRF24L01_RX_NeiMengGu_CONFIG
+
    • >>   NRF24L01_RX_NMGYD_CONFIG
+
    • >>   NRF24L01_RX_NEW_LIAO_NING_CONFIG
+
    • >>   NRF24L01_RX_LIAO_NING_CONFIG
+
    • >>   NRF24L01_RX_JiangXi_CONFIG
+
    • >>   NRF24L01_RX_GuiZhou_CONFIG
+
    • >>   NRF24L01_RX_GXYD_CONFIG
+
    • >>   NRF24L01_RX_GSYD_CONFIG
+
    • >>   NRF24L01_RX_FJZZ_CONFIG
+
    • >>   NRF24L01_RX_DH_CONFIG
+
    • >>   NRF24L01_RX_CQYD_CONFIG
+
    • >>   NRF24L01_RX_AnHui_CONFIG
+
    • >>   NRF24L01_RX_AHDX_CONFIG
+
    • >>   NRF24L01_RX_Mode
+
    • >>   NRF24L01_Check
+
    
+
+
    NRF24L01_Write_Reg (Thumb, 84 bytes, Stack size 24 bytes, nrf24l01.o(i.NRF24L01_Write_Reg))
+

    [Stack]
    • Max Depth = 48
    • Call Chain = NRF24L01_Write_Reg ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_ReadWriteByte
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_RX_YunNan_CONFIG
+
    • >>   NRF24L01_RX_XDF_CONFIG
+
    • >>   NRF24L01_RX_VCM_CONFIG
+
    • >>   NRF24L01_RX_TelPo_CONFIG
+
    • >>   NRF24L01_RX_TP_CONFIG
+
    • >>   NRF24L01_RX_SiChuan_CONFIG
+
    • >>   NRF24L01_RX_ShanXiXinNuo_CONFIG
+
    • >>   NRF24L01_RX_SZML_CONFIG
+
    • >>   NRF24L01_RX_SXYD_CONFIG
+
    • >>   NRF24L01_RX_NeiMengGu_CONFIG
+
    • >>   NRF24L01_RX_NMGYD_CONFIG
+
    • >>   NRF24L01_RX_NEW_LIAO_NING_CONFIG
+
    • >>   NRF24L01_RX_LIAO_NING_CONFIG
+
    • >>   NRF24L01_RX_JiangXi_CONFIG
+
    • >>   NRF24L01_RX_GuiZhou_CONFIG
+
    • >>   NRF24L01_RX_GXYD_CONFIG
+
    • >>   NRF24L01_RX_GSYD_CONFIG
+
    • >>   NRF24L01_RX_FJZZ_CONFIG
+
    • >>   NRF24L01_RX_DH_CONFIG
+
    • >>   NRF24L01_RX_CQYD_CONFIG
+
    • >>   NRF24L01_RX_AnHui_CONFIG
+
    • >>   NRF24L01_RX_AHDX_CONFIG
+
    • >>   NRF24L01_RX_Mode
+
    
+
+
    NVIC_Configuration (Thumb, 124 bytes, Stack size 8 bytes, main.o(i.NVIC_Configuration))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = NVIC_Configuration ⇒ NVIC_Init
+
    
+
    [Calls]
    • >>   NVIC_PriorityGroupConfig
+
    • >>   NVIC_Init
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    NVIC_Init (Thumb, 100 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = NVIC_Init
+
    
+
    [Called By]
    • >>   NVIC_Configuration
+
    
+
+
    NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig))
+

    [Called By]
    • >>   NVIC_Configuration
+
    
+
+
    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.PendSV_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd))
+

    [Called By]
    • >>   SPI2_Init
+
    • >>   USART2_Init
+
    • >>   TIM3_Int_Init
+
    • >>   RCC_Configuration
+
    • >>   USART_Configuration
+
    
+
+
    RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd))
+

    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   led_init
+
    • >>   USART2_Init
+
    • >>   NRF24L01_Init
+
    • >>   RCC_Configuration
+
    • >>   USART_Configuration
+
    
+
+
    RCC_Configuration (Thumb, 98 bytes, Stack size 16 bytes, main.o(i.RCC_Configuration))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = RCC_Configuration
+
    
+
    [Calls]
    • >>   SysTick_CLKSourceConfig
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    RCC_GetClocksFreq (Thumb, 190 bytes, Stack size 16 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = RCC_GetClocksFreq
+
    
+
    [Called By]
    • >>   USART_Init
+
    
+
+
    Readpara_from_flash (Thumb, 52 bytes, Stack size 32 bytes, flash.o(i.Readpara_from_flash))
+

    [Stack]
    • Max Depth = 48
    • Call Chain = Readpara_from_flash ⇒ Readstr_of_flash
+
    
+
    [Calls]
    • >>   Readstr_of_flash
+
    • >>   __aeabi_memclr4
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    Readstr_of_flash (Thumb, 36 bytes, Stack size 16 bytes, flash.o(i.Readstr_of_flash))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = Readstr_of_flash
+
    
+
    [Calls]
    • >>   GetPara
+
    
+
    [Called By]
    • >>   Readpara_from_flash
+
    
+
+
    SPI1_Init (Thumb, 122 bytes, Stack size 32 bytes, spi.o(i.SPI1_Init))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = SPI1_Init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   SPI_Init
+
    • >>   SPI_Cmd
+
    • >>   GPIO_SetBits
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   GPIO_Init
+
    
+
    [Called By]
    • >>   NRF24L01_Init
+
    
+
+
    SPI2_Init (Thumb, 132 bytes, Stack size 32 bytes, spi.o(i.SPI2_Init))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = SPI2_Init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   SPI_Init
+
    • >>   SPI_Cmd
+
    • >>   GPIO_SetBits
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    • >>   GPIO_Init
+
    
+
    [Called By]
    • >>   NRF24L01_Init
+
    
+
+
    SPI_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_Cmd))
+

    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    • >>   SPI_SetSpeed
+
    
+
+
    SPI_I2S_GetFlagStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus))
+

    [Called By]
    • >>   SPI_ReadWriteByte
+
    
+
+
    SPI_I2S_ReceiveData (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_ReceiveData))
+

    [Called By]
    • >>   SPI_ReadWriteByte
+
    
+
+
    SPI_I2S_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_SendData))
+

    [Called By]
    • >>   SPI_ReadWriteByte
+
    
+
+
    SPI_Init (Thumb, 60 bytes, Stack size 8 bytes, stm32f10x_spi.o(i.SPI_Init))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = SPI_Init
+
    
+
    [Called By]
    • >>   SPI2_Init
+
    • >>   SPI1_Init
+
    
+
+
    SPI_ReadWriteByte (Thumb, 158 bytes, Stack size 24 bytes, spi.o(i.SPI_ReadWriteByte))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   SPI_I2S_SendData
+
    • >>   SPI_I2S_ReceiveData
+
    • >>   SPI_I2S_GetFlagStatus
+
    
+
    [Called By]
    • >>   NRF24L01_Write_Reg
+
    • >>   NRF24L01_Write_Buf
+
    • >>   NRF24L01_Read_Reg
+
    • >>   NRF24L01_Read_Buf
+
    
+
+
    SPI_SetSpeed (Thumb, 72 bytes, Stack size 16 bytes, spi.o(i.SPI_SetSpeed))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = SPI_SetSpeed
+
    
+
    [Calls]
    • >>   SPI_Cmd
+
    
+
    [Called By]
    • >>   NRF24L01_RxPacket
+
    • >>   NRF24L01_Init
+
    • >>   NRF24L01_Check
+
    
+
+
    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SVC_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SavePara (Thumb, 16 bytes, Stack size 16 bytes, flash.o(i.SavePara))
+

    [Stack]
    • Max Depth = 36
    • Call Chain = SavePara ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation
+
    
+
    [Calls]
    • >>   FLASH_ProgramHalfWord
+
    
+
    [Called By]
    • >>   Savestr_to_flash
+
    
+
+
    SavePara_to_flash (Thumb, 62 bytes, Stack size 32 bytes, flash.o(i.SavePara_to_flash))
+

    [Stack]
    • Max Depth = 92
    • Call Chain = SavePara_to_flash ⇒ Savestr_to_flash ⇒ SavePara ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation
+
    
+
    [Calls]
    • >>   Write_Complete
+
    • >>   Startwritedata
+
    • >>   Savestr_to_flash
+
    • >>   __aeabi_memclr4
+
    
+
    [Called By]
    • >>   DataProc_USART1
+
    
+
+
    Savestr_to_flash (Thumb, 40 bytes, Stack size 24 bytes, flash.o(i.Savestr_to_flash))
+

    [Stack]
    • Max Depth = 60
    • Call Chain = Savestr_to_flash ⇒ SavePara ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation
+
    
+
    [Calls]
    • >>   SavePara
+
    
+
    [Called By]
    • >>   SavePara_to_flash
+
    
+
+
    SendConsoleData (Thumb, 18 bytes, Stack size 16 bytes, printf.o(i.SendConsoleData))
+

    [Stack]
    • Max Depth = 56
    • Call Chain = SendConsoleData ⇒ SendUartData ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartData
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   DataProc_USART1
+
    
+
+
    SendUSART2Byte (Thumb, 14 bytes, Stack size 8 bytes, printf.o(i.SendUSART2Byte))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = SendUSART2Byte ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartByte
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   DegugPrintf
+
    
+
+
    SendUSART2Str (Thumb, 14 bytes, Stack size 8 bytes, printf.o(i.SendUSART2Str))
+

    [Stack]
    • Max Depth = 40
    • Call Chain = SendUSART2Str ⇒ SendUartStr ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartStr
+
    
+
    [Called By]
    • >>   DataProc_A0_WriteNum_SPI2
+
    • >>   DataProc_USART1
+
    • >>   main
+
    
+
+
    SendUartByte (Thumb, 32 bytes, Stack size 16 bytes, printf.o(i.SendUartByte))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = SendUartByte
+
    
+
    [Calls]
    • >>   USART_SendData
+
    • >>   USART_GetFlagStatus
+
    
+
    [Called By]
    • >>   SendUartStr
+
    • >>   SendUartData
+
    • >>   SendUSART2Byte
+
    
+
+
    SendUartData (Thumb, 50 bytes, Stack size 24 bytes, printf.o(i.SendUartData))
+

    [Stack]
    • Max Depth = 40
    • Call Chain = SendUartData ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartByte
+
    
+
    [Called By]
    • >>   SendConsoleData
+
    
+
+
    SendUartStr (Thumb, 60 bytes, Stack size 16 bytes, printf.o(i.SendUartStr))
+

    [Stack]
    • Max Depth = 32
    • Call Chain = SendUartStr ⇒ SendUartByte
+
    
+
    [Calls]
    • >>   SendUartByte
+
    
+
    [Called By]
    • >>   SendUSART2Str
+
    
+
+
    Startwritedata (Thumb, 16 bytes, Stack size 8 bytes, flash.o(i.Startwritedata))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = Startwritedata ⇒ FLASH_ErasePage ⇒ FLASH_WaitForLastOperation
+
    
+
    [Calls]
    • >>   FLASH_Unlock
+
    • >>   FLASH_ErasePage
+
    
+
    [Called By]
    • >>   SavePara_to_flash
+
    
+
+
    SysTick_CLKSourceConfig (Thumb, 40 bytes, Stack size 0 bytes, misc.o(i.SysTick_CLKSourceConfig))
+

    [Called By]
    • >>   RCC_Configuration
+
    
+
+
    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SysTick_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    SystemInit (Thumb, 82 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
+

    [Stack]
    • Max Depth = 28
    • Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo24
+
    
+
    [Calls]
    • >>   SetSysClock
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(.text)
+
    
+
    TIM3_IRQHandler (Thumb, 134 bytes, Stack size 8 bytes, dataproc.o(i.TIM3_IRQHandler))
+

    [Stack]
    • Max Depth = 20
    • Call Chain = TIM3_IRQHandler ⇒ TIM_GetITStatus
+
    
+
    [Calls]
    • >>   TIM_GetITStatus
+
    • >>   TIM_ClearITPendingBit
+
    • >>   GPIO_ResetBits
+
    • >>   GPIO_SetBits
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    TIM3_Int_Init (Thumb, 60 bytes, Stack size 24 bytes, tim.o(i.TIM3_Int_Init))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = TIM3_Int_Init
+
    
+
    [Calls]
    • >>   TIM_TimeBaseInit
+
    • >>   TIM_ITConfig
+
    • >>   TIM_Cmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    TIM_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ClearITPendingBit))
+

    [Called By]
    • >>   TIM3_IRQHandler
+
    
+
+
    TIM_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_Cmd))
+

    [Called By]
    • >>   TIM3_Int_Init
+
    
+
+
    TIM_GetITStatus (Thumb, 34 bytes, Stack size 12 bytes, stm32f10x_tim.o(i.TIM_GetITStatus))
+

    [Stack]
    • Max Depth = 12
    • Call Chain = TIM_GetITStatus
+
    
+
    [Called By]
    • >>   TIM3_IRQHandler
+
    
+
+
    TIM_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ITConfig))
+

    [Called By]
    • >>   TIM3_Int_Init
+
    
+
+
    TIM_TimeBaseInit (Thumb, 122 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_TimeBaseInit))
+

    [Called By]
    • >>   TIM3_Int_Init
+
    
+
+
    USART1_IRQHandler (Thumb, 78 bytes, Stack size 8 bytes, printf.o(i.USART1_IRQHandler))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = USART1_IRQHandler ⇒ USART_GetITStatus
+
    
+
    [Calls]
    • >>   USART_ReceiveData
+
    • >>   USART_GetITStatus
+
    • >>   USART_GetFlagStatus
+
    • >>   USART_ClearITPendingBit
+
    • >>   USART_ClearFlag
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USART2_IRQHandler (Thumb, 78 bytes, Stack size 8 bytes, usart2.o(i.USART2_IRQHandler))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = USART2_IRQHandler ⇒ USART_GetITStatus
+
    
+
    [Calls]
    • >>   USART_ReceiveData
+
    • >>   USART_GetITStatus
+
    • >>   USART_GetFlagStatus
+
    • >>   USART_ClearITPendingBit
+
    • >>   USART_ClearFlag
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USART2_Init (Thumb, 126 bytes, Stack size 32 bytes, usart2.o(i.USART2_Init))
+

    [Stack]
    • Max Depth = 104
    • Call Chain = USART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
    
+
    [Calls]
    • >>   USART_Init
+
    • >>   USART_ITConfig
+
    • >>   USART_Cmd
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    • >>   GPIO_Init
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    USART3_IRQHandler (Thumb, 88 bytes, Stack size 8 bytes, printf.o(i.USART3_IRQHandler))
+

    [Stack]
    • Max Depth = 24
    • Call Chain = USART3_IRQHandler ⇒ USART_GetITStatus
+
    
+
    [Calls]
    • >>   USART_ReceiveData
+
    • >>   USART_GetITStatus
+
    • >>   USART_GetFlagStatus
+
    • >>   USART_ClearITPendingBit
+
    • >>   USART_ClearFlag
+
    
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    USART_ClearFlag (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ClearFlag))
+

    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART_Configuration
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    
+
+
    USART_ClearITPendingBit (Thumb, 30 bytes, Stack size 8 bytes, stm32f10x_usart.o(i.USART_ClearITPendingBit))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = USART_ClearITPendingBit
+
    
+
    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    
+
+
    USART_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_Cmd))
+

    [Called By]
    • >>   USART2_Init
+
    • >>   USART_Configuration
+
    
+
+
    USART_Configuration (Thumb, 266 bytes, Stack size 24 bytes, printf.o(i.USART_Configuration))
+

    [Stack]
    • Max Depth = 96
    • Call Chain = USART_Configuration ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
    
+
    [Calls]
    • >>   USART_Init
+
    • >>   USART_ITConfig
+
    • >>   USART_Cmd
+
    • >>   USART_ClearFlag
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   RCC_APB1PeriphClockCmd
+
    • >>   GPIO_Init
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    USART_GetFlagStatus (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_GetFlagStatus))
+

    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   fputc
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    • >>   SendUartByte
+
    
+
+
    USART_GetITStatus (Thumb, 84 bytes, Stack size 16 bytes, stm32f10x_usart.o(i.USART_GetITStatus))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = USART_GetITStatus
+
    
+
    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    
+
+
    USART_ITConfig (Thumb, 74 bytes, Stack size 20 bytes, stm32f10x_usart.o(i.USART_ITConfig))
+

    [Stack]
    • Max Depth = 20
    • Call Chain = USART_ITConfig
+
    
+
    [Called By]
    • >>   USART2_Init
+
    • >>   USART_Configuration
+
    
+
+
    USART_Init (Thumb, 210 bytes, Stack size 56 bytes, stm32f10x_usart.o(i.USART_Init))
+

    [Stack]
    • Max Depth = 72
    • Call Chain = USART_Init ⇒ RCC_GetClocksFreq
+
    
+
    [Calls]
    • >>   RCC_GetClocksFreq
+
    
+
    [Called By]
    • >>   USART2_Init
+
    • >>   USART_Configuration
+
    
+
+
    USART_ReceiveData (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ReceiveData))
+

    [Called By]
    • >>   USART2_IRQHandler
+
    • >>   USART3_IRQHandler
+
    • >>   USART1_IRQHandler
+
    
+
+
    USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_SendData))
+

    [Called By]
    • >>   SendUartByte
+
    
+
+
    UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.UsageFault_Handler))
+
    [Address Reference Count : 1]
    •  startup_stm32f10x_hd.o(RESET)
+
    
+
    Write_Complete (Thumb, 8 bytes, Stack size 8 bytes, flash.o(i.Write_Complete))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = Write_Complete
+
    
+
    [Calls]
    • >>   FLASH_Lock
+
    
+
    [Called By]
    • >>   SavePara_to_flash
+
    
+
+
    __0printf$bare (Thumb, 8 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare), UNUSED)
+

    [Calls]
    • >>   _printf_core
+
    
+
+
    __1printf$bare (Thumb, 0 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare), UNUSED)
+
+
    __2printf (Thumb, 0 bytes, Stack size 0 bytes, printfb.o(i.__0printf$bare))
+

    [Called By]
    • >>   main
+
    
+
+
    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
+
+
    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
+
+
    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
+
+
    delay_ms (Thumb, 42 bytes, Stack size 8 bytes, delay.o(i.delay_ms))
+

    [Stack]
    • Max Depth = 8
    • Call Chain = delay_ms
+
    
+
    [Called By]
    • >>   DataProc_USART1
+
    • >>   main
+
    
+
+
    fputc (Thumb, 32 bytes, Stack size 16 bytes, printf.o(i.fputc))
+

    [Stack]
    • Max Depth = 16
    • Call Chain = fputc
+
    
+
    [Calls]
    • >>   USART_GetFlagStatus
+
    
+
    [Address Reference Count : 1]
    •  printfb.o(i.__0printf$bare)
+
    
+
    led_init (Thumb, 84 bytes, Stack size 8 bytes, led.o(i.led_init))
+

    [Stack]
    • Max Depth = 32
    • Call Chain = led_init ⇒ GPIO_Init
+
    
+
    [Calls]
    • >>   GPIO_ResetBits
+
    • >>   GPIO_SetBits
+
    • >>   RCC_APB2PeriphClockCmd
+
    • >>   GPIO_Init
+
    
+
    [Called By]
    • >>   main
+
    
+
+
    main (Thumb, 402 bytes, Stack size 0 bytes, main.o(i.main))
+

    [Stack]
    • Max Depth = 128
    • Call Chain = main ⇒ DataProc_USART1 ⇒ DataProc_A0_WriteNum_SPI2 ⇒ NRF24L01_RX_Mode_NOACK ⇒ NRF24L01_RX_YunNan_CONFIG ⇒ NRF24L01_Write_Buf ⇒ SPI_ReadWriteByte
+
    
+
    [Calls]
    • >>   led_init
+
    • >>   USART2_Init
+
    • >>   TIM3_Int_Init
+
    • >>   Readpara_from_flash
+
    • >>   NRF24L01_RX_Mode
+
    • >>   NRF24L01_Init
+
    • >>   NRF24L01_Check
+
    • >>   Data_Init
+
    • >>   DataProc_USART1
+
    • >>   DataProc_1356
+
    • >>   RCC_Configuration
+
    • >>   NVIC_Configuration
+
    • >>   IWDG_Init
+
    • >>   IWDG_Feed
+
    • >>   delay_ms
+
    • >>   USART_Configuration
+
    • >>   SendUSART2Str
+
    • >>   DegugPrintf
+
    • >>   __2printf
+
    
+
    [Address Reference Count : 1]
    •  entry9a.o(.ARM.Collect$$$$0000000B)
+
    
+
    
+Local Symbols
+
    
+
    SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
+

    [Stack]
    • Max Depth = 20
    • Call Chain = SetSysClock ⇒ SetSysClockTo24
+
    
+
    [Calls]
    • >>   SetSysClockTo24
+
    
+
    [Called By]
    • >>   SystemInit
+
    
+
+
    SetSysClockTo24 (Thumb, 178 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo24))
+

    [Stack]
    • Max Depth = 12
    • Call Chain = SetSysClockTo24
+
    
+
    [Called By]
    • >>   SetSysClock
+
    
+
+
    _printf_core (Thumb, 34 bytes, Stack size 24 bytes, printfb.o(i._printf_core), UNUSED)
+

    [Called By]
    • >>   __0printf$bare
+
    
+
    
+
    
+Undefined Global Symbols
+
    
diff --git a/RVMDK/Obj/Printf_PC.lnp b/RVMDK/Obj/Printf_PC.lnp
new file mode 100644
index 0000000..237bd84
--- /dev/null
+++ b/RVMDK/Obj/Printf_PC.lnp
@@ -0,0 +1,28 @@
+--cpu Cortex-M3
+".\obj\printf.o"
+".\obj\delay.o"
+".\obj\main.o"
+".\obj\nrf24l01.o"
+".\obj\tim.o"
+".\obj\spi.o"
+".\obj\led.o"
+".\obj\dataproc.o"
+".\obj\usart2.o"
+".\obj\flash.o"
+".\obj\lcd.o"
+".\obj\stm32f10x_it.o"
+".\obj\stm32f10x_rcc.o"
+".\obj\stm32f10x_usart.o"
+".\obj\misc.o"
+".\obj\stm32f10x_gpio.o"
+".\obj\stm32f10x_spi.o"
+".\obj\stm32f10x_tim.o"
+".\obj\stm32f10x_iwdg.o"
+".\obj\stm32f10x_flash.o"
+".\obj\core_cm3.o"
+".\obj\system_stm32f10x.o"
+".\obj\startup_stm32f10x_hd.o"
+--library_type=microlib --strict --scatter ".\Obj\Printf_PC.sct"
+--summary_stderr --info summarysizes --map --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\List\Printf_PC.map" -o .\Obj\Printf_PC.axf
\ No newline at end of file
diff --git a/RVMDK/Obj/Printf_PC.sct b/RVMDK/Obj/Printf_PC.sct
new file mode 100644
index 0000000..668038c
--- /dev/null
+++ b/RVMDK/Obj/Printf_PC.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00006000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/RVMDK/Obj/Printf_PC_sct.Bak b/RVMDK/Obj/Printf_PC_sct.Bak
new file mode 100644
index 0000000..0873d6c
--- /dev/null
+++ b/RVMDK/Obj/Printf_PC_sct.Bak
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00030000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00030000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x0000C000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/RVMDK/Obj/core_cm3.crf b/RVMDK/Obj/core_cm3.crf
new file mode 100644
index 0000000..cb98389
Binary files /dev/null and b/RVMDK/Obj/core_cm3.crf differ
diff --git a/RVMDK/Obj/core_cm3.d b/RVMDK/Obj/core_cm3.d
new file mode 100644
index 0000000..eeabbb1
--- /dev/null
+++ b/RVMDK/Obj/core_cm3.d
@@ -0,0 +1,2 @@
+.\obj\core_cm3.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+.\obj\core_cm3.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
diff --git a/RVMDK/Obj/core_cm3.o b/RVMDK/Obj/core_cm3.o
new file mode 100644
index 0000000..24a2ab3
Binary files /dev/null and b/RVMDK/Obj/core_cm3.o differ
diff --git a/RVMDK/Obj/dataproc.crf b/RVMDK/Obj/dataproc.crf
new file mode 100644
index 0000000..b5b5730
Binary files /dev/null and b/RVMDK/Obj/dataproc.crf differ
diff --git a/RVMDK/Obj/dataproc.d b/RVMDK/Obj/dataproc.d
new file mode 100644
index 0000000..303f471
--- /dev/null
+++ b/RVMDK/Obj/dataproc.d
@@ -0,0 +1,44 @@
+.\obj\dataproc.o: ..\bsp\DataProc.c
+.\obj\dataproc.o: ..\bsp\DataProc.h
+.\obj\dataproc.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\dataproc.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\dataproc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\dataproc.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\dataproc.o: ..\Libraries\stm32f10x_conf.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\dataproc.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\dataproc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\dataproc.o: ..\bsp\nrf24L01.h
+.\obj\dataproc.o: ..\bsp\nrf_gpio.h
+.\obj\dataproc.o: ..\bsp\spi.h
+.\obj\dataproc.o: ..\bsp\printf.h
+.\obj\dataproc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\dataproc.o: ..\bsp\printf.h
+.\obj\dataproc.o: ..\bsp\delay.h
+.\obj\dataproc.o: ..\bsp\led.h
+.\obj\dataproc.o: ..\bsp\USART2.h
+.\obj\dataproc.o: ..\bsp\stmflash.h
+.\obj\dataproc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
+.\obj\dataproc.o: ..\bsp\flash.h
+.\obj\dataproc.o: ..\bsp\LCD.h
diff --git a/RVMDK/Obj/dataproc.o b/RVMDK/Obj/dataproc.o
new file mode 100644
index 0000000..5d6ad78
Binary files /dev/null and b/RVMDK/Obj/dataproc.o differ
diff --git a/RVMDK/Obj/delay.crf b/RVMDK/Obj/delay.crf
new file mode 100644
index 0000000..d0aee75
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diff --git a/RVMDK/Obj/delay.d b/RVMDK/Obj/delay.d
new file mode 100644
index 0000000..bf9941b
--- /dev/null
+++ b/RVMDK/Obj/delay.d
@@ -0,0 +1,31 @@
+.\obj\delay.o: ..\bsp\delay.c
+.\obj\delay.o: ..\bsp\delay.h
+.\obj\delay.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\delay.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\delay.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\delay.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\delay.o: ..\Libraries\stm32f10x_conf.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\delay.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\delay.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/RVMDK/Obj/delay.o b/RVMDK/Obj/delay.o
new file mode 100644
index 0000000..9fbe288
Binary files /dev/null and b/RVMDK/Obj/delay.o differ
diff --git a/RVMDK/Obj/flash.crf b/RVMDK/Obj/flash.crf
new file mode 100644
index 0000000..cdaf85e
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diff --git a/RVMDK/Obj/flash.d b/RVMDK/Obj/flash.d
new file mode 100644
index 0000000..a4b08b6
--- /dev/null
+++ b/RVMDK/Obj/flash.d
@@ -0,0 +1,34 @@
+.\obj\flash.o: ..\bsp\flash.c
+.\obj\flash.o: ..\bsp\flash.h
+.\obj\flash.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\flash.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\flash.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\flash.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\flash.o: ..\Libraries\stm32f10x_conf.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\flash.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\flash.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\flash.o: ..\bsp\printf.h
+.\obj\flash.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\flash.o: ..\bsp\printf.h
diff --git a/RVMDK/Obj/flash.o b/RVMDK/Obj/flash.o
new file mode 100644
index 0000000..0099222
Binary files /dev/null and b/RVMDK/Obj/flash.o differ
diff --git a/RVMDK/Obj/lcd.crf b/RVMDK/Obj/lcd.crf
new file mode 100644
index 0000000..6adf96a
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diff --git a/RVMDK/Obj/lcd.d b/RVMDK/Obj/lcd.d
new file mode 100644
index 0000000..02443d9
--- /dev/null
+++ b/RVMDK/Obj/lcd.d
@@ -0,0 +1,31 @@
+.\obj\lcd.o: ..\bsp\LCD.c
+.\obj\lcd.o: ..\bsp\LCD.h
+.\obj\lcd.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\lcd.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\lcd.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\lcd.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\lcd.o: ..\Libraries\stm32f10x_conf.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\lcd.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\lcd.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/RVMDK/Obj/lcd.o b/RVMDK/Obj/lcd.o
new file mode 100644
index 0000000..88fd534
Binary files /dev/null and b/RVMDK/Obj/lcd.o differ
diff --git a/RVMDK/Obj/led.crf b/RVMDK/Obj/led.crf
new file mode 100644
index 0000000..364ca15
Binary files /dev/null and b/RVMDK/Obj/led.crf differ
diff --git a/RVMDK/Obj/led.d b/RVMDK/Obj/led.d
new file mode 100644
index 0000000..981fd9e
--- /dev/null
+++ b/RVMDK/Obj/led.d
@@ -0,0 +1,31 @@
+.\obj\led.o: ..\bsp\LED.c
+.\obj\led.o: ..\bsp\LED.h
+.\obj\led.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\led.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\led.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\led.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\led.o: ..\Libraries\stm32f10x_conf.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\led.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\led.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/RVMDK/Obj/led.o b/RVMDK/Obj/led.o
new file mode 100644
index 0000000..52d67c3
Binary files /dev/null and b/RVMDK/Obj/led.o differ
diff --git a/RVMDK/Obj/main.crf b/RVMDK/Obj/main.crf
new file mode 100644
index 0000000..5df8b6a
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diff --git a/RVMDK/Obj/main.d b/RVMDK/Obj/main.d
new file mode 100644
index 0000000..175c13b
--- /dev/null
+++ b/RVMDK/Obj/main.d
@@ -0,0 +1,44 @@
+.\obj\main.o: ..\bsp\main.c
+.\obj\main.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\main.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\main.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\main.o: ..\Libraries\stm32f10x_conf.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\main.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\main.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\main.o: ..\bsp\printf.h
+.\obj\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\main.o: ..\bsp\printf.h
+.\obj\main.o: ..\bsp\USART2.h
+.\obj\main.o: ..\bsp\LED.h
+.\obj\main.o: ..\bsp\delay.h
+.\obj\main.o: ..\bsp\nrf24L01.h
+.\obj\main.o: ..\bsp\nrf_gpio.h
+.\obj\main.o: ..\bsp\spi.h
+.\obj\main.o: ..\bsp\DataProc.h
+.\obj\main.o: ..\bsp\stmflash.h
+.\obj\main.o: ..\bsp\tim.h
+.\obj\main.o: ..\bsp\flash.h
+.\obj\main.o: ..\bsp\LCD.h
diff --git a/RVMDK/Obj/main.o b/RVMDK/Obj/main.o
new file mode 100644
index 0000000..4257fd9
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diff --git a/RVMDK/Obj/misc.crf b/RVMDK/Obj/misc.crf
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index 0000000..3d12ff7
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diff --git a/RVMDK/Obj/misc.d b/RVMDK/Obj/misc.d
new file mode 100644
index 0000000..b843267
--- /dev/null
+++ b/RVMDK/Obj/misc.d
@@ -0,0 +1,31 @@
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\misc.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\misc.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\misc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\misc.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\misc.o: ..\Libraries\stm32f10x_conf.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\misc.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\misc.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/RVMDK/Obj/misc.o b/RVMDK/Obj/misc.o
new file mode 100644
index 0000000..18622ae
Binary files /dev/null and b/RVMDK/Obj/misc.o differ
diff --git a/RVMDK/Obj/nrf24l01.crf b/RVMDK/Obj/nrf24l01.crf
new file mode 100644
index 0000000..d0d86e3
Binary files /dev/null and b/RVMDK/Obj/nrf24l01.crf differ
diff --git a/RVMDK/Obj/nrf24l01.d b/RVMDK/Obj/nrf24l01.d
new file mode 100644
index 0000000..16266d3
--- /dev/null
+++ b/RVMDK/Obj/nrf24l01.d
@@ -0,0 +1,37 @@
+.\obj\nrf24l01.o: ..\bsp\nrf24L01.c
+.\obj\nrf24l01.o: ..\bsp\nrf24L01.h
+.\obj\nrf24l01.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\nrf24l01.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\nrf24l01.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\nrf24l01.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\nrf24l01.o: ..\Libraries\stm32f10x_conf.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\nrf24l01.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\nrf24l01.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\nrf24l01.o: ..\bsp\nrf_gpio.h
+.\obj\nrf24l01.o: ..\bsp\spi.h
+.\obj\nrf24l01.o: ..\bsp\printf.h
+.\obj\nrf24l01.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\nrf24l01.o: ..\bsp\printf.h
+.\obj\nrf24l01.o: ..\bsp\delay.h
diff --git a/RVMDK/Obj/nrf24l01.o b/RVMDK/Obj/nrf24l01.o
new file mode 100644
index 0000000..faf0355
Binary files /dev/null and b/RVMDK/Obj/nrf24l01.o differ
diff --git a/RVMDK/Obj/printf.crf b/RVMDK/Obj/printf.crf
new file mode 100644
index 0000000..0195f2d
Binary files /dev/null and b/RVMDK/Obj/printf.crf differ
diff --git a/RVMDK/Obj/printf.d b/RVMDK/Obj/printf.d
new file mode 100644
index 0000000..7aa3ba3
--- /dev/null
+++ b/RVMDK/Obj/printf.d
@@ -0,0 +1,33 @@
+.\obj\printf.o: ..\bsp\printf.c
+.\obj\printf.o: ..\bsp\printf.h
+.\obj\printf.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\printf.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\printf.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\printf.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\printf.o: ..\Libraries\stm32f10x_conf.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\printf.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\printf.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\printf.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\printf.o: ..\bsp\printf.h
diff --git a/RVMDK/Obj/printf.o b/RVMDK/Obj/printf.o
new file mode 100644
index 0000000..642a26a
Binary files /dev/null and b/RVMDK/Obj/printf.o differ
diff --git a/RVMDK/Obj/spi.crf b/RVMDK/Obj/spi.crf
new file mode 100644
index 0000000..cce8b68
Binary files /dev/null and b/RVMDK/Obj/spi.crf differ
diff --git a/RVMDK/Obj/spi.d b/RVMDK/Obj/spi.d
new file mode 100644
index 0000000..a3389b6
--- /dev/null
+++ b/RVMDK/Obj/spi.d
@@ -0,0 +1,31 @@
+.\obj\spi.o: ..\bsp\spi.c
+.\obj\spi.o: ..\bsp\spi.h
+.\obj\spi.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\spi.o: ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h
+.\obj\spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\spi.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h
+.\obj\spi.o: ..\Libraries\stm32f10x_conf.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\spi.o: ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h
+.\obj\spi.o: ..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/RVMDK/Obj/spi.o b/RVMDK/Obj/spi.o
new file mode 100644
index 0000000..b8ca856
Binary files /dev/null and b/RVMDK/Obj/spi.o differ
diff --git a/RVMDK/Obj/sscom.ini b/RVMDK/Obj/sscom.ini
new file mode 100644
index 0000000..6a8a977
--- /dev/null
+++ b/RVMDK/Obj/sscom.ini
@@ -0,0 +1,67 @@
+;SSCOMñļ,ڳúõĴڲַݶԶ,òҪⲿ༭Ķļ!
+;ļ޸ĺܴ,ɾļ,򽫻Զһµiniļ.
+;׵İǷֺעͷ
+;ÿжԻس
+
+;ǰںPort
+N80=,COM16
+;Band rate
+N81=,38400
+;λData bits
+N82=,8
+;ֹͣλStop bits
+N83=,1
+;УλParity
+;N84=,޷,
+;Flow control
+;N85=,޷,
+
+;"="HʾǸHEXݴ
+;"="AʾǸASCַ
+;Nxʾڼַ(1
+
+
    +
    Vision Build Log
    
+
    Project:
    
+E:\ѧϰר\»\\VC\CreativeST_VC\Printf\RVMDK\Printf.uvproj
+Project File Date:  05/20/2011
+
+
    Output:
    
+Build target 'CreativeST_VC'
+compiling stm32f10x_it.c...
+..\stm32f10x_it.c(135): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(36): error:  #1268-D: declaration aliased to undefined entity "SysTickHandler"
+..\stm32f10x_it.c(126): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(35): error:  #1268-D: declaration aliased to undefined entity "PendSVC"
+..\stm32f10x_it.c(108): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(34): error:  #1268-D: declaration aliased to undefined entity "SVCHandler"
+..\stm32f10x_it.c(117): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(33): error:  #1268-D: declaration aliased to undefined entity "DebugMonitor"
+..\stm32f10x_it.c(95): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(32): error:  #1268-D: declaration aliased to undefined entity "UsageFaultException"
+..\stm32f10x_it.c(82): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(31): error:  #1268-D: declaration aliased to undefined entity "BusFaultException"
+..\stm32f10x_it.c(69): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(30): error:  #1268-D: declaration aliased to undefined entity "MemManageException"
+..\stm32f10x_it.c(56): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(29): error:  #1268-D: declaration aliased to undefined entity "HardFaultException"
+..\stm32f10x_it.c(47): error:  #1270: entity declared as alias cannot have definition
+D:\Program Files\keil 4.10\ARM\INC\ST\STM32F10x\stm32f10x_it.h(28): error:  #1268-D: declaration aliased to undefined entity "NMIException"
+compiling main.c...
+compiling printf.c...
+..\printf.c(47): error:  #20: identifier "USART_InitTypeDef" is undefined
+..\printf.c(49): error:  #20: identifier "GPIO_InitTypeDef" is undefined
+..\printf.c(52): warning:  #223-D: function "RCC_APB2PeriphClockCmd" declared implicitly
+..\printf.c(52): error:  #20: identifier "RCC_APB2Periph_USART1" is undefined
+..\printf.c(52): error:  #20: identifier "RCC_APB2Periph_GPIOA" is undefined
+..\printf.c(55): error:  #20: identifier "GPIO_Pin_9" is undefined
+..\printf.c(56): error:  #20: identifier "GPIO_Speed_50MHz" is undefined
+..\printf.c(57): error:  #20: identifier "GPIO_Mode_AF_PP" is undefined
+..\printf.c(58): warning:  #223-D: function "GPIO_Init" declared implicitly
+..\printf.c(61): error:  #20: identifier "GPIO_Pin_10" is undefined
+..\printf.c(62): error:  #20: identifier "GPIO_Mode_IN_FLOATING" is undefined
+..\printf.c(67): error:  #20: identifier "USART_WordLength_8b" is undefined
+..\printf.c(68): error:  #20: identifier "USART_StopBits_1" is undefined
+..\printf.c(69): error:  #20: identifier "USART_Parity_No" is undefined
+..\printf.c(70): error:  #20: identifier "USART_HardwareFlowControl_None" is undefined
+..\printf.c(71): error:  #20: identifier "USART_Mode_Tx" is undefined
+..\printf.c(71): error:  #20: identifier "USART_Mode_Rx" is undefined
+..\printf.c(72): warning:  #223-D: function "USART_Init" declared implicitly
+..\printf.c(78): warning:  #223-D: function "USART_Cmd" declared implicitly
+..\printf.c(82): warning:  #223-D: function "USART_ClearFlag" declared implicitly
+..\printf.c(82): error:  #20: identifier "USART_FLAG_TC" is undefined
+..\printf.c(98): warning:  #223-D: function "USART_GetFlagStatus" declared implicitly
+..\printf.c(98): error:  #20: identifier "USART_FLAG_TC" is undefined
+..\printf.c(101): warning:  #223-D: function "USART_SendData" declared implicitly
+..\printf.c(122): warning:  #223-D: function "USART_GetFlagStatus" declared implicitly
+..\printf.c(122): error:  #20: identifier "USART_FLAG_TC" is undefined
+compiling stm32f10x_rcc.c...
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(272): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(337): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(356): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(382): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(403): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(567): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(611): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(637): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(663): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(702): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(730): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(769): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(831): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(864): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(881): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(895): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1066): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1097): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1128): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1187): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1218): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1239): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1252): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1284): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1331): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1405): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c(1450): warning:  #223-D: function "assert_param" declared implicitly
+compiling stm32f10x_usart.c...
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(131): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(181): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(303): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(351): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(390): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(448): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(476): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(499): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(518): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(547): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(566): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(592): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(609): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(625): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(641): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(661): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(680): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(705): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(731): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(762): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(789): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(818): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(837): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(875): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(923): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(958): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c(1031): warning:  #223-D: function "assert_param" declared implicitly
+compiling misc.c...
+..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c(98): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c(116): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c(157): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c(176): warning:  #223-D: function "assert_param" declared implicitly
+..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c(200): warning:  #223-D: function "assert_param" declared implicitly
+compiling system_stm32f10x.c...
+compiling core_cm3.c...
+assembling startup_stm32f10x_hd.s...
+Target not created
diff --git a/RVMDK/Printf.uvgui.Administrator b/RVMDK/Printf.uvgui.Administrator
new file mode 100644
index 0000000..a0837d9
--- /dev/null
+++ b/RVMDK/Printf.uvgui.Administrator
@@ -0,0 +1,2815 @@
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diff --git a/RVMDK/Printf.uvgui.woody b/RVMDK/Printf.uvgui.woody
new file mode 100644
index 0000000..5902abd
--- /dev/null
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diff --git a/RVMDK/Printf.uvguix.Administrator b/RVMDK/Printf.uvguix.Administrator
new file mode 100644
index 0000000..5cf185f
--- /dev/null
+++ b/RVMDK/Printf.uvguix.Administrator
@@ -0,0 +1,2700 @@
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diff --git a/RVMDK/Printf.uvguix.FS_BJB15018 b/RVMDK/Printf.uvguix.FS_BJB15018
new file mode 100644
index 0000000..5aa63c6
--- /dev/null
+++ b/RVMDK/Printf.uvguix.FS_BJB15018
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diff --git a/RVMDK/Printf.uvguix.tel b/RVMDK/Printf.uvguix.tel
new file mode 100644
index 0000000..dafa52f
--- /dev/null
+++ b/RVMDK/Printf.uvguix.tel
@@ -0,0 +1,2646 @@
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+
+  -5.1
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+  
    ### uVision Project, (C) Keil Software
    
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+      Registers
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+      665 517
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+    
+      204
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diff --git a/RVMDK/Printf.uvguix_Administrator.bak b/RVMDK/Printf.uvguix_Administrator.bak
new file mode 100644
index 0000000..9204cad
--- /dev/null
+++ b/RVMDK/Printf.uvguix_Administrator.bak
@@ -0,0 +1,2635 @@
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diff --git a/RVMDK/Printf.uvopt b/RVMDK/Printf.uvopt
new file mode 100644
index 0000000..0784b7b
--- /dev/null
+++ b/RVMDK/Printf.uvopt
@@ -0,0 +1,646 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    CreativeST_VC
+    0x4
+    ARM-ADS
+    
+      24000000
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+        
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+        
+        
+        
+        
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+        Segger\JL2CM3.dll
+      
+      
+        
+          0
+          ST-LINKIII-KEIL
+          -S
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          /
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O206 -O206 -S3 -C0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000
+        
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+          JL2CM3
+          -U20090928 -O78 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000
+        
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+          -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0STM32F10x_512 -FL080000 -FS08000000 -FP0($$Device:STM32F100RC$Flash/STM32F10x_512.FLM)
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    134219494
    
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+          
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diff --git a/RVMDK/Printf.uvoptx b/RVMDK/Printf.uvoptx
new file mode 100644
index 0000000..9b2a740
--- /dev/null
+++ b/RVMDK/Printf.uvoptx
@@ -0,0 +1,592 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
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+        
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diff --git a/RVMDK/Printf.uvproj.saved_uv4 b/RVMDK/Printf.uvproj.saved_uv4
new file mode 100644
index 0000000..a3bd40b
--- /dev/null
+++ b/RVMDK/Printf.uvproj.saved_uv4
@@ -0,0 +1,556 @@
+
+
+
+  1.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CreativeST_VC
+      0x4
+      ARM-ADS
+      
+        
+          STM32F100RC
+          STMicroelectronics
+          IROM(0x08000000,0x40000) IRAM(0x20000000,0x6000) CPUTYPE("Cortex-M3") CLOCK(24000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F100RC$Flash/STM32F10x_512.FLM))
+          5311
+          $$Device:STM32F100RC$Device/Include/stm32f10x.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F100RC$SVD/STM32F100xx.svd
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+          
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+          
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+          
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+            "C:\Keil_v5\ARM\ARMCC\bin\fromelf.exe" --bin -o  ..\RVMDK\obj\Printf_PC.bin  ..\RVMDK\obj\Printf_PC.axf
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+          -REMAP
+          DCM.DLL
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+        
+          
+            1
+            0
+            0
+            1
+            1
+            4099
+          
+          0
+          Segger\JL2CM3.dll
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
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+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M3"
+            
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+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            8
+            1
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+            0
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+            1
+            0
+            
+              
+                0
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+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x6000
+              
+              
+                1
+                0x8000000
+                0x40000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x40000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x6000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            0
+            0
+            
+              
+              USE_STDPERIPH_DRIVER, STM32F10X_HD_VL
+              
+              ..\;..\Libraries\CMSIS\CM3\CoreSupport;..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\bsp;..\Libraries
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          User
+          
+            
+              main.c
+              1
+              ..\bsp\main.c
+            
+            
+              printf.c
+              1
+              ..\bsp\printf.c
+            
+            
+              delay.c
+              1
+              ..\bsp\delay.c
+            
+            
+              nrf24L01.c
+              1
+              ..\bsp\nrf24L01.c
+            
+            
+              tim.c
+              1
+              ..\bsp\tim.c
+            
+            
+              spi.c
+              1
+              ..\bsp\spi.c
+            
+            
+              LED.c
+              1
+              ..\bsp\LED.c
+            
+            
+              DataProc.c
+              1
+              ..\bsp\DataProc.c
+            
+            
+              USART2.c
+              1
+              ..\bsp\USART2.c
+            
+            
+              flash.c
+              1
+              ..\bsp\flash.c
+            
+            
+              LCD.c
+              1
+              ..\bsp\LCD.c
+            
+          
+        
+        
+          StdPeriph_Driver
+          
+            
+              stm32f10x_it.c
+              1
+              ..\Libraries\stm32f10x_it.c
+            
+            
+              stm32f10x_rcc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+            
+            
+              stm32f10x_usart.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+            
+            
+              misc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+            
+            
+              stm32f10x_gpio.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+            
+            
+              stm32f10x_spi.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+            
+            
+              stm32f10x_tim.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+            
+            
+              stm32f10x_iwdg.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c
+            
+            
+              stm32f10x_flash.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+            
+          
+        
+        
+          CMSIS
+          
+            
+              core_cm3.c
+              1
+              ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+            
+            
+              system_stm32f10x.c
+              1
+              ..\Libraries\system_stm32f10x.c
+            
+          
+        
+        
+          MDK-ARM
+          
+            
+              startup_stm32f10x_hd.s
+              2
+              ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s
+            
+          
+        
+        
+          Doc
+          
+            
+              说明.txt
+              5
+              ..\说明.txt
+            
+          
+        
+      
+    
+  
+
+    
diff --git a/RVMDK/Printf.uvprojx b/RVMDK/Printf.uvprojx
new file mode 100644
index 0000000..6d85212
--- /dev/null
+++ b/RVMDK/Printf.uvprojx
@@ -0,0 +1,547 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CreativeST_VC
+      0x4
+      ARM-ADS
+      5060061::V5.06 update 1 (build 61)::ARMCC
+      0
+      
+        
+          STM32F100RC
+          STMicroelectronics
+          Keil.STM32F1xx_DFP.2.2.0
+          http://www.keil.com/pack/
+          IROM(0x08000000,0x40000) IRAM(0x20000000,0x6000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F100RC$Flash\STM32F10x_512.FLM))
+          5311
+          $$Device:STM32F100RC$Device\Include\stm32f10x.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F100RC$SVD\STM32F100xx.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Obj\
+          Printf_PC
+          1
+          0
+          1
+          1
+          1
+          .\List\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            "C:\Keil_v5\ARM\ARMCC\bin\fromelf.exe" --bin -o  ..\RVMDK\obj\Printf_PC.bin  ..\RVMDK\obj\Printf_PC.axf
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+          -REMAP
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4099
+          
+          0
+          Segger\JL2CM3.dll
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
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+            1
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+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M3"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            8
+            1
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+            3
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+            0
+            0
+            0
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+            0
+            1
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+            0
+            0
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+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
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+                0x0
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+              
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+                0x0
+              
+              
+                0
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+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x6000
+              
+              
+                1
+                0x8000000
+                0x40000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x40000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x6000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            0
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+            0
+            0
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_STDPERIPH_DRIVER, STM32F10X_HD_VL
+              
+              ..\;..\Libraries\CMSIS\CM3\CoreSupport;..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\bsp;..\Libraries
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          User
+          
+            
+              printf.c
+              1
+              ..\bsp\printf.c
+            
+            
+              delay.c
+              1
+              ..\bsp\delay.c
+            
+            
+              main.c
+              1
+              ..\bsp\main.c
+            
+            
+              nrf24L01.c
+              1
+              ..\bsp\nrf24L01.c
+            
+            
+              tim.c
+              1
+              ..\bsp\tim.c
+            
+            
+              spi.c
+              1
+              ..\bsp\spi.c
+            
+            
+              LED.c
+              1
+              ..\bsp\LED.c
+            
+            
+              DataProc.c
+              1
+              ..\bsp\DataProc.c
+            
+            
+              USART2.c
+              1
+              ..\bsp\USART2.c
+            
+            
+              flash.c
+              1
+              ..\bsp\flash.c
+            
+            
+              LCD.c
+              1
+              ..\bsp\LCD.c
+            
+          
+        
+        
+          StdPeriph_Driver
+          
+            
+              stm32f10x_it.c
+              1
+              ..\Libraries\stm32f10x_it.c
+            
+            
+              stm32f10x_rcc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+            
+            
+              stm32f10x_usart.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+            
+            
+              misc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+            
+            
+              stm32f10x_gpio.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+            
+            
+              stm32f10x_spi.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+            
+            
+              stm32f10x_tim.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+            
+            
+              stm32f10x_iwdg.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c
+            
+            
+              stm32f10x_flash.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+            
+          
+        
+        
+          CMSIS
+          
+            
+              core_cm3.c
+              1
+              ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+            
+            
+              system_stm32f10x.c
+              1
+              ..\Libraries\system_stm32f10x.c
+            
+          
+        
+        
+          MDK-ARM
+          
+            
+              startup_stm32f10x_hd.s
+              2
+              ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s
+            
+          
+        
+        
+          Doc
+          
+            
+              说明.txt
+              5
+              ..\说明.txt
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/RVMDK/Printf_Coder003.dep b/RVMDK/Printf_Coder003.dep
new file mode 100644
index 0000000..88974a5
--- /dev/null
+++ b/RVMDK/Printf_Coder003.dep
@@ -0,0 +1,499 @@
+Dependencies for Project 'Printf', Target 'Coder003': (DO NOT MODIFY !)
+F (..\bsp\main.c)(0x593A0E96)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\main.o --omf_browse .\obj\main.crf --depend .\obj\main.d)
+I (E:\code\003\д\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x4DA03596)
+I (E:\code\003\д\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x4CBC3900)
+I (C:\Program Files (x86)\keil 5\ARM\ARMCC\include\stdint.h)(0x51C7B744)
+I (E:\code\003\д\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x4CBC3900)
+I (E:\code\003\д\Libraries\stm32f10x_conf.h)(0x4DB8C12A)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4CBC3904)
+I (E:\code\003\д\bsp\printf.h)(0x5939FA02)
+I (C:\Program Files (x86)\keil 5\ARM\ARMCC\include\stdio.h)(0x51C7B744)
+I (E:\code\003\д\bsp\USART2.h)(0x593DF243)
+I (E:\code\003\д\bsp\LED.h)(0x59390169)
+I (E:\code\003\д\bsp\delay.h)(0x593902C3)
+I (E:\code\003\д\bsp\nrf24L01.h)(0x593A1649)
+I (E:\code\003\д\bsp\nrf_gpio.h)(0x5938C2F1)
+I (E:\code\003\д\bsp\spi.h)(0x5938EC44)
+I (E:\code\003\д\bsp\DataProc.h)(0x593A09AA)
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-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\dataproc.o --omf_browse .\obj\dataproc.crf --depend .\obj\dataproc.d)
+I (E:\code\003\д\bsp\DataProc.h)(0x593A09AA)
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+I (E:\code\003\д\bsp\spi.h)(0x5938EC44)
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-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\nrf24l01.o --omf_browse .\obj\nrf24l01.crf --depend .\obj\nrf24l01.d)
+I (E:\code\003\д\bsp\nrf24L01.h)(0x593A1649)
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-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\delay.o --omf_browse .\obj\delay.crf --depend .\obj\delay.d)
+I (E:\code\003\д\bsp\delay.h)(0x593902C3)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\led.o --omf_browse .\obj\led.crf --depend .\obj\led.d)
+I (E:\code\003\д\bsp\LED.h)(0x59390169)
+I (E:\code\003\д\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x4DA03596)
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-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\printf.o --omf_browse .\obj\printf.crf --depend .\obj\printf.d)
+I (E:\code\003\д\bsp\printf.h)(0x5939FA02)
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-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\spi.o --omf_browse .\obj\spi.crf --depend .\obj\spi.d)
+I (E:\code\003\д\bsp\spi.h)(0x5938EC44)
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-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\usart2.o --omf_browse .\obj\usart2.crf --depend .\obj\usart2.d)
+I (E:\code\003\д\bsp\USART2.h)(0x593DF243)
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-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\stmflash.o --omf_browse .\obj\stmflash.crf --depend .\obj\stmflash.d)
+I (E:\code\003\д\bsp\stmflash.h)(0x593E04C9)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\stm32f10x_it.o --omf_browse .\obj\stm32f10x_it.crf --depend .\obj\stm32f10x_it.d)
+I (E:\code\003\д\Libraries\stm32f10x_it.h)(0x4CBC5B58)
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-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\stm32f10x_rcc.o --omf_browse .\obj\stm32f10x_rcc.crf --depend .\obj\stm32f10x_rcc.d)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4CBC3904)
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+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4CBC3904)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\stm32f10x_usart.o --omf_browse .\obj\stm32f10x_usart.crf --depend .\obj\stm32f10x_usart.d)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x4DA03596)
+I (E:\code\003\д\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x4CBC3900)
+I (C:\Program Files (x86)\keil 5\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\misc.o --omf_browse .\obj\misc.crf --depend .\obj\misc.d)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4CBC3904)
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+I (C:\Program Files (x86)\keil 5\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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+I (E:\code\003\д\Libraries\stm32f10x_conf.h)(0x4DB8C12A)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\stm32f10x_gpio.o --omf_browse .\obj\stm32f10x_gpio.crf --depend .\obj\stm32f10x_gpio.d)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x4DA03596)
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+I (C:\Program Files (x86)\keil 5\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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+I (E:\code\003\д\Libraries\stm32f10x_conf.h)(0x4DB8C12A)
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+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x4CBC3904)
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+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4CBC3904)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\stm32f10x_spi.o --omf_browse .\obj\stm32f10x_spi.crf --depend .\obj\stm32f10x_spi.d)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4CBC3904)
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+I (C:\Program Files (x86)\keil 5\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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+I (E:\code\003\д\Libraries\stm32f10x_conf.h)(0x4DB8C12A)
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+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x4CBC3904)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\core_cm3.o --omf_browse .\obj\core_cm3.crf --depend .\obj\core_cm3.d)
+I (C:\Program Files (x86)\keil 5\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

-DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD -o .\obj\system_stm32f10x.o --omf_browse .\obj\system_stm32f10x.crf --depend .\obj\system_stm32f10x.d)
+I (E:\code\003\д\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x4DA03596)
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+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x4CBC3904)
+I (E:\code\003\д\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4CBC3904)
+F (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s)(0x4CBC3902)(--cpu Cortex-M3 -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I "C:\Program Files (x86)\keil 5\ARM\RV31\INC"

-I "C:\Program Files (x86)\keil 5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include"

-I "C:\Program Files (x86)\keil 5\ARM\Inc\ST\STM32F10x"

--list .\list\startup_stm32f10x_hd.lst --xref -o .\obj\startup_stm32f10x_hd.o --depend .\obj\startup_stm32f10x_hd.d)
+F (..\˵.txt)(0x593923FB)()
diff --git a/RVMDK/Printf_CreativeST_VC.dep b/RVMDK/Printf_CreativeST_VC.dep
new file mode 100644
index 0000000..0bd3ef8
--- /dev/null
+++ b/RVMDK/Printf_CreativeST_VC.dep
@@ -0,0 +1,658 @@
+Dependencies for Project 'Printf', Target 'CreativeST_VC': (DO NOT MODIFY !)
+F (..\bsp\main.c)(0x5AB51718)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\main.o --omf_browse .\obj\main.crf --depend .\obj\main.d)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\printf.h)(0x5A45F82F)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (..\bsp\USART2.h)(0x59926A43)
+I (..\bsp\LED.h)(0x59926A43)
+I (..\bsp\delay.h)(0x5A547551)
+I (..\bsp\nrf24L01.h)(0x5A559D9D)
+I (..\bsp\nrf_gpio.h)(0x5AB2098B)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\bsp\DataProc.h)(0x59C34BC1)
+I (..\bsp\stmflash.h)(0x59C5CBBC)
+I (..\bsp\tim.h)(0x59926A43)
+I (..\bsp\flash.h)(0x598BC710)
+I (..\bsp\LCD.h)(0x5AC11E14)
+F (..\bsp\printf.c)(0x5A45F7AF)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\printf.o --omf_browse .\obj\printf.crf --depend .\obj\printf.d)
+I (..\bsp\printf.h)(0x5A45F82F)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+F (..\bsp\delay.c)(0x5AAF6F3E)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\delay.o --omf_browse .\obj\delay.crf --depend .\obj\delay.d)
+I (..\bsp\delay.h)(0x5A547551)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\nrf24L01.c)(0x5AB51721)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\nrf24l01.o --omf_browse .\obj\nrf24l01.crf --depend .\obj\nrf24l01.d)
+I (..\bsp\nrf24L01.h)(0x5A559D9D)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\nrf_gpio.h)(0x5AB2098B)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\bsp\printf.h)(0x5A45F82F)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (..\bsp\delay.h)(0x5A547551)
+F (..\bsp\tim.c)(0x59926A43)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\tim.o --omf_browse .\obj\tim.crf --depend .\obj\tim.d)
+I (..\bsp\tim.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\spi.c)(0x59C4A827)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\spi.o --omf_browse .\obj\spi.crf --depend .\obj\spi.d)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\LED.c)(0x59926A43)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\led.o --omf_browse .\obj\led.crf --depend .\obj\led.d)
+I (..\bsp\LED.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\DataProc.c)(0x5AAFA42B)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\dataproc.o --omf_browse .\obj\dataproc.crf --depend .\obj\dataproc.d)
+I (..\bsp\DataProc.h)(0x59C34BC1)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\nrf24L01.h)(0x5A559D9D)
+I (..\bsp\nrf_gpio.h)(0x5AB2098B)
+I (..\bsp\spi.h)(0x59926A43)
+I (..\bsp\printf.h)(0x5A45F82F)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (..\bsp\delay.h)(0x5A547551)
+I (..\bsp\led.h)(0x59926A43)
+I (..\bsp\USART2.h)(0x59926A43)
+I (..\bsp\stmflash.h)(0x59C5CBBC)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (..\bsp\flash.h)(0x598BC710)
+I (..\bsp\LCD.h)(0x5AC11E14)
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-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\usart2.o --omf_browse .\obj\usart2.crf --depend .\obj\usart2.d)
+I (..\bsp\USART2.h)(0x59926A43)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\bsp\flash.c)(0x59C5BD9B)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\flash.o --omf_browse .\obj\flash.crf --depend .\obj\flash.d)
+I (..\bsp\flash.h)(0x598BC710)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\bsp\printf.h)(0x5A45F82F)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+F (..\bsp\LCD.c)(0x5AC11D8A)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\lcd.o --omf_browse .\obj\lcd.crf --depend .\obj\lcd.d)
+I (..\bsp\LCD.h)(0x5AC11E14)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\stm32f10x_it.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_it.o --omf_browse .\obj\stm32f10x_it.crf --depend .\obj\stm32f10x_it.d)
+I (..\Libraries\stm32f10x_it.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c)(0x5AA93522)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_rcc.o --omf_browse .\obj\stm32f10x_rcc.crf --depend .\obj\stm32f10x_rcc.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_usart.o --omf_browse .\obj\stm32f10x_usart.crf --depend .\obj\stm32f10x_usart.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\misc.o --omf_browse .\obj\misc.crf --depend .\obj\misc.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_gpio.o --omf_browse .\obj\stm32f10x_gpio.crf --depend .\obj\stm32f10x_gpio.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_spi.o --omf_browse .\obj\stm32f10x_spi.crf --depend .\obj\stm32f10x_spi.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_tim.o --omf_browse .\obj\stm32f10x_tim.crf --depend .\obj\stm32f10x_tim.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c)(0x59E1E338)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_iwdg.o --omf_browse .\obj\stm32f10x_iwdg.crf --depend .\obj\stm32f10x_iwdg.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c)(0x59C5CC1A)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\stm32f10x_flash.o --omf_browse .\obj\stm32f10x_flash.crf --depend .\obj\stm32f10x_flash.d)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c)(0x59926A40)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\core_cm3.o --omf_browse .\obj\core_cm3.crf --depend .\obj\core_cm3.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+F (..\Libraries\system_stm32f10x.c)(0x59926A41)(-c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I..\ -I..\Libraries\CMSIS\CM3\CoreSupport -I..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\bsp -I..\Libraries

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0

-D_RTE_ -DSTM32F10X_HD_VL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD_VL

-o .\obj\system_stm32f10x.o --omf_browse .\obj\system_stm32f10x.crf --depend .\obj\system_stm32f10x.d)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h)(0x59926A41)
+I (..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.h)(0x59926A40)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.h)(0x59926A41)
+I (..\Libraries\stm32f10x_conf.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x59C3395C)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h)(0x59926A41)
+I (..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x59926A41)
+F (..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s)(0x5A535F2C)(--cpu Cortex-M3 -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I E:\svn\Answer_card\⿨2.4GȶԹ\⿨2.4GȶԹ\⿨2.4GȶԹߣͨð棩\RVMDK\RTE

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.0\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0



--list .\list\startup_stm32f10x_hd.lst --xref -o .\obj\startup_stm32f10x_hd.o --depend .\obj\startup_stm32f10x_hd.d)
+F (..\˵.txt)(0x59926A43)()
diff --git a/RVMDK/Printf_Target 1.dep b/RVMDK/Printf_Target 1.dep
new file mode 100644
index 0000000..32f7e21
--- /dev/null
+++ b/RVMDK/Printf_Target 1.dep	
@@ -0,0 +1 @@
+Dependencies for Project 'Printf', Target 'Target 1': (DO NOT MODIFY !)
diff --git a/RVMDK/Printf_uvopt.bak b/RVMDK/Printf_uvopt.bak
new file mode 100644
index 0000000..c39b741
--- /dev/null
+++ b/RVMDK/Printf_uvopt.bak
@@ -0,0 +1,630 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    CreativeST_VC
+    0x4
+    ARM-ADS
+    
+      24000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\List\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
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+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        0
+        1
+        1
+        1
+        0
+        0
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        BIN\UL2CM3.DLL
+      
+      
+        
+          0
+          ST-LINKIII-KEIL
+          -S
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O206 -O206 -S3 -C0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000
+        
+        
+          0
+          JL2CM3
+          -U20090928 -O78 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000
+        
+        
+          0
+          UL2CM3
+          -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0STM32F10x_512 -FL080000 -FS08000000 -FP0($$Device:STM32F100RC$Flash/STM32F10x_512.FLM)
+        
+      
+      
+        
+          0
+          0
+          911
+          1
+          
    134219494
    
+          0
+          0
+          0
+          0
+          0
+          1
+          E:\svn\Answer_card\麓冒脤芒驴篓2.4G卤脠露脭鹿陇戮脽\麓冒脤芒驴篓2.4G卤脠露脭鹿陇戮脽拢篓脥篓脫脙掳忙拢漏\bsp\DataProc.c
+          
+          \\Printf_PC\../bsp/DataProc.c\911
+            
+        
+          1
+          0
+          1350
+          1
+          
    134221134
    
+          0
+          0
+          0
+          0
+          0
+          1
+          E:\svn\Answer_card\麓冒脤芒驴篓2.4G卤脠露脭鹿陇戮脽\麓冒脤芒驴篓2.4G卤脠露脭鹿陇戮脽拢篓脥篓脫脙掳忙拢漏\bsp\DataProc.c
+          
+          \\Printf_PC\../bsp/DataProc.c\1350
+            
+          
+      
+        
+          0
+          1
+          SPI1_IRQ
+        
+        
+          1
+          1
+          rspFlag
+        
+        
+          2
+          1
+          buffer
+        
+        
+          3
+          1
+          USART1_RX_CNT
+        
+        
+          4
+          1
+          USART1_RX_BUF[20]
+        
+        
+          5
+          1
+          count
+        
+        
+          6
+          1
+          USART3_RX_BUF[0]
+        
+      
+      
+        
+          0
+          2
+          USART1_RX_CNT
+        
+      
+      
+        
+          1
+          0
+          buffer
+        
+      
+      
+        
+          2
+          0
+          USART1_RX_BUF
+        
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
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+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+        
+      
+
+  
+    User
+    1
+    0
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\main.c
+      main.c
+      0
+      0
+    
+    
+      1
+      2
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\printf.c
+      printf.c
+      0
+      0
+    
+    
+      1
+      3
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\delay.c
+      delay.c
+      0
+      0
+    
+    
+      1
+      4
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\nrf24L01.c
+      nrf24L01.c
+      0
+      0
+    
+    
+      1
+      5
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\tim.c
+      tim.c
+      0
+      0
+    
+    
+      1
+      6
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\spi.c
+      spi.c
+      0
+      0
+    
+    
+      1
+      7
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\LED.c
+      LED.c
+      0
+      0
+    
+    
+      1
+      8
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\DataProc.c
+      DataProc.c
+      0
+      0
+    
+    
+      1
+      9
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\USART2.c
+      USART2.c
+      0
+      0
+    
+    
+      1
+      10
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\flash.c
+      flash.c
+      0
+      0
+    
+    
+      1
+      11
+      1
+      0
+      0
+      0
+      0
+      ..\bsp\LCD.c
+      LCD.c
+      0
+      0
+    
+  
+
+  
+    StdPeriph_Driver
+    1
+    0
+    0
+    0
+    
+      2
+      12
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\stm32f10x_it.c
+      stm32f10x_it.c
+      0
+      0
+    
+    
+      2
+      13
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+      stm32f10x_rcc.c
+      0
+      0
+    
+    
+      2
+      14
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+      stm32f10x_usart.c
+      0
+      0
+    
+    
+      2
+      15
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+      misc.c
+      0
+      0
+    
+    
+      2
+      16
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+      stm32f10x_gpio.c
+      0
+      0
+    
+    
+      2
+      17
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+      stm32f10x_spi.c
+      0
+      0
+    
+    
+      2
+      18
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+      stm32f10x_tim.c
+      0
+      0
+    
+    
+      2
+      19
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c
+      stm32f10x_iwdg.c
+      0
+      0
+    
+    
+      2
+      20
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+      stm32f10x_flash.c
+      0
+      0
+    
+  
+
+  
+    CMSIS
+    1
+    0
+    0
+    0
+    
+      3
+      21
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+      core_cm3.c
+      0
+      0
+    
+    
+      3
+      22
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\system_stm32f10x.c
+      system_stm32f10x.c
+      0
+      0
+    
+  
+
+  
+    MDK-ARM
+    1
+    0
+    0
+    0
+    
+      4
+      23
+      2
+      0
+      0
+      0
+      0
+      ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s
+      startup_stm32f10x_hd.s
+      0
+      0
+    
+  
+
+  
+    Doc
+    1
+    0
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+    
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+      0
+      0
+      ..\说明.txt
+      说明.txt
+      0
+      0
+    
+  
+
+    
diff --git a/RVMDK/Printf_uvoptx.bak b/RVMDK/Printf_uvoptx.bak
new file mode 100644
index 0000000..d2fbf7e
--- /dev/null
+++ b/RVMDK/Printf_uvoptx.bak
@@ -0,0 +1,605 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    CreativeST_VC
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\List\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
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+        1
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+        1
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+      
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+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        Segger\JL2CM3.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          ST-LINKIII-KEIL
+          -S
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O206 -O206 -S3 -C0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000
+        
+        
+          0
+          JL2CM3
+          -U20090928 -O78 -S2 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512.FLM -FS08000000 -FL040000 -FP0($$Device:STM32F100RC$Flash\STM32F10x_512.FLM)
+        
+        
+          0
+          UL2CM3
+          -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0STM32F10x_512 -FL080000 -FS08000000 -FP0($$Device:STM32F100RC$Flash\STM32F10x_512.FLM)
+        
+      
+      
+      
+        
+          0
+          1
+          SPI1_IRQ
+        
+        
+          1
+          1
+          rspFlag
+        
+        
+          2
+          1
+          buffer
+        
+        
+          3
+          1
+          USART1_RX_CNT
+        
+        
+          4
+          1
+          USART1_RX_BUF[20]
+        
+        
+          5
+          1
+          count
+        
+        
+          6
+          1
+          USART3_RX_BUF[0]
+        
+      
+      
+        
+          0
+          2
+          USART1_RX_CNT
+        
+      
+      
+        
+          1
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+          ReceiveBuf
+        
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+      
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+          2
+          0
+          USART1_RX_BUF
+        
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+      printf.c
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+      delay.c
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+      nrf24L01.c
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+      tim.c
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+      0
+      0
+      ..\bsp\spi.c
+      spi.c
+      0
+      0
+    
+    
+      1
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+      1
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+      0
+      ..\bsp\LED.c
+      LED.c
+      0
+      0
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+      0
+      ..\bsp\DataProc.c
+      DataProc.c
+      0
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+      USART2.c
+      0
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+      ..\bsp\flash.c
+      flash.c
+      0
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+    
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+      0
+      0
+      ..\bsp\LCD.c
+      LCD.c
+      0
+      0
+    
+  
+
+  
+    StdPeriph_Driver
+    1
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+    0
+    0
+    
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+      12
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\stm32f10x_it.c
+      stm32f10x_it.c
+      0
+      0
+    
+    
+      2
+      13
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+      stm32f10x_rcc.c
+      0
+      0
+    
+    
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+      stm32f10x_usart.c
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+      misc.c
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+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+      stm32f10x_gpio.c
+      0
+      0
+    
+    
+      2
+      17
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+      stm32f10x_spi.c
+      0
+      0
+    
+    
+      2
+      18
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+      stm32f10x_tim.c
+      0
+      0
+    
+    
+      2
+      19
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c
+      stm32f10x_iwdg.c
+      0
+      0
+    
+    
+      2
+      20
+      1
+      0
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+      ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+      stm32f10x_flash.c
+      0
+      0
+    
+  
+
+  
+    CMSIS
+    1
+    0
+    0
+    0
+    
+      3
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+      0
+      0
+      0
+      0
+      ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+      core_cm3.c
+      0
+      0
+    
+    
+      3
+      22
+      1
+      0
+      0
+      0
+      0
+      ..\Libraries\system_stm32f10x.c
+      system_stm32f10x.c
+      0
+      0
+    
+  
+
+  
+    MDK-ARM
+    1
+    0
+    0
+    0
+    
+      4
+      23
+      2
+      0
+      0
+      0
+      0
+      ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s
+      startup_stm32f10x_hd.s
+      0
+      0
+    
+  
+
+  
+    Doc
+    1
+    0
+    0
+    0
+    
+      5
+      24
+      5
+      0
+      0
+      0
+      0
+      ..\说明.txt
+      说明.txt
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/RVMDK/Printf_uvproj.bak b/RVMDK/Printf_uvproj.bak
new file mode 100644
index 0000000..c429cb7
--- /dev/null
+++ b/RVMDK/Printf_uvproj.bak
@@ -0,0 +1,556 @@
+
+
+
+  1.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CreativeST_VC
+      0x4
+      ARM-ADS
+      
+        
+          STM32F100RC
+          STMicroelectronics
+          IROM(0x08000000,0x40000) IRAM(0x20000000,0x6000) CPUTYPE("Cortex-M3") CLOCK(24000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F100RC$Flash/STM32F10x_512.FLM))
+          5311
+          $$Device:STM32F100RC$Device/Include/stm32f10x.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F100RC$SVD/STM32F100xx.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Obj\
+          Printf_PC
+          1
+          0
+          1
+          1
+          1
+          .\List\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
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+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            "C:\Keil_v5\ARM\ARMCC\bin\fromelf.exe" --bin -o  ..\RVMDK\obj\Printf_PC.bin  ..\RVMDK\obj\Printf_PC.axf
+            
+            0
+            0
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+          1
+        
+        
+          SARMCM3.DLL
+          -REMAP
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
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+            
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+            
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+            
+            BIN\UL2CM3.DLL
+          
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+            1
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+          
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+            0
+            0
+            
+              
+              USE_STDPERIPH_DRIVER, STM32F10X_HD_VL
+              
+              ..\;..\Libraries\CMSIS\CM3\CoreSupport;..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\bsp;..\Libraries
+            
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+            
+            
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+            
+            
+            
+            
+          
+        
+      
+      
+        
+          User
+          
+            
+              main.c
+              1
+              ..\bsp\main.c
+            
+            
+              printf.c
+              1
+              ..\bsp\printf.c
+            
+            
+              delay.c
+              1
+              ..\bsp\delay.c
+            
+            
+              nrf24L01.c
+              1
+              ..\bsp\nrf24L01.c
+            
+            
+              tim.c
+              1
+              ..\bsp\tim.c
+            
+            
+              spi.c
+              1
+              ..\bsp\spi.c
+            
+            
+              LED.c
+              1
+              ..\bsp\LED.c
+            
+            
+              DataProc.c
+              1
+              ..\bsp\DataProc.c
+            
+            
+              USART2.c
+              1
+              ..\bsp\USART2.c
+            
+            
+              flash.c
+              1
+              ..\bsp\flash.c
+            
+            
+              LCD.c
+              1
+              ..\bsp\LCD.c
+            
+          
+        
+        
+          StdPeriph_Driver
+          
+            
+              stm32f10x_it.c
+              1
+              ..\Libraries\stm32f10x_it.c
+            
+            
+              stm32f10x_rcc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+            
+            
+              stm32f10x_usart.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+            
+            
+              misc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+            
+            
+              stm32f10x_gpio.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+            
+            
+              stm32f10x_spi.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+            
+            
+              stm32f10x_tim.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+            
+            
+              stm32f10x_iwdg.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c
+            
+            
+              stm32f10x_flash.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+            
+          
+        
+        
+          CMSIS
+          
+            
+              core_cm3.c
+              1
+              ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+            
+            
+              system_stm32f10x.c
+              1
+              ..\Libraries\system_stm32f10x.c
+            
+          
+        
+        
+          MDK-ARM
+          
+            
+              startup_stm32f10x_hd.s
+              2
+              ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s
+            
+          
+        
+        
+          Doc
+          
+            
+              说明.txt
+              5
+              ..\说明.txt
+            
+          
+        
+      
+    
+  
+
+    
diff --git a/RVMDK/Printf_uvprojx.bak b/RVMDK/Printf_uvprojx.bak
new file mode 100644
index 0000000..fc2c69e
--- /dev/null
+++ b/RVMDK/Printf_uvprojx.bak
@@ -0,0 +1,540 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CreativeST_VC
+      0x4
+      ARM-ADS
+      5060061::V5.06 update 1 (build 61)::ARMCC
+      
+        
+          STM32F100RC
+          STMicroelectronics
+          Keil.STM32F1xx_DFP.2.1.0
+          http://www.keil.com/pack/
+          IROM(0x08000000,0x40000) IRAM(0x20000000,0x6000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F100RC$Flash\STM32F10x_512.FLM))
+          5311
+          $$Device:STM32F100RC$Device\Include\stm32f10x.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F100RC$SVD\STM32F100xx.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Obj\
+          Printf_PC
+          1
+          0
+          1
+          1
+          1
+          .\List\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            "C:\Keil_v5\ARM\ARMCC\bin\fromelf.exe" --bin -o  ..\RVMDK\obj\Printf_PC.bin  ..\RVMDK\obj\Printf_PC.axf
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
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+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+          -REMAP
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4099
+          
+          0
+          Segger\JL2CM3.dll
+          "" ()
+          
+          
+          
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+            1
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+            1
+            1
+            1
+            1
+            
+              
+              USE_STDPERIPH_DRIVER, STM32F10X_HD_VL
+              
+              ..\;..\Libraries\CMSIS\CM3\CoreSupport;..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\bsp;..\Libraries
+            
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+            0x20000000
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          User
+          
+            
+              main.c
+              1
+              ..\bsp\main.c
+            
+            
+              printf.c
+              1
+              ..\bsp\printf.c
+            
+            
+              delay.c
+              1
+              ..\bsp\delay.c
+            
+            
+              nrf24L01.c
+              1
+              ..\bsp\nrf24L01.c
+            
+            
+              tim.c
+              1
+              ..\bsp\tim.c
+            
+            
+              spi.c
+              1
+              ..\bsp\spi.c
+            
+            
+              LED.c
+              1
+              ..\bsp\LED.c
+            
+            
+              DataProc.c
+              1
+              ..\bsp\DataProc.c
+            
+            
+              USART2.c
+              1
+              ..\bsp\USART2.c
+            
+            
+              flash.c
+              1
+              ..\bsp\flash.c
+            
+            
+              LCD.c
+              1
+              ..\bsp\LCD.c
+            
+          
+        
+        
+          StdPeriph_Driver
+          
+            
+              stm32f10x_it.c
+              1
+              ..\Libraries\stm32f10x_it.c
+            
+            
+              stm32f10x_rcc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+            
+            
+              stm32f10x_usart.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+            
+            
+              misc.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+            
+            
+              stm32f10x_gpio.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+            
+            
+              stm32f10x_spi.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+            
+            
+              stm32f10x_tim.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+            
+            
+              stm32f10x_iwdg.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c
+            
+            
+              stm32f10x_flash.c
+              1
+              ..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+            
+          
+        
+        
+          CMSIS
+          
+            
+              core_cm3.c
+              1
+              ..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+            
+            
+              system_stm32f10x.c
+              1
+              ..\Libraries\system_stm32f10x.c
+            
+          
+        
+        
+          MDK-ARM
+          
+            
+              startup_stm32f10x_hd.s
+              2
+              ..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s
+            
+          
+        
+        
+          Doc
+          
+            
+              说明.txt
+              5
+              ..\说明.txt
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/RVMDK/RTE/_CreativeST_VC/RTE_Components.h b/RVMDK/RTE/_CreativeST_VC/RTE_Components.h
new file mode 100644
index 0000000..a543cf2
--- /dev/null
+++ b/RVMDK/RTE/_CreativeST_VC/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'Printf' 
+ * Target:  'CreativeST_VC' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/bsp/DataProc.c b/bsp/DataProc.c
new file mode 100644
index 0000000..e9c5820
--- /dev/null
+++ b/bsp/DataProc.c
@@ -0,0 +1,1663 @@
+#include "DataProc.h"
+#include 
+#include "printf.h"
+#include "flash.h"
+#include "LCD.h"
+//SPIType	SPI_Using = SPI_PORT1;	//ѡһSPIӿ
+
+extern void IWDG_Feed(void);
+
+u8 CheckData_1356[10] = {0xD1,0xD1,0xE0,0xD0,0x00,0x00,0x00,0x00,0xD2,0xD2}; //13.56M
+u8 GetNum_1356[5] = {0x00,0x00,0x00,0x00,0x00}; //13.56M
+static u8 ResNum_1356[5];  //13.56M棬ڻظA2
+static u8 oldResNum_1356[5];
+
+u8 uartSendData[100]; //100ֽ
+u8 uartRecData[100]; //100ֽ
+
+u8 uartSendRdNumData[100];
+u8 uartSendWrNumOkData[100];
+u8 uartSendConfigKaoQinData[100];
+volatile u16 count;
+u16 count_num;
+u8 flag_1ms;
+u8 first_clear_flag;
+u8 HW_Open;
+u16 HW_OpenCount;
+
+u8 Flag_update;
+u8 WriteOKFlag=0;
+u8 protocol_config_flg;
+
+struct Protocol_send_data   //ͨѶЭ 
+{
+    u8 HeadFix;
+    u8 Control;
+    u8 Magic[4];
+    u8 SequenceID[4];
+    u8 Command;
+    u8 Tag;
+    u8 Length;
+    u8 Value[6];            //ֵ6
+    u8 FootCRC[2];          //CRC ʱ̶Ϊ00 00
+    u8 FootFix;             //̶Ϊ0xFB
+};
+
+struct Protocol_rec_data   //ͨѶЭ 
+{
+    u8 HeadFix;
+    u8 Control;
+    u8 Magic[4];
+    u8 SequenceID[4];
+    u8 Command;
+    u8 Tag;
+    u8 Length;
+    u8 Value[62];           //ֵ62
+    u8 FootCRC[2];          //CRC ʱ̶Ϊ00 00
+    u8 FootFix;             //̶Ϊ0xFB
+};
+
+//struct ReadNum_send_data   //Żظָ 30Byte
+//{
+//    u8 HeadFix;
+//    u8 Control;
+//    u8 Magic[4];
+//    u8 SequenceID[4];
+//    u8 Command;
+//    u8 Tag1;
+//    u8 Length1;
+//    u8 Value1[6];            //ֵ6
+//    u8 Tag2;
+//    u8 Length2;
+//    u8 Value2[6];            //ֵ6
+//    u8 FootCRC[2];          //CRC ʱ̶Ϊ00 00
+//    u8 FootFix;             //̶Ϊ0xFB
+//};
+
+struct ReadNum_send_data   //Żظָ 22Byte
+{
+    u8 HeadFix;
+    u8 Control;
+    u8 Magic[4];
+    u8 SequenceID[4];
+    u8 Command;
+    u8 Tag1;
+    u8 Length1;
+    u8 Value1[6];            //ֵ6
+    u8 FootCRC[2];          //CRC ʱ̶Ϊ00 00
+    u8 FootFix;             //̶Ϊ0xFB
+};
+
+struct WrNumOk_send_data   //дɹظָ
+{
+    u8 HeadFix;
+    u8 Control;
+    u8 Magic[4];
+    u8 SequenceID[4];
+    u8 Command;
+    u8 FootCRC[2];          //CRC ʱ̶Ϊ00 00
+    u8 FootFix;             //̶Ϊ0xFB
+};
+
+struct ConfigKaoQin_send_data
+{
+	u8 HeadFix;           //̶Ϊ0xFA
+	u8 Control;           // 1ʾɹ
+	u8 Magic[4];
+	u8 SequenceID[4];
+	u8 Command;            //  A8
+	u8 FootCRC[2];			//CRC ʱ̶Ϊ00 00
+	u8 FootFix; 			//̶Ϊ0xFB
+};
+
+
+#define ReceiveBuf ((struct Protocol_rec_data *)&uartRecData[0])
+#define SendBuf ((struct Protocol_send_data *)&uartSendData[0])
+#define ConfigKaoQinBuf ((struct ConfigKaoQin_send_data *)&uartSendConfigKaoQinData[0])
+#define WrNumOkBuf ((struct WrNumOk_send_data *)&uartSendWrNumOkData[0])
+#define ReadNumBuf ((struct ReadNum_send_data *)&uartSendRdNumData[0])
+
+#define	CndRspBufferSize  100
+
+unsigned char CmdRspBuffer[CndRspBufferSize];
+unsigned char CmdRspBufferWr_Rx = 0;
+
+u8 idBuf[5];        //2.4G IDռ
+
+
+u16 count_A34;
+u8 idResA3Buf[5];     //2.4G ID棬ڻظA3
+u8 ReadAttenID[5];  //2.4G ڿID
+
+u8 newIdFlag;   //д2.4G ID־
+u8 recFlag;
+u8 rspFlag_A3;
+u8 read1356flag;
+
+unsigned char txBuf[32]="123456789123456789";
+unsigned char txA3Buf[32]="123456789123456789";
+unsigned char rspFlag = 0;  //Ƿ⿨ϵ2.4GϢ ־
+unsigned char wrNumFlag = 0;//дǷɱ־
+
+/****************************************************
+: У
+
+: sum = ~(data0+...+datan)+1;
+*****************************************************/
+u8 CheckSum(u8 *buf,u8 len)
+{
+	u8 sum = 0;
+	u8 i;
+	for(i = 0;i < len; i++)
+	{
+		sum += buf[i];
+	}
+	sum = ~sum;
+	sum += 1;
+	return sum;
+}
+
+//void AT_AddNewRxByte(u8 c)
+//{
+//	if (c != 0x0D)
+//	{
+//		if (c < 32) return;											// ignore control charcters			
+//		if (CmdRspBufferWr_Rx >= (CndRspBufferSize - 1)) return;	       // buffer overflow - ignore character
+//		CmdRspBuffer[CmdRspBufferWr_Rx++] = c;
+//		CmdRspBuffer[CmdRspBufferWr_Rx] = 0;	
+//		return;
+//	}
+//	//----------------------------------------------------
+//	// ID=XXXXX
+//	if((CmdRspBuffer[0] == 'I')&&(CmdRspBuffer[1] == 'D')&&(CmdRspBuffer[2] == '='))	
+//	{
+//	   memcpy(idBuf,&CmdRspBuffer[3],5);
+//	   SendConsoleStr("id=");
+//	   SendConsoleData(idBuf,5);
+//	   SendConsoleStr("\n");
+//	   newIdFlag = 1;
+//	}
+//	else if((CmdRspBuffer[0] == 'I')&&(CmdRspBuffer[1] == 'D')&&(CmdRspBuffer[2] == '?'))
+//	{
+//	  	SendConsoleStr("id=");
+//	   	SendConsoleData(idBuf,5);
+//		SendConsoleStr("\n");  		
+//	}
+//	memset(CmdRspBuffer,0,sizeof(CmdRspBuffer));
+//	CmdRspBufferWr_Rx = 0;
+//}
+
+
+void Data_Init(void)    //ݳʼ
+{
+    SendBuf->HeadFix = 0xFA;        //ͻʼ
+    SendBuf->Control = 0x10;
+    SendBuf->Magic[0]= 0;
+    SendBuf->Magic[1]= 0;
+    SendBuf->Magic[2]= 0;
+    SendBuf->Magic[3]= 0;
+    SendBuf->SequenceID[0] = 0;
+    SendBuf->SequenceID[1] = 0;
+    SendBuf->SequenceID[2] = 0;
+    SendBuf->SequenceID[3] = 0;
+    SendBuf->FootCRC[0] = 0;
+    SendBuf->FootCRC[1] = 0;
+    SendBuf->FootFix = 0xFB;
+    
+    ReceiveBuf->HeadFix = 0xFA;         //ջʼ
+    ReceiveBuf->Control = 0x10;
+    ReceiveBuf->Magic[0]= 0;
+    ReceiveBuf->Magic[1]= 0;
+    ReceiveBuf->Magic[2]= 0;
+    ReceiveBuf->Magic[3]= 0;
+    ReceiveBuf->SequenceID[0] = 0;
+    ReceiveBuf->SequenceID[1] = 0;
+    ReceiveBuf->SequenceID[2] = 0;
+    ReceiveBuf->SequenceID[3] = 0;
+    ReceiveBuf->FootCRC[0] = 0;
+    ReceiveBuf->FootCRC[1] = 0;
+    ReceiveBuf->FootFix = 0xFB;
+
+	ConfigKaoQinBuf->HeadFix = 0xFA;         //ջʼ
+    ConfigKaoQinBuf->Control = 0x10;
+    ConfigKaoQinBuf->Magic[0]= 0;
+    ConfigKaoQinBuf->Magic[1]= 0;
+    ConfigKaoQinBuf->Magic[2]= 0;
+    ConfigKaoQinBuf->Magic[3]= 0;
+    ConfigKaoQinBuf->SequenceID[0] = 0;
+    ConfigKaoQinBuf->SequenceID[1] = 0;
+    ConfigKaoQinBuf->SequenceID[2] = 0;
+    ConfigKaoQinBuf->SequenceID[3] = 0;
+    ConfigKaoQinBuf->FootCRC[0] = 0;
+    ConfigKaoQinBuf->FootCRC[1] = 0;
+    ConfigKaoQinBuf->FootFix = 0xFB;
+
+	
+    ReadNumBuf->HeadFix = 0xFA;         //ջʼ
+    ReadNumBuf->Control = 0x10;
+    ReadNumBuf->Magic[0]= 0;
+    ReadNumBuf->Magic[1]= 0;
+    ReadNumBuf->Magic[2]= 0;
+    ReadNumBuf->Magic[3]= 0;
+    ReadNumBuf->SequenceID[0] = 0;
+    ReadNumBuf->SequenceID[1] = 0;
+    ReadNumBuf->SequenceID[2] = 0;
+    ReadNumBuf->SequenceID[3] = 0;
+    ReadNumBuf->FootCRC[0] = 0;
+    ReadNumBuf->FootCRC[1] = 0;
+    ReadNumBuf->FootFix = 0xFB;
+    
+    WrNumOkBuf->HeadFix = 0xFA;         //ջʼ
+    WrNumOkBuf->Control = 0x10;
+    WrNumOkBuf->Magic[0]= 0;
+    WrNumOkBuf->Magic[1]= 0;
+    WrNumOkBuf->Magic[2]= 0;
+    WrNumOkBuf->Magic[3]= 0;
+    WrNumOkBuf->SequenceID[0] = 0;
+    WrNumOkBuf->SequenceID[1] = 0;
+    WrNumOkBuf->SequenceID[2] = 0;
+    WrNumOkBuf->SequenceID[3] = 0;
+    WrNumOkBuf->FootCRC[0] = 0;
+    WrNumOkBuf->FootCRC[1] = 0;
+    WrNumOkBuf->FootFix = 0xFB;
+}
+
+//void Usart1_Process(void)
+//{
+//    
+//    if(USART1_RX_CNT==10 && USART1_RX_BUF[0]==0xd1 && USART1_RX_BUF[9]==0xd2)
+//    {
+//        USART1_REC_Status |= 0x8000;    //յIDʮ10λID
+//    }
+//    
+//    
+//    if(USART1_REC_Status & 0x8000)
+//    {
+////        memcpy(idBuf,&USART1_RX_BUF[3],5);  //5λʮIDдidBuf
+//        idBuf[0]=0;
+//        idBuf[1]=USART1_RX_BUF[4];
+//        idBuf[2]=USART1_RX_BUF[5];
+//        idBuf[3]=USART1_RX_BUF[6];
+//        idBuf[4]=USART1_RX_BUF[7];  //յIDд뵽idBuf
+//        
+//        SendConsoleStr("id=");
+//        SendConsoleData(idBuf,5);
+//        SendConsoleStr("\n");
+//        newIdFlag = 1;
+//        
+//        USART1_RX_CNT = 0;
+//        USART1_REC_Status = 0;
+//    }
+//}
+
+
+void DataProc_1356(void)
+{    
+	u32 dat1,dat2,dat3,dat4;
+	u8 IdBuf[10]={0};
+	IWDG_Feed();
+	if(USART3_RX_CNT==10)
+	{
+		if(USART3_RX_BUF[0]==CheckData_1356[0] && USART3_RX_BUF[1]==CheckData_1356[1]
+		&& USART3_RX_BUF[8]==CheckData_1356[8] && USART3_RX_BUF[9]==CheckData_1356[9])
+		{
+		    USART3_REC_Status |= 0x8000;    //3ɽһ֡
+		}
+		else
+		{
+			memset(USART3_RX_BUF,0,20);
+		}
+	}
+    
+	if(USART3_REC_Status & 0x8000)
+	{        
+        //дֹһдӰ
+        //delay_ms(1);
+#if 0
+        idBuf[0]=0;
+        idBuf[1]=0;
+        idBuf[2]=0;
+        idBuf[3]=0;
+        idBuf[4]=0;
+
+        GetNum_1356[0]=0;
+        GetNum_1356[1]=0;
+        GetNum_1356[2]=0;
+        GetNum_1356[3]=0;
+        GetNum_1356[4]=0;
+        
+        idResA3Buf[0]=0;
+        idResA3Buf[1]=0;
+        idResA3Buf[2]=0;
+        idResA3Buf[3]=0;
+        idResA3Buf[4]=0;
+        
+        ReadAttenID[0]=0;
+        ReadAttenID[1]=0;
+        ReadAttenID[2]=0;
+        ReadAttenID[3]=0;
+        ReadAttenID[4]=0;
+ #else
+		memset(idBuf,0,5);
+		memset(GetNum_1356,0,5);
+		memset(idResA3Buf,0,5);
+		memset(ReadAttenID,0,5);
+ #endif
+//        SendConsoleData(USART3_RX_BUF,10);
+//        DegugPrintf(USART3_RX_BUF,10);
+//        SendConsoleStr("\n");
+       
+        //IWDG_Feed();
+        GetNum_1356[0]=0;
+        GetNum_1356[1]=USART3_RX_BUF[4];
+        GetNum_1356[2]=USART3_RX_BUF[5];
+        GetNum_1356[3]=USART3_RX_BUF[6];
+        GetNum_1356[4]=USART3_RX_BUF[7];  //յIDд뵽idBuf
+        
+		ResNum_1356[0]=0;
+		ResNum_1356[1]=GetNum_1356[1];
+		ResNum_1356[2]=GetNum_1356[2];
+		ResNum_1356[3]=GetNum_1356[3];
+		ResNum_1356[4]=GetNum_1356[4];
+
+       // NRF24L01_RX_Mode(SPI_SEND);     //
+        dat1 = (GetNum_1356[1]<<24);
+        dat2 = (GetNum_1356[2]<<16);
+        dat3 = (GetNum_1356[3]<<8);
+        dat4 = dat1 + dat2 + dat3 + GetNum_1356[4];
+#if LCD
+		HexToDec(dat4,IdBuf,sizeof(IdBuf));
+		vDispClearLine(2);
+		vDispStr(2,1,"13.56:",6);
+		vDispStr(2,7,(char*)IdBuf,10);
+#endif
+		read1356flag = 1;
+//        printf("1356_0=%x\r\n",GetNum_1356[0]);
+//        printf("1356_1=%x\r\n",GetNum_1356[1]);
+//        printf("1356_2=%x\r\n",GetNum_1356[2]);
+//        printf("1356_3=%x\r\n",GetNum_1356[3]);
+//        printf("1356_4=%x\r\n",GetNum_1356[4]);
+//        printf("\r\n13.56Mţ%u\r\n",dat4);       
+        IWDG_Feed();
+//        idBuf[0]=GetNum_1356[0];
+//        idBuf[1]=GetNum_1356[1];
+//        idBuf[2]=GetNum_1356[2];
+//        idBuf[3]=GetNum_1356[3];
+//        idBuf[4]=GetNum_1356[4];
+//        delay_ms(100);delay_ms(100);
+        
+        //HW_Open = 1;                     //غɨǹ
+        
+//        newIdFlag = 1;  //2.4Gʼд
+//        count = 0;
+
+        //IWDG_Feed();
+        USART3_RX_CNT = 0;		   //
+		USART3_REC_Status = 0;
+		memset(USART3_RX_BUF,0,20);
+    }
+}
+#if 0
+void DataProc_RecNrf24L01(void)
+{
+    u8 buffer[7];
+    u8 temp;
+    u32 dat1,dat2,dat3,dat4;
+    IWDG_Feed();
+//    if(WriteOKFlag==1)
+//    {
+        
+            if(SPI2_IRQ == 0)
+            {
+                IWDG_Feed();
+                temp = NRF24L01_RxPacket(SPI_SEND,buffer);
+                
+        //        printf("temp=%x\r\n",temp);
+        //            SendConsoleData(buffer,RX_PLOAD_WIDTH);
+                
+                idBuf[0] = 0;
+                idBuf[1] = buffer[1];
+                idBuf[2] = buffer[2];
+                idBuf[3] = buffer[3];
+                idBuf[4] = buffer[4];
+                
+//                if(idBuf[0]==GetNum_1356[0] && idBuf[1]==GetNum_1356[1] && idBuf[2]==GetNum_1356[2] && idBuf[3]==GetNum_1356[3] && idBuf[4]==GetNum_1356[4])
+//                {
+//                    recFlag = 2;    //д2.4G
+                    dat1 = idBuf[1]<<24;
+                    dat2 = idBuf[2]<<16;
+                    dat3 = idBuf[3]<<8;
+                    dat4 = dat1 + dat2 + dat3 + idBuf[4];
+//                    if(WriteOKFlag)
+//                        printf("ID=%u\r\n",dat4);
+                        delay_ms(10);
+//                    else
+//                        printf("дţ:%u\r\n",dat4);
+                    
+                    WriteOKFlag = 0;
+                    idBuf[0]=0;
+                    idBuf[1]=0;
+                    idBuf[2]=0;
+                    idBuf[3]=0;
+                    idBuf[4]=0;
+                    GetNum_1356[0]=0;
+                    GetNum_1356[1]=0;
+                    GetNum_1356[2]=0;
+                    GetNum_1356[3]=0;
+                    GetNum_1356[4]=0;
+//                }
+//                else
+//                {
+////                    printf("δдţ\r\n");
+////                    NRF24L01_RX_Mode(SPI_SEND);
+//                    IWDG_Feed();
+//                    
+//                    WriteOKFlag = 0;
+//                    WriteFailFlag = 0;
+//                    idBuf[0] = 0;
+//                    idBuf[1] = 0;
+//                    idBuf[2] = 0;
+//                    idBuf[3] = 0;
+//                    idBuf[4] = 0;
+//                    GetNum_1356[0]=0;
+//                    GetNum_1356[1]=0;
+//                    GetNum_1356[2]=0;
+//                    GetNum_1356[3]=0;
+//                    GetNum_1356[4]=0;
+//                    
+//                    NRF24L01_TX_Mode(SPI_SEND);
+//                }
+            }
+       
+
+}
+
+#else
+void DataProc_RecNrf24L01(void)
+{
+    u8 tmp;
+    u32 IdData;
+    u8  IdBuf[10]={0};
+    //if(read1356flag)
+    {
+        NRF24L01_RX_Mode_NOACK(SPI_SEND,protocol_config_flg);//NOACK??,?????
+        count_A34 = 0;
+        {
+            while(1)   //
+            {
+
+                tmp = DataProc_A4_nrf();
+
+                if(tmp)
+                    break;
+            }
+            read1356flag = 0;
+#if LCD
+            IdData =(ReadAttenID[1]<<24)|(ReadAttenID[2]<<16)|(ReadAttenID[3]<<8)|(ReadAttenID[4]);
+            HexToDec(IdData,IdBuf,sizeof(IdBuf));
+            vDispClearLine(3);
+            vDispStr(3,1,"ID:",3);
+            vDispStr(3,4,(char*)IdBuf,10); 
+            if((ReadAttenID[0] & 0x80) !=0)
+            {
+                vDispStr(3,15,"1",1); 
+            }
+            else
+            {
+                vDispStr(3,15,"0",1); 
+            } 
+#endif
+            SendConsoleData((char*)uartSendRdNumData,22);   //ԣظPC
+            delay_ms(50);
+
+            DegugPrintf(uartSendRdNumData,22);
+            SendUSART2Str("\n");	
+#if LCD
+            if(ResNum_1356[0] ==ReadAttenID[0] &&ResNum_1356[1] ==ReadAttenID[1] && ResNum_1356[2] ==ReadAttenID[2]
+                &&ResNum_1356[3] ==ReadAttenID[3] && ResNum_1356[4] ==ReadAttenID[4]) 
+            {
+                vDispClearLine(4);
+                vDispStr(4,4,"OK",2);
+
+            }
+            else
+            {
+                vDispClearLine(4);
+                vDispStr(4,4,"NG",2);
+
+            }
+#endif
+            //дֹһдӰ
+            ReadAttenID[0]=0;
+            ReadAttenID[1]=0;
+            ReadAttenID[2]=0;
+            ReadAttenID[3]=0;
+            ReadAttenID[4]=0;
+            ResNum_1356[0]=0;
+            ResNum_1356[1]=0;
+            ResNum_1356[2]=0;
+            ResNum_1356[3]=0;
+            ResNum_1356[4]=0;
+            GetNum_1356[0]=0;
+            GetNum_1356[1]=0;
+            GetNum_1356[2]=0;
+            GetNum_1356[3]=0;
+            GetNum_1356[4]=0;    
+        }
+    }
+
+}
+
+#endif
+
+void DataProc_Nrf24l01_SPI2(void)
+{
+    u8 buffer[32];
+    u8 temp;
+    //u32 dat1,dat2,dat3,dat4,cardid;
+    IWDG_Feed();
+
+    if(newIdFlag==1)
+    {
+        newIdFlag = 0;
+        txBuf[0] = 0xfc;
+        txBuf[1] = 0x11;
+//        if(idBuf[0]==GetNum_1356[0] && idBuf[1]==GetNum_1356[1] && idBuf[2]==GetNum_1356[2] && idBuf[3]==GetNum_1356[3] && idBuf[4]==GetNum_1356[4])
+//        {
+            txBuf[2] = idBuf[0];
+            txBuf[3] = idBuf[1];
+            txBuf[4] = idBuf[2];
+            txBuf[5] = idBuf[3];
+            txBuf[6] = idBuf[4];
+//        }
+        
+        txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+		SPI2_CE =0;
+        
+        NRF24L01_Write_Reg(SPI_SEND,FLUSH_TX,0xff);//TX FIFOĴ 
+		NRF24L01_Write_Buf(SPI_SEND,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF 8ֽڣԶ
+		NRF24L01_RX_Mode(SPI_SEND);      //24L01Ϊģʽ
+        rspFlag = 1;
+        count=0;
+        IWDG_Feed();
+        
+    }
+        
+
+        
+    if(rspFlag) //⿨ϵ緢͵
+    {
+        IWDG_Feed();
+        if(count<=2000) //2Sδյ2.4GظźţrspFlagʧЧ
+        {
+            if(SPI2_IRQ == 0)   //24L01յ⿨ϵ緢͵
+            {
+                IWDG_Feed();
+                temp = NRF24L01_RxPacket(SPI_SEND,buffer);
+//                SendConsoleByte(temp);
+
+                if((temp&0x40)==0x40)   //յʾ
+                {
+                    buffer[RX_PLOAD_WIDTH]='\0';
+                    led0=~led0;
+
+//                    SendConsoleData(buffer,RX_PLOAD_WIDTH); //
+
+                    if((buffer[1]==idBuf[0])&& (buffer[2]==idBuf[1])&&(buffer[3]==idBuf[2])&&(buffer[4]==idBuf[3])&&(buffer[5]==idBuf[4]))    //յд
+                    {
+//                        if((buffer[1]==GetNum_1356[0])&& (buffer[2]==GetNum_1356[1])&&(buffer[3]==GetNum_1356[2])&&(buffer[4]==GetNum_1356[3])&&(buffer[5]==GetNum_1356[4]))
+//                        {
+                            if(rspFlag == 1)
+                            {
+                                rspFlag++;
+                                txBuf[1] = 0x12;             ///0xfc + cmd(0x12) +id +crc   ----cmd=0x12 ȷ
+                                txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+                                NRF24L01_Write_Buf(SPI_SEND,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF 8ֽڣԶ
+                            }
+                            else
+                            {
+                                rspFlag=0;  //IDѾ£rspFlag㣬
+                                count = 0;  //
+                                idBuf[0]=0;
+                                
+                                WrNumOkBuf->Control = 0x10; //д
+                                SendConsoleData((char*)uartSendWrNumOkData,14);   //ԣظPC
+                                
+                                DegugPrintf(uartSendWrNumOkData,14);
+                                SendUSART2Str("\n");
+                                
+                                //dat1 = (idBuf[1]<<24);
+                                //dat2 = (idBuf[2]<<16);
+                                //dat3 = (idBuf[3]<<8);
+                                //dat4 = idBuf[4];
+                                //cardid = dat1 + dat2 + dat3 + dat4;
+//                                printf("дɣţ%u\r\n",cardid);
+                                
+                                //NRF24L01_RX_Mode_NOACK(SPI_SEND);//
+                            #if APP
+                            NRF24L01_RX_Mode_NOACK(SPI_SEND,protocol_config_flg);//???
+                            #else
+                            NRF24L01_RX_Mode_NOACK(SPI_SEND);//
+                            #endif
+                                WriteOKFlag = 1;
+                            }
+//                        }
+                        
+                        
+                    }
+                    else
+                    {
+                        SPI2_CE =0;
+                        txBuf[1] = 0x11;
+                        txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+                        NRF24L01_Write_Buf(SPI_SEND,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF  8ֽ
+                        SPI2_CE =1;
+                    }
+                }
+            }
+            
+        }
+        else    //2sʱظ
+        {
+            IWDG_Feed();
+            rspFlag=0;  //IDѾ£rspFlag㣬
+            count = 0;  //
+            
+            idBuf[0]=0;
+            idBuf[1]=0;
+            idBuf[2]=0;
+            idBuf[3]=0;
+            idBuf[4]=0;
+            GetNum_1356[0]=0;
+            GetNum_1356[1]=0;
+            GetNum_1356[2]=0;
+            GetNum_1356[3]=0;
+            GetNum_1356[4]=0;
+            
+            
+            WrNumOkBuf->Control = 0x30; //
+            SendConsoleData((char*)uartSendWrNumOkData,14);   //ԣظPC
+            
+            DegugPrintf(uartSendWrNumOkData,14);
+            SendUSART2Str("\n");
+//            printf("дʧ:ʱ\r\n");
+//            NRF24L01_RX_Mode_NOACK(SPI_SEND);//
+        }
+        
+    }
+
+}
+
+
+u8 DataProc_A0_WriteNum_SPI2(void)
+{
+    u8 temp;
+    u8 buffer[32];
+    
+    if(newIdFlag==1)
+    {
+        newIdFlag = 0;
+        txBuf[0] = 0xfc;
+        txBuf[1] = 0x11;
+        txBuf[2] = idBuf[0];
+        txBuf[3] = idBuf[1];
+        txBuf[4] = idBuf[2];
+        txBuf[5] = idBuf[3];
+        txBuf[6] = idBuf[4];
+        
+        txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+		SPI2_CE =0;
+        NRF24L01_Write_Reg(SPI_SEND,FLUSH_TX,0xff);//TX FIFOĴ 
+		NRF24L01_Write_Buf(SPI_SEND,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF 8ֽڣԶ
+		NRF24L01_RX_Mode(SPI_SEND);      //24L01Ϊģʽ
+        SPI2_CE =1;
+        rspFlag = 1;
+        count=0;
+        IWDG_Feed();
+        
+    }
+    
+    if(count<=3000)
+    {
+        IWDG_Feed();
+        if(SPI2_IRQ == 0)   //24L01յ⿨ϵ緢͵
+        {
+            IWDG_Feed();
+            temp = NRF24L01_RxPacket(SPI_SEND,buffer);
+            SendUSART2Byte(temp);
+            SendUSART2Str("\n");
+
+            if((temp&0x40)==0x40)   //յʾ
+            {
+                buffer[RX_PLOAD_WIDTH]='\0';
+                
+                DegugPrintf(buffer,7);
+                SendUSART2Str("\n");
+
+                if((buffer[1]==idBuf[0])&& (buffer[2]==idBuf[1])&&(buffer[3]==idBuf[2])&&(buffer[4]==idBuf[3])&&(buffer[5]==idBuf[4]))    //յд
+                {
+                        if(rspFlag == 1)
+                        {
+                            rspFlag++;
+                            txBuf[1] = 0x12;             ///0xfc + cmd(0x12) +id +crc   ----cmd=0x12 ȷ
+                            txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+                            SPI2_CE =0;
+                            NRF24L01_Write_Buf(SPI_SEND,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF 8ֽڣԶ
+                            SPI2_CE =1;
+                        }
+                        else
+                        {
+                            rspFlag=0;  //IDѾ£rspFlag㣬
+                        
+                            DegugPrintf(uartSendWrNumOkData,14);
+                            SendUSART2Str("\n");
+                            
+                            //NRF24L01_RX_Mode_NOACK(SPI_SEND);//
+                            #if  APP
+                            NRF24L01_RX_Mode_NOACK(SPI_SEND,protocol_config_flg);//???
+                            #else
+                             NRF24L01_RX_Mode_NOACK(SPI_SEND);//
+                            #endif
+                            WrNumOkBuf->Control = 0x10; //д
+                            SendConsoleData((char*)uartSendWrNumOkData,14);   //ԣظPC
+
+                            SendUSART2Str("OK\n");
+                            return 1;
+                        }                    
+                    
+                }
+                else
+                {
+                    SPI2_CE =0;
+                    txBuf[1] = 0x11;
+                    txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+                    NRF24L01_Write_Buf(SPI_SEND,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF  8ֽ
+                    SPI2_CE =1;
+                    
+                }
+            }
+            
+        }
+    }
+    else
+    {
+        idBuf[0] = 0;
+        idBuf[1] = 0x00;
+        idBuf[2] = 0x00;
+        idBuf[3] = 0x00;
+        idBuf[4] = 0x00;
+        ReadAttenID[0]=0;
+        ReadAttenID[1]=0;
+        ReadAttenID[2]=0;
+        ReadAttenID[3]=0;
+        ReadAttenID[4]=0;
+        ResNum_1356[0]=0;
+        ResNum_1356[1]=0;
+        ResNum_1356[2]=0;
+        ResNum_1356[3]=0;
+        ResNum_1356[4]=0;
+        GetNum_1356[0]=0;
+        GetNum_1356[1]=0;
+        GetNum_1356[2]=0;
+        GetNum_1356[3]=0;
+        GetNum_1356[4]=0;
+        WrNumOkBuf->Control = 0x30; //дʧ
+        SendConsoleData((char*)uartSendWrNumOkData,14);   //ԣظPC
+//        USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);	//ʼ1ж
+        SendUSART2Str("3000\n");
+        return 1;
+    }
+    IWDG_Feed();
+    return 0;
+}
+
+
+u8 DataProc_A3_nrf(void)
+{
+    u8 temp;
+    u8 buffer[32];
+    
+    if(rspFlag_A3)
+    {
+        rspFlag_A3=0;
+        SPI2_CE = 0;
+        NRF24L01_Write_Reg(SPI_SEND,FLUSH_TX,0xff);//TX FIFOĴ 
+        NRF24L01_Write_Buf(SPI_SEND,W_ACK_PAYLOAD,txA3Buf,8);   //дݵTX BUF 8ֽڣԶ
+        NRF24L01_RX_Mode(SPI_SEND);      //24L01Ϊģʽ
+        SPI2_CE = 1;    
+    }
+    if(count_A34<1500)
+    {
+        if(SPI2_IRQ == 0)   //24L01յ⿨ϵ緢͵
+        {
+            IWDG_Feed();
+            temp = NRF24L01_RxPacket(SPI_SEND,buffer);
+
+
+            
+            if((temp&0x40)==0x40)   //յʾ
+            {
+                buffer[RX_PLOAD_WIDTH]='\0';
+
+                DegugPrintf(buffer,7);
+                SendUSART2Str("\n");
+
+                if((buffer[1]==0)&& (buffer[2]==0)&&(buffer[3]==0)&&(buffer[4]==0)&&(buffer[5]==0))    //δд
+                {
+                    idResA3Buf[0] = 0;
+                    idResA3Buf[1] = 0;
+                    idResA3Buf[2] = 0;
+                    idResA3Buf[3] = 0;
+                    idResA3Buf[4] = 0;
+//                        USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);	//ʼ1ж
+                    return 1;
+                }
+                else
+                {
+                    idResA3Buf[0] = buffer[1];
+                    idResA3Buf[1] = buffer[2];
+                    idResA3Buf[2] = buffer[3];
+                    idResA3Buf[3] = buffer[4];
+                    idResA3Buf[4] = buffer[5];
+//                        USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);	//ʼ1ж
+                    return 1;
+                }
+
+            }
+        }
+        IWDG_Feed();
+    }
+    else
+    {
+        idResA3Buf[0] = 0;
+        idResA3Buf[1] = 0x00;
+        idResA3Buf[2] = 0x00;
+        idResA3Buf[3] = 0x00;
+        idResA3Buf[4] = 0x00;
+//        USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);	//ʼ1ж
+        return 1;
+    }
+    return 0;
+}
+
+u8 DataProc_A4_nrf(void)
+{
+    u8 temp;
+    u8 buffer[32];
+	if(count_A34<3000)
+	{
+		if(SPI2_IRQ == 0)   //24L01յ⿨ϵ緢͵
+		{
+			IWDG_Feed();
+			temp = NRF24L01_RxPacket(SPI_SEND,buffer);
+
+			if((temp&0x40)==0x40)   //յʾ
+			{
+				buffer[RX_PLOAD_WIDTH]='\0';
+
+				//DegugPrintf(buffer,7);
+				//SendUSART2Str("\n");
+				//SendConsoleData(buffer,32);   //ԣظPC
+				if((buffer[1]==0)&& (buffer[2]==0)&&(buffer[3]==0))    //δд                    
+				{
+					ReadAttenID[0] = 0;
+					ReadAttenID[1] = 0;
+					ReadAttenID[2] = 0;
+					ReadAttenID[3] = 0;
+					ReadAttenID[4] = 0;
+					return 1;
+				}
+				else
+				{
+					if((protocol_config_flg == 7)||(protocol_config_flg == 13))
+					{
+					    ReadAttenID[0] = 0;
+					    ReadAttenID[1] = buffer[0];
+					    ReadAttenID[2] = buffer[1];
+					    ReadAttenID[3] = buffer[2];
+					    ReadAttenID[4] = buffer[3];
+					}
+					else if((protocol_config_flg == 8))
+					{
+					    ReadAttenID[0] = buffer[1];
+					    ReadAttenID[1] = buffer[2];
+					    ReadAttenID[2] = buffer[3];
+					    ReadAttenID[3] = buffer[4];
+					    ReadAttenID[4] = buffer[5];
+					}
+					else if((protocol_config_flg == 9)||(protocol_config_flg == 14))
+					{
+					    ReadAttenID[0] = 0;
+					    ReadAttenID[1] = (buffer[1]^0x53);
+					    ReadAttenID[2] = (buffer[2]^0x43);
+					    ReadAttenID[3] = (buffer[3]^0x44);
+					    ReadAttenID[4] = (buffer[4]^0x58);
+
+					}
+					else if(protocol_config_flg == 20)
+					{
+						ReadAttenID[0] = 0;
+						ReadAttenID[1] = buffer[4];
+						ReadAttenID[2] = buffer[5];
+						ReadAttenID[3] = buffer[6];
+						ReadAttenID[4] = buffer[7];
+					}
+					else
+					{															
+						ReadAttenID[0] = 0;
+						ReadAttenID[1] = buffer[1];
+						ReadAttenID[2] = buffer[2];
+						ReadAttenID[3] = buffer[3];
+						ReadAttenID[4] = buffer[4];
+					}
+				    return 1;
+				}
+
+			}
+		}
+		IWDG_Feed();
+	}
+	else
+	{
+		ReadAttenID[0] = 0;
+		ReadAttenID[1] = 0;
+		ReadAttenID[2] = 0;
+		ReadAttenID[3] = 0;
+		ReadAttenID[4] = 0;
+		return 1;
+	}
+	return 0;
+}
+
+
+
+void DataProc_USART1(void)
+{
+//    u8 i;
+//    u16 reclen;
+//	u32 IdData;
+//	u8  IdBuf[10]={0};
+    IWDG_Feed();
+
+    if(USART1_RX_CNT==8 && USART1_RX_BUF[0]=='u' && USART1_RX_BUF[1]=='p' && USART1_RX_BUF[2]=='d' && USART1_RX_BUF[3]=='a' && USART1_RX_BUF[4]=='t' && USART1_RX_BUF[5]=='e' )
+    {
+        USART1_RX_CNT =0;
+        NVIC_SystemReset(); //ϵͳλ
+    }    
+
+    if(USART1_RX_BUF[0]!='u' && USART1_RX_BUF[0]!=0xFA)
+    {
+        USART1_RX_CNT =0;
+        return;
+    }
+    
+    if(USART1_RX_CNT < 14)
+    {
+        return;
+    }
+    if(USART1_RX_BUF[USART1_RX_CNT-1] != 0xFB)
+    {
+        return;
+    }
+    if(USART1_RX_BUF[10]==0xA0 && USART1_RX_CNT != 21)
+    {
+        return;
+    }
+    
+    if(USART1_RX_CNT == 14)       //һָ־
+    {
+        
+        if(USART1_RX_BUF[0]==0xFA && USART1_RX_BUF[13]==0xFB)//ͷβ
+        {
+            USART1_REC_Status |= 0x8000;
+            USART1_RX_CNT = 0;
+//            SendUartData(USART1_RX_BUF,14,USART2);
+            DegugPrintf(USART1_RX_BUF,14);
+            SendUSART2Str("\n");
+        }
+        else
+        {
+            USART1_RX_CNT = 0;
+            USART1_REC_Status = 0;  //ճȷͷβûͨ
+        }
+    }
+    else if(USART1_RX_CNT == 21)
+    {
+
+        if(USART1_RX_BUF[0]==0xFA && USART1_RX_BUF[20]==0xFB)//ͷβ
+        {
+            USART1_REC_Status |= 0x8000;
+            USART1_RX_CNT = 0;
+//            SendUartData(USART1_RX_BUF,21,USART2);
+            DegugPrintf(USART1_RX_BUF,21);
+            SendUSART2Str("\n");
+        }
+        else
+        {
+            USART1_RX_CNT = 0;
+            USART1_REC_Status = 0;  //ճȷͷβûͨ
+        }
+    }
+    else if(USART1_RX_CNT == 17)
+    {
+        if(USART1_RX_BUF[0]==0xFA && USART1_RX_BUF[16]==0xFB)//ͷβ
+        {
+            USART1_REC_Status |= 0x8000;
+            USART1_RX_CNT = 0;
+//            SendUartData(USART1_RX_BUF,21,USART2);
+            DegugPrintf(USART1_RX_BUF,17);
+            SendUSART2Str("\n");
+        }
+        else
+        {
+            USART1_RX_CNT = 0;
+            USART1_REC_Status = 0;  //ճȷͷβûͨ
+        }  
+    }
+
+
+
+    if(USART1_REC_Status & 0x8000)                  //һ֡
+    {
+//        DegugPrintf(USART1_RX_BUF,strlen(USART1_RX_BUF));
+//        printf("len=%d\n",USART1_RX_CNT);
+		
+
+        IWDG_Feed();
+//        printf("Rec = %d\r\n",USART1_RX_CNT);
+        ReceiveBuf->SequenceID[0] = USART1_RX_BUF[6];
+        ReceiveBuf->SequenceID[1] = USART1_RX_BUF[7];
+        ReceiveBuf->SequenceID[2] = USART1_RX_BUF[8];
+        ReceiveBuf->SequenceID[3] = USART1_RX_BUF[9];
+        
+        ReceiveBuf->Command = USART1_RX_BUF[10];    //
+//        ReceiveBuf->Tag     = USART1_RX_BUF[11];    //Tag 
+//        ReceiveBuf->Length  = USART1_RX_BUF[12];    //ݳ        
+        
+        SendBuf->SequenceID[0] = ReceiveBuf->SequenceID[0];
+        SendBuf->SequenceID[1] = ReceiveBuf->SequenceID[1];
+        SendBuf->SequenceID[2] = ReceiveBuf->SequenceID[2];
+        SendBuf->SequenceID[3] = ReceiveBuf->SequenceID[3]; //SequenceIDͬ
+        
+        //USART1_REC_Status = 0;
+        //USART1_RX_CNT =0;
+        
+        
+        switch(ReceiveBuf->Command)
+        {
+            case Reset:                     //λ
+//                printf("Reset\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+                
+            case GetFirmversion:            //ȡ̼汾
+//                printf("GetFirmversion\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+                
+            case SetReaderID:            //ĶID
+//                printf("SetReaderID\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+                
+            case GetReaderID:            //ȡĶID
+//                printf("GetReaderID\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case DelWhite:            //ɾ
+//                printf("DelWhite\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case OpenWhite:            //򿪰
+//                printf("OpenWhite\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case CloseWhite:            //رհ
+//                printf("CloseWhite\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case AddWhite:            //Ӱ
+//                printf("AddWhite\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case GetWhite:            //ȡ
+//                printf("GetWhite\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case Heart:            //
+//                printf("Heart\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case GetWhiteState:            //ȡ״̬
+//                printf("GetWhiteState\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case WriteNum:            //д A0
+                //FA 00 00 00 00 00 00 00 00 00 A0 01 05 00 01 02 03 04 00 00 FB --21byte
+//                printf("д 2.4G \n");                
+//                DegugPrintf(USART1_RX_BUF,21);
+//                SendUSART2Str("\n");
+            {   
+                u8 tmp;
+                //ݴ
+                USART1_RX_CNT = 0;
+                WrNumOkBuf->SequenceID[0] = ReceiveBuf->SequenceID[0];
+                WrNumOkBuf->SequenceID[1] = ReceiveBuf->SequenceID[1];
+                WrNumOkBuf->SequenceID[2] = ReceiveBuf->SequenceID[2];
+                WrNumOkBuf->SequenceID[3] = ReceiveBuf->SequenceID[3]; //SequenceIDͬ
+                
+                WrNumOkBuf->Command = ReceiveBuf->Command;
+                
+                ReceiveBuf->Value[0] = USART1_RX_BUF[13];
+                ReceiveBuf->Value[1] = USART1_RX_BUF[14];
+                ReceiveBuf->Value[2] = USART1_RX_BUF[15];
+                ReceiveBuf->Value[3] = USART1_RX_BUF[16];
+                ReceiveBuf->Value[4] = USART1_RX_BUF[17];
+
+                idBuf[0] = USART1_RX_BUF[13];
+                idBuf[1] = USART1_RX_BUF[14];
+                idBuf[2] = USART1_RX_BUF[15];
+                idBuf[3] = USART1_RX_BUF[16];
+                idBuf[4] = USART1_RX_BUF[17];
+    
+                newIdFlag = 1;  //2.4Gд
+                count = 0;      //ʱ
+                NRF24L01_RX_Mode(SPI_SEND);
+                
+                SendUSART2Str("0000\n");
+                while(1)   //
+                {
+                    
+                    tmp = DataProc_A0_WriteNum_SPI2();
+                    
+                    if(tmp)
+                        break;
+                }
+                SendUSART2Str("0000\n");
+                
+                ReadAttenID[0]=0;
+                ReadAttenID[1]=0;
+                ReadAttenID[2]=0;
+                ReadAttenID[3]=0;
+                ReadAttenID[4]=0;
+                ResNum_1356[0]=0;
+                ResNum_1356[1]=0;
+                ResNum_1356[2]=0;
+                ResNum_1356[3]=0;
+                ResNum_1356[4]=0;
+                GetNum_1356[0]=0;
+                GetNum_1356[1]=0;
+                GetNum_1356[2]=0;
+                GetNum_1356[3]=0;
+                GetNum_1356[4]=0;
+                    
+//                USART1_REC_Status = 0;
+//                USART1_RX_CNT =0;
+//                for(i=0;i<30;i++)
+//                {
+//                    USART3_RX_BUF[i] = 0;
+//                }
+                ReceiveBuf->Command = 0;    //
+            }
+            
+                
+                break;
+
+            case WriteNumState:             //дŽϱ
+
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case Read_1345Num:            //13.45M A2
+                    //FA 00 00 00 00 00 00 00 00 00 A2 00 00 FB
+					if(first_clear_flag == 0)
+					{
+						memset(ResNum_1356,0,5);
+						//memset(oldResNum_1356,0,5);
+						first_clear_flag = 1;
+					}
+                    if((ResNum_1356[1] == 0) && (ResNum_1356[2] == 0)&& (ResNum_1356[3] == 0)&&(ResNum_1356[4] ==0))
+                    {
+						           break;
+                    }
+					          //ledL;
+                    USART1_RX_CNT = 0;
+                    ReadNumBuf->SequenceID[0] = ReceiveBuf->SequenceID[0];
+                    ReadNumBuf->SequenceID[1] = ReceiveBuf->SequenceID[1];
+                    ReadNumBuf->SequenceID[2] = ReceiveBuf->SequenceID[2];
+                    ReadNumBuf->SequenceID[3] = ReceiveBuf->SequenceID[3]; //SequenceIDͬ
+                    
+                    ReadNumBuf->Command  = ReceiveBuf->Command;
+                    ReadNumBuf->Tag1      = 1;
+                    ReadNumBuf->Length1   = 6;
+                    ReadNumBuf->Value1[0] = 0;      //len=0 Ч
+                    ReadNumBuf->Value1[1] = ResNum_1356[0];
+                    ReadNumBuf->Value1[2] = ResNum_1356[1];
+                    ReadNumBuf->Value1[3] = ResNum_1356[2];
+                    ReadNumBuf->Value1[4] = ResNum_1356[3];
+                    ReadNumBuf->Value1[5] = ResNum_1356[4];
+
+//                    SendUartData(uartSendRdNumData,22,USART2);
+                    
+                    SendConsoleData((char*)uartSendRdNumData,22);   //ԣظPC
+                    delay_ms(50);
+
+                    DegugPrintf(uartSendRdNumData,22);
+                    SendUSART2Str("\n");
+										//ledH;                    
+                    ResNum_1356[0]=0;
+                    ResNum_1356[1]=0;
+                    ResNum_1356[2]=0;
+                    ResNum_1356[3]=0;
+                    ResNum_1356[4]=0;
+//                    USART1_REC_Status = 0;
+//                    USART1_RX_CNT =0;
+//                    for(i=0;i<30;i++)
+//                    {
+//                        USART3_RX_BUF[i] = 0;
+//                    }
+										first_clear_flag = 0;
+
+                    ReceiveBuf->Command = 0;    //
+                   // ledH;
+                break;
+                
+            case Read_24Num:  //A3 һ2.4G
+                //FA 00 00 00 00 00 00 00 00 00 A3 00 00 FB
+/*                        USART1_RX_CNT = 0;
+                        NRF24L01_RX_Mode(SPI_SEND);
+                        count_A34 = 0;
+                        rspFlag_A3 = 1;
+
+                    {
+                        u8 tmp;
+                        SendUSART2Str("3333\n");
+                        while(1)   //
+                        {
+                            
+                            tmp = DataProc_A3_nrf();
+                            
+                            if(tmp)
+                                break;
+                        }
+                        SendUSART2Str("3333\n");
+                        ReadNumBuf->SequenceID[0] = ReceiveBuf->SequenceID[0];
+                        ReadNumBuf->SequenceID[1] = ReceiveBuf->SequenceID[1];
+                        ReadNumBuf->SequenceID[2] = ReceiveBuf->SequenceID[2];
+                        ReadNumBuf->SequenceID[3] = ReceiveBuf->SequenceID[3]; //SequenceIDͬ
+                        
+                        ReadNumBuf->Command  = ReceiveBuf->Command;
+                        ReadNumBuf->Tag1      = 1;
+                        ReadNumBuf->Length1   = 6;
+                        ReadNumBuf->Value1[0] = 0;      //len=0 Ч
+                        ReadNumBuf->Value1[1] = idResA3Buf[0];
+                        ReadNumBuf->Value1[2] = idResA3Buf[1];
+                        ReadNumBuf->Value1[3] = idResA3Buf[2];
+                        ReadNumBuf->Value1[4] = idResA3Buf[3];
+                        ReadNumBuf->Value1[5] = idResA3Buf[4];
+                        
+                            
+                        DegugPrintf(uartSendRdNumData,22);
+                        SendUSART2Str("\n");
+                        
+                        SendConsoleData(uartSendRdNumData,22);   //ԣظPC
+                        delay_ms(50);
+
+                            
+                        //дֹһдӰ
+                        ReadAttenID[0]=0;
+                        ReadAttenID[1]=0;
+                        ReadAttenID[2]=0;
+                        ReadAttenID[3]=0;
+                        ReadAttenID[4]=0;
+                        ResNum_1356[0]=0;
+                        ResNum_1356[1]=0;
+                        ResNum_1356[2]=0;
+                        ResNum_1356[3]=0;
+                        ResNum_1356[4]=0;
+                        GetNum_1356[0]=0;
+                        GetNum_1356[1]=0;
+                        GetNum_1356[2]=0;
+                        GetNum_1356[3]=0;
+                        GetNum_1356[4]=0;  
+
+//                        USART1_REC_Status = 0;
+//                        USART1_RX_CNT =0;
+//                        for(i=0;i<30;i++)
+//                        {
+//                            USART3_RX_BUF[i] = 0;
+//                        }
+                        ReceiveBuf->Command = 0;    //
+                        
+                    }
+                
+  */              break;
+                
+            case ReadCardNum:   //A4 
+                    USART1_RX_CNT = 0;
+                    //SendConsoleByte(protocol_config_flg);   //ԣظPC
+                    //NRF24L01_RX_Mode_NOACK(SPI_SEND);//NOACKģʽ
+                    #if APP
+                    NRF24L01_RX_Mode_NOACK(SPI_SEND,protocol_config_flg);//NOACK??,?????
+                    #else
+                    NRF24L01_RX_Mode_NOACK(SPI_SEND);////NOACKģʽ
+                    #endif
+                        count_A34 = 0;
+                    {
+                        u8 tmp;
+                        SendUSART2Str("4444\n");
+                        while(1)   //
+                        {
+                            
+                            tmp = DataProc_A4_nrf();
+                            
+                            if(tmp)
+                                break;
+                        }
+																						
+                        SendUSART2Str("4444\n");
+                        ReadNumBuf->SequenceID[0] = ReceiveBuf->SequenceID[0];
+                        ReadNumBuf->SequenceID[1] = ReceiveBuf->SequenceID[1];
+                        ReadNumBuf->SequenceID[2] = ReceiveBuf->SequenceID[2];
+                        ReadNumBuf->SequenceID[3] = ReceiveBuf->SequenceID[3]; //SequenceID
+                        
+                        ReadNumBuf->Command  = ReceiveBuf->Command;
+                        ReadNumBuf->Tag1      = 1;
+                        ReadNumBuf->Length1   = 6;
+                        ReadNumBuf->Value1[0] = 0;      //
+                        ReadNumBuf->Value1[1] = ReadAttenID[0];
+                        ReadNumBuf->Value1[2] = ReadAttenID[1];
+                        ReadNumBuf->Value1[3] = ReadAttenID[2];
+                        ReadNumBuf->Value1[4] = ReadAttenID[3];
+                        ReadNumBuf->Value1[5] = ReadAttenID[4];
+ 
+                            
+                        SendConsoleData((char*)uartSendRdNumData,22);   //ԣظPC
+                        delay_ms(50);
+
+                        DegugPrintf(uartSendRdNumData,22);
+                        SendUSART2Str("\n");
+                            
+                        //дֹһдӰ
+                        ReadAttenID[0]=0;
+                        ReadAttenID[1]=0;
+                        ReadAttenID[2]=0;
+                        ReadAttenID[3]=0;
+                        ReadAttenID[4]=0;
+                        ResNum_1356[0]=0;
+                        ResNum_1356[1]=0;
+                        ResNum_1356[2]=0;
+                        ResNum_1356[3]=0;
+                        ResNum_1356[4]=0;
+                        GetNum_1356[0]=0;
+                        GetNum_1356[1]=0;
+                        GetNum_1356[2]=0;
+                        GetNum_1356[3]=0;
+                        GetNum_1356[4]=0;
+                        //memset(ResNum_1356,0,5);
+                        
+                        ReceiveBuf->Command = 0;    //
+                        
+                    }
+                break;
+#if APP1
+			case Config24Agreement:
+                
+				protocol_config_flg = USART1_RX_BUF[13];
+                ConfigKaoQinBuf->SequenceID[0] = ReceiveBuf->SequenceID[0];
+                ConfigKaoQinBuf->SequenceID[1] = ReceiveBuf->SequenceID[1];
+                ConfigKaoQinBuf->SequenceID[2] = ReceiveBuf->SequenceID[2];
+                ConfigKaoQinBuf->SequenceID[3] = ReceiveBuf->SequenceID[3]; //SequenceID
+                ConfigKaoQinBuf->Command = ReceiveBuf->Command;
+				ConfigKaoQinBuf->Control =0x01;
+                SendConsoleData((char*)uartSendConfigKaoQinData,14);   //ԣظPC
+                delay_ms(50);
+#if 1
+                StoreBuffer[0] = protocol_config_flg;//޸Э汾
+                SavePara_to_flash();    //ݵFlash
+                //Readpara_from_flash();  //ݲӡ
+                //protocol_config_flg = Save_Buffer[2*0];
+#endif 
+                //SendConsoleByte(protocol_config_flg);   //ԣظPC
+                //SendConsoleByte(0xff);
+                //SendConsoleByte(protocol_config_flg);
+                //дֹһдӰ
+                ReadAttenID[0]=0;
+                ReadAttenID[1]=0;
+                ReadAttenID[2]=0;
+                ReadAttenID[3]=0;
+                ReadAttenID[4]=0;
+                ResNum_1356[0]=0;
+                ResNum_1356[1]=0;
+                ResNum_1356[2]=0;
+                ResNum_1356[3]=0;
+                ResNum_1356[4]=0;
+                GetNum_1356[0]=0;
+                GetNum_1356[1]=0;
+                GetNum_1356[2]=0;
+                GetNum_1356[3]=0;
+                GetNum_1356[4]=0;
+                ReceiveBuf->Command = 0;    //??
+            
+				break;
+#endif
+            case UpdateFirmversion:            //̼
+//                printf("UpdateFirmversion\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case UpdateFirm:            //̼
+//                printf("UpdateFirm\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            case UpdateFirmState:            //̼ϱ
+//                printf("UpdateFirmState\n");
+                //ݴ
+                
+                ReceiveBuf->Command = 0;    //
+                break;
+
+            default:
+                break;
+        }
+
+
+        
+        USART1_REC_Status = 0;                      //
+        //USART1_RX_CNT = 0;
+
+    }
+    
+}
+
+void DataProc_Nrf24l01(void)
+{
+    u8 buffer[32];
+    u8 temp;
+    IWDG_Feed();
+    
+    if(newIdFlag==1)
+    {
+        newIdFlag = 0;
+        recFlag = 0;
+        txBuf[0] = 0xfc;
+        txBuf[1] = 0x11;
+        if(idBuf[0]==GetNum_1356[0] && idBuf[1]==GetNum_1356[1] && idBuf[2]==GetNum_1356[2] && idBuf[3]==GetNum_1356[3] && idBuf[4]==GetNum_1356[4])
+        {
+            txBuf[2] = idBuf[0];
+            txBuf[3] = idBuf[1];
+            txBuf[4] = idBuf[2];
+            txBuf[5] = idBuf[3];
+            txBuf[6] = idBuf[4];
+        }
+        
+        txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+		SPI1_CE =0;
+        NRF24L01_Write_Reg(SPI_REV,FLUSH_TX,0xff);//TX FIFOĴ 
+		NRF24L01_Write_Buf(SPI_REV,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF 8ֽڣԶ
+		NRF24L01_RX_Mode(SPI_REV);      //24L01Ϊģʽ
+        rspFlag = 1;
+        count=0;
+        IWDG_Feed();
+        
+    }
+    
+
+    
+    if(rspFlag) //⿨ϵ緢͵
+    {
+        IWDG_Feed();
+        if(count<=2000) //1.5Sδյ2.4GظźţrspFlagʧЧ
+        {
+            if(SPI1_IRQ == 0)   //24L01յ⿨ϵ緢͵
+            {
+                IWDG_Feed();
+                temp = NRF24L01_RxPacket(SPI_REV,buffer);
+//                SendConsoleByte(temp);
+
+                if((temp&0x40)==0x40)   //յʾ
+                {
+                    buffer[RX_PLOAD_WIDTH]='\0';
+                    led0=~led0;
+
+//                    SendConsoleData(buffer,RX_PLOAD_WIDTH); //
+
+                    if((buffer[1]==idBuf[0])&& (buffer[2]==idBuf[1])&&(buffer[3]==idBuf[2])&&(buffer[4]==idBuf[3])&&(buffer[5]==idBuf[4]))    //յд
+                    {
+                        if((buffer[1]==GetNum_1356[0])&& (buffer[2]==GetNum_1356[1])&&(buffer[3]==GetNum_1356[2])&&(buffer[4]==GetNum_1356[3])&&(buffer[5]==GetNum_1356[4]))
+                        {
+                            if(rspFlag == 1)
+                            {
+                                rspFlag++;
+                                txBuf[1] = 0x12;             ///0xfc + cmd(0x12) +id +crc   ----cmd=0x12 ȷ
+                                txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+                                NRF24L01_Write_Buf(SPI_REV,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF 8ֽڣԶ
+                            }
+                            else
+                            {
+                                rspFlag=0;  //IDѾ£rspFlag㣬
+                                count = 0;  //
+                                idBuf[0]=0;
+                                WrNumOkBuf->Control = 0x10; //д
+                                SendConsoleData((char*)uartSendWrNumOkData,14);   //ԣظPC
+                                
+                            }
+                        }
+                        
+                        
+                    }
+                    else
+                    {
+                        SPI1_CE =0;
+                        txBuf[1] = 0x11;
+                        txBuf[7] = CheckSum(txBuf,7);   //дŵtxBuf
+                        NRF24L01_Write_Buf(SPI_REV,W_ACK_PAYLOAD,txBuf,8);   //дݵTX BUF  8ֽ
+                        SPI1_CE =1;
+                    }
+                }
+            }
+            
+        }
+        else    //2sʱظ
+        {
+            IWDG_Feed();
+            rspFlag=0;  //IDѾ£rspFlag㣬
+            count = 0;  //
+            
+            idBuf[0]=0;
+            idBuf[1]=0;
+            idBuf[2]=0;
+            idBuf[3]=0;
+            idBuf[4]=0;
+            GetNum_1356[0]=0;
+            GetNum_1356[1]=0;
+            GetNum_1356[2]=0;
+            GetNum_1356[3]=0;
+            GetNum_1356[4]=0;
+            
+            WrNumOkBuf->Control = 0x30; //
+            SendConsoleData((char*)uartSendWrNumOkData,14);   //ԣظPC
+        }
+        
+    }
+}
+
+ //------------------------------------------------------------------
+//void TIM3_IRQHandler(void)
+//null
+//زnull
+//˵ʱ3жϷ
+//------------------------------------------------------------------
+void TIM3_IRQHandler(void)
+{ 
+  if(TIM_GetITStatus(TIM3,TIM_IT_Update)!=RESET)        //жǷΪʱ3ж
+  {
+	 TIM_ClearITPendingBit(TIM3, TIM_IT_Update);  //жϱ
+	 count ++;
+     count_A34 ++;
+     count_num ++;
+     if(HW_Open)
+     {
+        GPIO_SetBits(GPIOC,GPIO_Pin_9);   //򿪺ɨǹ
+        HW_OpenCount ++;
+        if(HW_OpenCount>=400)
+        {
+            GPIO_ResetBits(GPIOC,GPIO_Pin_9);   //رպɨǹ
+            HW_OpenCount = 0;
+            HW_Open = 0;
+        }
+
+     }
+     if(count_num==5000)
+     {
+        count_num = 0;
+//        printf("1356_0=%x\r\n",GetNum_1356[0]);
+//        printf("1356_1=%x\r\n",GetNum_1356[1]);
+//        printf("1356_2=%x\r\n",GetNum_1356[2]);
+//        printf("1356_3=%x\r\n",GetNum_1356[3]);
+//        printf("1356_4=%x\r\n",GetNum_1356[4]);
+//        
+//        printf("2.4G_0=%x\r\n",idBuf[0]);
+//        printf("2.4G_1=%x\r\n",idBuf[1]);
+//        printf("2.4G_2=%x\r\n",idBuf[2]);
+//        printf("2.4G_3=%x\r\n",idBuf[3]);
+//        printf("2.4G_4=%x\r\n",idBuf[4]);
+     }
+	 flag_1ms = 1;
+  }
+}
diff --git a/bsp/DataProc.h b/bsp/DataProc.h
new file mode 100644
index 0000000..6eae86f
--- /dev/null
+++ b/bsp/DataProc.h
@@ -0,0 +1,64 @@
+#ifndef _DATAPROC_H
+#define _DATAPROC_H
+#include "stm32f10x.h"
+#include "nrf24L01.h"
+#include "delay.h"
+#include "printf.h"
+#include "led.h"
+#include "USART2.h"
+#include "stmflash.h"
+
+
+void DataProc_Nrf24l01(void);
+void DataProc_Nrf24l01_SPI2(void);
+
+u8 DataProc_A0_WriteNum_SPI2(void);
+u8 DataProc_A3_nrf(void);
+u8 DataProc_A4_nrf(void);
+
+void DataProc_RecNrf24L01(void);
+void Usart1_Process(void);
+
+void DataProc_1356(void);
+void DataProc_USART3(void);
+void Data_Init(void);
+void DataProc_USART1(void);
+
+#define TestFlashAddr 0x80020000
+
+enum
+{
+    Reset = 0x21,           //Ķλ
+    GetFirmversion = 0x22,  //ȡ̼汾
+    
+    SetReaderID = 0x25,     //ĶID
+    GetReaderID = 0x26,     //ȡĶID
+    
+    DelWhite = 0x71,        //ɾ
+    OpenWhite = 0x73,       //򿪰
+    CloseWhite = 0x74,      //رհ
+    AddWhite = 0x75,        //Ӱ
+    GetWhite = 0x78,        //ȡ
+    
+    Heart = 0x82,           //
+    
+    GetWhiteState = 0x94    //ȡ״̬
+};
+
+enum
+{
+    WriteNum = 0xA0,    //A0д
+    WriteNumState,      //A1дŽϱ
+    Read_1345Num,       //A2ٶһο
+    Read_24Num,         //A3
+    ReadCardNum,        //A42.4G
+    UpdateFirmversion,  //A5̼
+    UpdateFirm,         //A6̼
+    UpdateFirmState,    //A7ϱ
+#if APP1
+    Config24Agreement,   //A8??????
+#endif
+    
+};
+
+#endif
diff --git a/bsp/LCD.c b/bsp/LCD.c
new file mode 100644
index 0000000..276a586
--- /dev/null
+++ b/bsp/LCD.c
@@ -0,0 +1,926 @@
+#include "LCD.h"
+
+u8 ucDispDT;
+
+static const u8 font816[38][16]=
+{
+	{0xF8,0xFC,0x04,0xC4,0x24,0xFC,0xF8,0x00,0x07,0x0F,0x09,0x08,0x08,0x0F,0x07,0x00},  // -0-
+	{0x00,0x10,0x18,0xFC,0xFC,0x00,0x00,0x00,0x00,0x08,0x08,0x0F,0x0F,0x08,0x08,0x00},  // -1-
+	{0x08,0x0C,0x84,0xC4,0x64,0x3C,0x18,0x00,0x0E,0x0F,0x09,0x08,0x08,0x0C,0x0C,0x00},  // -2-
+	{0x08,0x0C,0x44,0x44,0x44,0xFC,0xB8,0x00,0x04,0x0C,0x08,0x08,0x08,0x0F,0x07,0x00},  // -3-
+	{0xC0,0xE0,0xB0,0x98,0xFC,0xFC,0x80,0x00,0x00,0x00,0x00,0x08,0x0F,0x0F,0x08,0x00},  // -4-
+	{0x7C,0x7C,0x44,0x44,0xC4,0xC4,0x84,0x00,0x04,0x0C,0x08,0x08,0x08,0x0F,0x07,0x00},  // -5-
+	{0xF0,0xF8,0x4C,0x44,0x44,0xC0,0x80,0x00,0x07,0x0F,0x08,0x08,0x08,0x0F,0x07,0x00},  // -6-
+	{0x0C,0x0C,0x04,0x84,0xC4,0x7C,0x3C,0x00,0x00,0x00,0x0F,0x0F,0x00,0x00,0x00,0x00},  // -7-
+	{0xB8,0xFC,0x44,0x44,0x44,0xFC,0xB8,0x00,0x07,0x0F,0x08,0x08,0x08,0x0F,0x07,0x00},  // -8-
+	{0x38,0x7C,0x44,0x44,0x44,0xFC,0xF8,0x00,0x00,0x08,0x08,0x08,0x0C,0x07,0x03,0x00},  // -9-
+	{0xE0,0xF0,0x98,0x8C,0x98,0xF0,0xE0,0x00,0x0F,0x0F,0x00,0x00,0x00,0x0F,0x0F,0x00},  // -A- 10
+	{0x04,0xFC,0xFC,0x44,0x44,0xFC,0xB8,0x00,0x08,0x0F,0x0F,0x08,0x08,0x0F,0x07,0x00},  // -B- 11
+	{0xF0,0xF8,0x0C,0x04,0x04,0x0C,0x18,0x00,0x03,0x07,0x0C,0x08,0x08,0x0C,0x06,0x00},  // -C- 12
+	{0x04,0xFC,0xFC,0x04,0x0C,0xF8,0xF0,0x00,0x08,0x0F,0x0F,0x08,0x0C,0x07,0x03,0x00},  // -D- 13
+	{0x04,0xFC,0xFC,0x44,0xE4,0x0C,0x1C,0x00,0x08,0x0F,0x0F,0x08,0x08,0x0C,0x0E,0x00},  // -E- 14
+	{0x04,0xFC,0xFC,0x44,0xE4,0x0C,0x1C,0x00,0x08,0x0F,0x0F,0x08,0x00,0x00,0x00,0x00},  // -F- 15	
+	{0xF0,0xF8,0x0C,0x84,0x84,0x8C,0x98,0x00,0x03,0x07,0x0C,0x08,0x08,0x07,0x0F,0x00},  // -G- 16		
+	{0xFC,0xFC,0x40,0x40,0x40,0xFC,0xFC,0x00,0x0F,0x0F,0x00,0x00,0x00,0x0F,0x0F,0x00},  // -H- 17		
+	{0x00,0x00,0x04,0xFC,0xFC,0x04,0x00,0x00,0x00,0x00,0x08,0x0F,0x0F,0x08,0x00,0x00},  // -I- 18	
+	{0x00,0x00,0x00,0x04,0xFC,0xFC,0x04,0x00,0x07,0x0F,0x08,0x08,0x0F,0x07,0x00,0x00},  // -J- 19	
+	{0x04,0xFC,0xFC,0xC0,0xF0,0x3C,0x0C,0x00,0x08,0x0F,0x0F,0x00,0x01,0x0F,0x0E,0x00},  // -K- 20	
+	{0x04,0xFC,0xFC,0x04,0x00,0x00,0x00,0x00,0x08,0x0F,0x0F,0x08,0x08,0x0C,0x0E,0x00},  // -L- 21	
+	{0xFC,0xFC,0x38,0x70,0x38,0xFC,0xFC,0x00,0x0F,0x0F,0x00,0x00,0x00,0x0F,0x0F,0x00},  // -M- 22	
+	{0xFC,0xFC,0x38,0x70,0xE0,0xFC,0xFC,0x00,0x0F,0x0F,0x00,0x00,0x00,0x0F,0x0F,0x00},  // -N- 23	
+	{0xF0,0xF8,0x0C,0x04,0x0C,0xF8,0xF0,0x00,0x03,0x07,0x0C,0x08,0x0C,0x07,0x03,0x00},  // -O- 24		
+	{0x04,0xFC,0xFC,0x44,0x44,0x7C,0x38,0x00,0x08,0x0F,0x0F,0x08,0x00,0x00,0x00,0x00},  // -P- 25		
+	{0xF8,0xFC,0x04,0x04,0x04,0xFC,0xF8,0x00,0x07,0x0F,0x08,0x0E,0x3C,0x3F,0x27,0x00},  // -Q- 26		
+	{0x04,0xFC,0xFC,0x44,0xC4,0xFC,0x38,0x00,0x08,0x0F,0x0F,0x00,0x00,0x0F,0x0F,0x00},  // -R- 27		
+	{0x18,0x3C,0x64,0x44,0xC4,0x9C,0x18,0x00,0x06,0x0E,0x08,0x08,0x08,0x0F,0x07,0x00},  // -S- 28	
+	{0x00,0x1C,0x0C,0xFC,0xFC,0x0C,0x1C,0x00,0x00,0x00,0x08,0x0F,0x0F,0x08,0x00,0x00},  // -T- 29		
+	{0xFC,0xFC,0x00,0x00,0x00,0xFC,0xFC,0x00,0x07,0x0F,0x08,0x08,0x08,0x0F,0x07,0x00},  // -U- 30		
+	{0xFC,0xFC,0x00,0x00,0x00,0xFC,0xFC,0x00,0x01,0x03,0x06,0x0C,0x06,0x03,0x01,0x00},  // -V- 31	
+	{0xFC,0xFC,0x00,0x80,0x00,0xFC,0xFC,0x00,0x03,0x0F,0x0E,0x03,0x0E,0x0F,0x03,0x00},  // -W- 32		
+	{0x0C,0x3C,0xF0,0xC0,0xF0,0x3C,0x0C,0x00,0x0C,0x0F,0x03,0x00,0x03,0x0F,0x0C,0x00},  // -X- 33	
+	{0x00,0x3C,0x7C,0xC0,0xC0,0x7C,0x3C,0x00,0x00,0x00,0x08,0x0F,0x0F,0x08,0x00,0x00},  // -Y- 34		
+	{0x1C,0x0C,0x84,0xC4,0x64,0x3C,0x1C,0x00,0x0E,0x0F,0x09,0x08,0x08,0x0C,0x0E,0x00},  // -Z- 35
+	{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x0C,0x00,0x00,0x00},  // -.- 36
+	{0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x00,0x00,0x00},  // -:- 37
+
+};
+void Get_8x16_Font(u16 character ,u8* backbuf)
+{
+	if( (character>='0')&&(character<='9'))
+	{
+		character -= '0';
+	}
+#if 1
+	else if( (character>='A')&&(character<='Z'))
+	{
+		character = character - 'A' + 10;
+	}
+#endif
+	else if(character == ':')
+	{
+		character = 37;
+	}
+	else if(character == '.')
+	{
+		character = 36;
+	}
+	//backbuf = (uint8 *)(Num612[character]);
+	memcpy(backbuf, (u8 *)(font816[character]),sizeof(font816[character]));          
+}
+#if 1
+void HexToDec(u32 tempdata,u8* buf,unsigned char bufLen)
+{
+	buf[0]=tempdata/1000000000;
+	buf[1]=tempdata/100000000-(buf[0]*10);
+	buf[2]=tempdata/10000000-(buf[0]*100)-(buf[1]*10);
+	buf[3]=tempdata/1000000-buf[0]*1000-buf[1]*100-buf[2]*10;
+	buf[4]=tempdata/100000-buf[0]*10000-buf[1]*1000-buf[2]*100-buf[3]*10;
+	buf[5]=tempdata/10000-buf[0]*100000-buf[1]*10000-buf[2]*1000-buf[3]*100-buf[4]*10;
+	buf[6]=tempdata/1000-buf[0]*1000000-buf[1]*100000-buf[2]*10000-buf[3]*1000-buf[4]*100-buf[5]*10;
+	buf[7]=tempdata/100-buf[0]*10000000-buf[1]*1000000-buf[2]*100000-buf[3]*10000-buf[4]*1000-buf[5]*100-buf[6]*10;
+	buf[8]=tempdata/10-buf[0]*100000000-buf[1]*10000000-buf[2]*1000000-buf[3]*100000-buf[4]*10000-buf[5]*1000-buf[6]*100-buf[7]*10;
+	buf[9]=tempdata-buf[0]*1000000000-buf[1]*100000000-buf[2]*10000000-buf[3]*1000000-buf[4]*100000-buf[5]*10000-buf[6]*1000-buf[7]*100-buf[8]*10;
+}
+#endif
+
+void AttenuatorConfig(void)
+{
+	GPIO_InitTypeDef  GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;	   //1A		   
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //50MHz
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;	   //2A	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;  //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;	   //3A   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;  //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;	   //4A	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;  //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;	   //5A	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;  //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+#if 1  //˥Ч
+	GPIO_SetBits(GPIOA,GPIO_Pin_8);
+	GPIO_SetBits(GPIOC,GPIO_Pin_8);
+	GPIO_SetBits(GPIOC,GPIO_Pin_4);
+	GPIO_SetBits(GPIOC,GPIO_Pin_5);
+	GPIO_SetBits(GPIOC,GPIO_Pin_14);
+#else
+	GPIO_ResetBits(GPIOA,GPIO_Pin_8);
+	GPIO_ResetBits(GPIOC,GPIO_Pin_8);
+	GPIO_ResetBits(GPIOC,GPIO_Pin_4);
+	GPIO_ResetBits(GPIOC,GPIO_Pin_5);
+	GPIO_ResetBits(GPIOC,GPIO_Pin_14);
+#endif
+
+}
+
+void lcd_init(void)
+{
+	GPIO_InitTypeDef  GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;	   //LCD  POWER		   
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;	   //LCD  CS 	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;	   //LCD  RES	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;	   //LCD  AO 	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+	
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;	   //LCD  SCK 	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+	
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;	   //LCD  SDA Ҫ 	   
+	//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	 
+	//GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //50MHz
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+	
+	GPIO_SetBits(GPIOC,GPIO_Pin_0);
+
+	vDispInit(0,24);
+	vDispClear();
+   
+}
+
+void _vWriteIR_spi(u8 ucData);	
+void _vWriteData_spi(void);
+void (* WriteIR)(u8); //20120502 hong   ָ룬ָ _vWriteIR  _vWriteIR_spi
+void (* WriteData)(void);				//20120502        ָ룬ָ_vWriteData_vWriteData_spi
+
+#if 0
+__inline void IRQEnable(void) 
+{
+	int tmp;
+	__asm
+	{
+    MRS tmp,CPSR       ///ȡCPSRֵ
+    BIC tmp,tmp,#0x80 //IRQжϽֹλI,IRQж 
+    MSR CPSR_c,tmp    //CPSRֵ
+	}
+}
+
+
+__inline void IRQDisable(void)
+{
+    int tmp;
+	
+    __asm 
+    {
+        MRS tmp,CPSR       ///ȡCPSRֵ
+        ORR tmp,tmp,#0x80 //IRQжϽֹλI,IRQж 
+        MSR CPSR_c,tmp    //CPSRֵ
+    }
+}
+#endif
+
+#if 0
+void SetDISPDATA( u8 DISPDATA )
+{
+    IO2SET = IO2SET | DISPDATA;
+    IO2CLR = (~IO2SET) | ((~DISPDATA) &0x000000ff);
+}
+#endif
+u32 vI2cHzkGetStart( u32 addr /*Int32 addr*/ )
+{
+    //ulong HfcAdd;
+	u32 HfcAdd;
+    HfcAdd = addr >> 8;
+    HfcAdd *= 264;
+    HfcAdd += (addr & 0xff);
+    return ( HfcAdd );
+
+}
+
+/**************************************************************
+ Һд
+ ucData--
+ л첨
+ 20080710xiehb
+*************************************************************/
+void _vWriteIR_spi(u8 ucData)
+{
+	u8 i;
+    // ж
+	ucData = ucData;
+    //IRQDisable();
+    //SPI1_CE = 0;
+	//P2WPin_HIGH(PIN_LCD_SDA);
+	//LCD_SDA_OUTMODE_SET;
+	GPIO_SetBits(GPIOC,GPIO_Pin_12);
+	//WPin(P2, PIN_LCD_CS0, 0);
+	//LCD_CS0_OUTMODE_CLEAR;
+	GPIO_ResetBits(GPIOC,GPIO_Pin_2);	
+	//P2WPin_LOW(PIN_LCD_DC);
+	//LCD_DC_OUTMODE_CLEAR;
+	GPIO_ResetBits(GPIOC,GPIO_Pin_10);	
+	for ( i = 0; i < 8; i++ )
+	{
+		//P2WPin_LOW(PIN_LCD_SCL);
+		//LCD_SCL_OUTMODE_CLEAR;
+		GPIO_ResetBits(GPIOC,GPIO_Pin_11);
+		if ( (ucData & 0x80) == 0 )
+		{
+			//P2WPin_LOW(PIN_LCD_SDA);
+			//LCD_SDA_OUTMODE_CLEAR;
+			GPIO_ResetBits(GPIOC,GPIO_Pin_12);
+		}
+		else
+		{
+			//P2WPin_HIGH(PIN_LCD_SDA);
+			//LCD_SDA_OUTMODE_SET;
+			GPIO_SetBits(GPIOC,GPIO_Pin_12);
+		}
+		ucData = ucData << 1;
+		//P2WPin_HIGH(PIN_LCD_SCL);
+		//LCD_SCL_OUTMODE_SET;
+		GPIO_SetBits(GPIOC,GPIO_Pin_11);
+	}
+	//WPin(P2, PIN_LCD_CS0, 1);   
+	//LCD_CS0_OUTMODE_SET;
+	GPIO_SetBits(GPIOC,GPIO_Pin_2);
+	//P2WPin_HIGH(PIN_LCD_SDA);
+	//LCD_SDA_OUTMODE_SET;
+	GPIO_SetBits(GPIOC,GPIO_Pin_12);  
+    // ж 
+    //IRQEnable();
+    //SPI1_CE = 1;
+
+}
+
+/**************************************************************
+ Һдݺ
+ ucDispDT--
+ л첨
+ 20080710xiehb
+*************************************************************/
+void _vWriteData_spi()
+{
+	u8 i;
+    // ж
+    //IRQDisable();
+	//SPI1_CE = 0;
+
+	//P2WPin_HIGH(PIN_LCD_SDA);
+	//LCD_SDA_OUTMODE_SET;
+	GPIO_SetBits(GPIOC,GPIO_Pin_12);
+	//WPin(P2, PIN_LCD_CS0, 0);
+	//LCD_CS0_OUTMODE_CLEAR;
+	GPIO_ResetBits(GPIOC,GPIO_Pin_2);
+
+	//P2WPin_HIGH(PIN_LCD_DC);
+	//LCD_DC_OUTMODE_SET;
+	GPIO_SetBits(GPIOC,GPIO_Pin_10);
+	for ( i = 0; i < 8; i++ )
+	{
+		//P2WPin_LOW(PIN_LCD_SCL);
+		//LCD_SCL_OUTMODE_CLEAR;
+		GPIO_ResetBits(GPIOC,GPIO_Pin_11);		
+		if ( (ucDispDT & 0x80) == 0 )
+		{
+			//P2WPin_LOW(PIN_LCD_SDA);
+			//LCD_SDA_OUTMODE_CLEAR;
+			GPIO_ResetBits(GPIOC,GPIO_Pin_12);
+		}
+		else
+		{
+			//P2WPin_HIGH(PIN_LCD_SDA);
+			//LCD_SDA_OUTMODE_SET;
+			GPIO_SetBits(GPIOC,GPIO_Pin_12);
+		}
+		ucDispDT = ucDispDT << 1;
+		//P2WPin_HIGH(PIN_LCD_SCL);
+		//LCD_SCL_OUTMODE_SET;
+		GPIO_SetBits(GPIOC,GPIO_Pin_11);	
+	}
+	//WPin(P2, PIN_LCD_CS0, 1);    
+	//LCD_CS0_OUTMODE_SET;
+	GPIO_SetBits(GPIOC,GPIO_Pin_2);
+	//P2WPin_HIGH(PIN_LCD_SDA);
+	//LCD_SDA_OUTMODE_SET;
+	GPIO_SetBits(GPIOC,GPIO_Pin_12);
+
+    // ж 
+    //IRQEnable();
+    //SPI1_CE = 1;
+}
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////
+//******************************************************************
+// : void     _vDispAddr(uchar  ucPage,uchar  ucCol)
+// : ʾַ
+// : ucPageҳַucColеַ
+// ֵ:
+//******************************************************************
+void   _vDispAddr(u8  ucPage,u8  ucCol)
+{	
+#if 0
+	if ( GetMainBoardType () == MAINBOARD_TYPE_GENERAL )
+	{
+		ucCol += 1;
+	}
+#endif	
+	(*WriteIR)(0xb0+ucPage);			// ҳַ
+	
+	(*WriteIR)(0x10+(ucCol >> 4));//modify by  ljc20071017	  // ʾʼи4λ
+	(*WriteIR)( ucCol & 0x0f);//modify by  ljc20071017	// ʾʼе4λ
+}
+
+//******************************************************************
+// : void     vDispOn()
+// : ʾ
+// :
+// ֵ:
+//******************************************************************
+void vDispOn(void)
+{
+    //have adjust
+    (*WriteIR)(0xaf); // ôʾ
+}
+
+//******************************************************************
+// : void     vDispClear()
+// : ʾ
+// :
+// ֵ:
+//******************************************************************
+void vDispClear(void)
+{
+    u8 i,j;
+
+    //have adjust
+    for ( i = 0; i < 8; i++ )
+    {
+        ucDispDT = 0;
+        _vDispAddr(i, 0);
+        for ( j = 0; j < 133; j++ )
+        {
+            // 128
+            (*WriteData)();
+        }
+
+    }
+    (*WriteIR)(0xaf); // ʾ
+    (*WriteIR)(0x2f); // Power   //20070913heq //20071108heq
+    
+}
+
+//******************************************************************
+// : void     vDispFull()
+// : ʾ
+// :
+// ֵ:
+//******************************************************************
+void vDispFull ( void )
+{
+	u8 i,j;
+
+	//have adjust
+	for ( i = 0; i < 8; i++ )
+	{
+		_vDispAddr(i, 0);
+		for ( j = 0; j < 133; j++ )
+		{
+			ucDispDT = 0xFF;
+			(*WriteData)();
+		}
+	}
+	(*WriteIR)(0xaf); // ʾ
+	(*WriteIR)(0x2f); // Power	 //20070913heq //20071108heq
+	
+}
+
+//#ifdef SPI_LCD_ENABLE //20110704 liugz
+/********************************************
+SPI ʼ
+20080710xiehb
+*********************************************/
+void  vDispInit_spi(u8 mode,u8 contrast) 
+{
+   if ( mode )
+   {
+	   //LCD_SDA_OUTMODE_SET;
+	   GPIO_SetBits(GPIOC,GPIO_Pin_12);
+	   delay_5us(1);
+	   //LCD_RST_OUTMODE_SET;
+	   GPIO_SetBits(GPIOC,GPIO_Pin_3);
+
+	   //LCD_CS0_OUTMODE_CLEAR;
+	   GPIO_ResetBits(GPIOC,GPIO_Pin_2);
+
+	   //vDelayMS(5);
+	   delay_ms(5);
+	   //LCD_RST_OUTMODE_CLEAR;
+	   GPIO_ResetBits(GPIOC,GPIO_Pin_3);
+
+	   //vDelayMS(30);	
+	   delay_ms(30);
+	   //LCD_RST_OUTMODE_SET;
+	   GPIO_SetBits(GPIOC,GPIO_Pin_3);
+
+	   //vDelayMS(19);
+	   delay_ms(19);
+   }
+   //LCD_CS0_OUTMODE_CLEAR;
+   GPIO_ResetBits(GPIOC,GPIO_Pin_2);
+
+   //LCD_SDA_OUTMODE_SET;
+   GPIO_SetBits(GPIOC,GPIO_Pin_12);
+
+   //LCD_RST_OUTMODE_SET;
+   GPIO_SetBits(GPIOC,GPIO_Pin_3);
+
+   (*WriteIR)(0xe2);
+   delay_ms(10);
+   (*WriteIR)(0xa2); 						/* 1/9bias */
+   (*WriteIR)(0xa0); 						/* ADC select , Normal */
+   (*WriteIR)(0xc8); 						/* Common output reverse */
+   (*WriteIR)(0xa6); 						/* normal display 1=on */
+#if 0
+   if ( GetMainBoardType () != MAINBOARD_TYPE_GENERAL )
+   {
+   	  (*WriteIR)(0x2C); 
+	  DeyNop(10);
+	  (*WriteIR)(0x2E); 
+	  DeyNop(10);
+   }
+#endif
+   (*WriteIR)(0x2F); 						/* V/C off, V/R off, V/F on */
+   //DeyNop(10);
+   delay_5us(2);
+   (*WriteIR)(0xf8); 						/* Common output reverse */
+   (*WriteIR)(0x01); 						/* normal display 1=on */
+   //(*WriteIR)(0x2F); 						/* V/C off, V/R off, V/F on */
+   (*WriteIR)(0x24); 						/* internal resistor ratio */
+#if 0
+   if ( contrast > MAX_CONTRAST )
+   {
+	  contrast = 0x24;
+   }
+   if ( contrast < MIN_CONTRAST )
+   {
+	  contrast = 0x24;	
+   }
+#else
+	contrast = 0x27;   //24
+#endif   
+   (*WriteIR)(0x81); 						/* electronic volume mode set */	
+   (*WriteIR)(contrast);                    /*0x31*/
+   (*WriteIR)(0xaf); 						/* display on */
+   (*WriteIR)(0x40); 						/* Start line Set 40-7fh  Ĭ40 */ //20110720 liugz  //60
+}
+
+///20120925 hong ʶ
+void  vDispInit( u8 mode,u8 contrast )
+{
+	WriteIR = _vWriteIR_spi;
+	WriteData = _vWriteData_spi;
+	vDispInit_spi(mode,contrast);
+}
+
+#if 1
+/*****************************************************************
+E_MAINBOARD_TYPE GetMainBoardType ( void )
+ܣ
+
+ע⣺
+ƣΰ
+ʱ䣺2014.06.28
+أ
+******************************************************************/
+void  SetLcdRow ( u8 * ucRow )
+{
+	//if ( GetMainBoardType () != MAINBOARD_TYPE_GENERAL )
+	{
+		if ( *ucRow < 3 )
+		{
+			*ucRow += 2;
+		}
+		else
+		{
+			*ucRow -= 2;
+		}
+	}
+}
+#endif
+
+//******************************************************************
+// : void     vDispClearLine(uchar  ucRow)
+// : LCDһ
+// : ucRowк
+// ֵ:
+//******************************************************************
+void vDispClearLine(u8 ucRow)
+{
+    u8 i,j;
+
+    SetLcdRow(&ucRow);
+	
+    if ( --ucRow >= 4 )
+    {
+        return ;
+    }
+	
+    ucRow += ucRow;
+    for ( i = 0; i < 2; i++ )
+    {
+        _vDispAddr(ucRow, 0);
+        ucDispDT = 0;
+        for ( j = 0; j < 128; j++ )
+        {
+            (*WriteData)();
+        }
+        _vDispAddr(ucRow + 1, 0);
+        ucDispDT = 0;
+        for (j = 0; j < 128; j++)
+        {
+            (*WriteData)();
+        }
+    }
+}
+
+void Display_Icon16(u8 ucRow, u8 ucCol, unsigned char *icon)
+{
+	u8 pZiMo;
+
+	SetLcdRow(&ucRow);
+	
+	if ( --ucRow >= 4 )
+	{
+		return ;
+	}
+	if ( --ucCol > 16 )
+	{
+		return ;
+	}
+
+	ucRow += ucRow;
+	ucCol <<= 3; 
+
+	_vDispAddr(ucRow, ucCol);
+	ucDispDT = 0x00;
+	for ( pZiMo = 0; pZiMo < 8; pZiMo++ )
+	{
+		if ( icon != 0 )
+		{
+			ucDispDT = icon[pZiMo];
+		}
+		(*WriteData)();
+	}
+	
+	_vDispAddr(ucRow+1, ucCol);
+	for ( ; pZiMo < 16; pZiMo++ )
+	{
+		if ( icon != 0 )
+		{
+			ucDispDT = icon[pZiMo];
+		}
+		(*WriteData)();
+	}
+
+    (*WriteIR)(0xaf);     // ʾ//20070913heq
+    (*WriteIR)(0x2f);     // Power   //20070913heq
+}
+
+void Display_Icon(u8 ucRow, u8 ucCol, unsigned char *icon,u8 size)
+{
+	u8 pZiMo;
+
+	SetLcdRow(&ucRow);
+	
+	if ( --ucRow >= 4 )
+	{
+		return ;
+	}
+	if ( --ucCol >= 16 )
+	{
+		return ;
+	}
+
+	ucRow += ucRow;
+	ucCol <<= 3; 
+
+	_vDispAddr(ucRow, ucCol);
+	ucDispDT = 0x00;
+	//for ( pZiMo = 0; pZiMo < 16; pZiMo++ )
+	for ( pZiMo = 0; pZiMo < size; pZiMo++ )
+	{
+		if ( icon != 0 )
+		{
+			ucDispDT = icon[pZiMo];
+		}
+		(*WriteData)();
+	}
+
+	_vDispAddr(ucRow + 1, ucCol);
+	//for ( ; pZiMo < 32; pZiMo++ )
+	for ( ; pZiMo < (2*size); pZiMo++ )
+	{
+		if ( icon != 0 )
+		{
+			ucDispDT = icon[pZiMo];
+		}
+		(*WriteData)();
+	}
+
+    (*WriteIR)(0xaf);     // ʾ//20070913heq
+    (*WriteIR)(0x2f);     // Power   //20070913heq
+}
+
+#if 0
+///AntiColor = 1   ʽʾ
+///AntiColor = 0   ʾ
+void vDispStr_light(u8 ucRow, u8 ucCol, char *szData, u8 AntiColor)
+{
+	u8 ZiMo[32], pZiMo;
+	u8 ucDispT1, ucDispT2, ucDispT4;
+	u32  uiDispT;
+	u32  uiDispT1;
+
+	//SetMayWatchDog();
+	IWDG_Feed();
+
+	//SetLcdRow(&ucRow);
+	
+    if ( --ucRow >= 4 )
+    {
+        return ;
+    }
+    if ( --ucCol >= 16 )
+    {
+        return ;
+    }
+	
+    ucRow += ucRow;
+    ucCol <<= 3; // *8
+    while ( (*szData != 0) && (ucCol < 128) )
+    {
+        ucDispT1 = *szData;
+        szData++;
+        if ( ucDispT1 == 0xff )
+        {
+            return ;
+        }
+		
+        //û0XFFʼĺ
+        if ( ucDispT1 < 0x80 )
+        {
+            //ASC
+            uiDispT = ucDispT1 << 4;
+            //uiDispT <<= 4;
+            pZiMo = 0;
+            vI2cRead(vI2cHzkGetStart( uiDispT + 222080l),16,(char *)ZiMo);
+
+            _vDispAddr(ucRow, ucCol);
+			if ( AntiColor )
+			{
+                for ( ucDispT4 = 0; ucDispT4 < 8; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+                    (*WriteData)();
+                }
+
+                _vDispAddr(ucRow + 1, ucCol);
+                for ( ucDispT4 = 8; ucDispT4 < 16; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+                    (*WriteData)();
+                }
+			}
+			else
+			{
+                for ( ucDispT4 = 0; ucDispT4 < 8; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++];
+                    (*WriteData)();
+                }
+
+                _vDispAddr(ucRow + 1, ucCol);
+                for ( ucDispT4 = 8; ucDispT4 < 16; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++];
+                    (*WriteData)();
+                }
+			}
+            ucCol += 8;
+        }
+        else
+        {
+            ucDispT2 =  *szData;
+            szData++;
+            if ( ucCol > 112 )
+            {
+                break;
+            }
+            if ( ucDispT1 >= 0xB0 )
+            {
+                //B0A1~F7FF
+                ucDispT1 -= 0xAE;
+            }
+            else if ( ucDispT1 == 0xA1 )
+            {
+                //A1A1~A1FF
+                ucDispT1 = 0;
+            }
+            else if ( ucDispT1 == 0xA3 )
+            {
+                //A3A1~A3FF
+                ucDispT1 = 1;
+            }
+            else
+            {
+                continue;
+            }
+            ucDispT2 -= 0xA1;
+
+            ucDispT1 <<= 1; //*2;   47
+            uiDispT = ucDispT1 << 4;
+            uiDispT1 = uiDispT;
+            uiDispT <<= 1;
+            uiDispT += uiDispT1;
+            uiDispT -= ucDispT1;
+            uiDispT += ucDispT2;
+            pZiMo = 0;
+            vI2cRead(vI2cHzkGetStart(uiDispT<<5),32,(char *)ZiMo);
+
+            _vDispAddr(ucRow, ucCol);
+			if ( AntiColor )
+			{
+                for ( ucDispT4 = 0; ucDispT4 < 8; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+                    (*WriteData)();
+                }
+			}
+			else
+			{
+                for ( ucDispT4 = 0; ucDispT4 < 8; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++];
+                    (*WriteData)();
+                }
+			}
+            if ( ucCol < 56 )
+            {
+				if ( AntiColor )
+				{
+	                for ( ucDispT4 = 8; ucDispT4 < 16; ucDispT4++ )
+	                {
+	                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+	                    (*WriteData)();
+	                }
+				}
+				else
+				{
+	                for ( ucDispT4 = 8; ucDispT4 < 16; ucDispT4++ )
+	                {
+	                    ucDispDT = ZiMo[pZiMo++];
+	                    (*WriteData)();
+	                }
+				}
+            }
+            else
+            {
+                if ( ucCol == 56 )
+                {
+                    _vDispAddr(ucRow, 64);
+                }
+				if ( AntiColor )
+				{
+	                for ( ucDispT4 = 8; ucDispT4 < 16; ucDispT4++ )
+	                {
+	                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+	                    (*WriteData)();
+	                }
+				}
+				else
+				{
+	                for ( ucDispT4 = 8; ucDispT4 < 16; ucDispT4++ )
+	                {
+	                    ucDispDT = ZiMo[pZiMo++];
+	                    (*WriteData)();
+	                }
+				}
+            }
+            _vDispAddr(ucRow + 1, ucCol);
+			if ( AntiColor )
+			{
+                for ( ucDispT4 = 16; ucDispT4 < 24; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+                    (*WriteData)();
+                }
+			}
+			else
+			{
+                for ( ucDispT4 = 16; ucDispT4 < 24; ucDispT4++ )
+                {
+                    ucDispDT = ZiMo[pZiMo++];
+                    (*WriteData)();
+                }
+			}
+            if ( ucCol < 56 )
+            {
+				if ( AntiColor )
+				{
+	                for ( ucDispT4 = 24; ucDispT4 < 32; ucDispT4++ )
+	                {
+	                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+	                    (*WriteData)();
+	                }
+				}
+				else
+				{
+	                for ( ucDispT4 = 24; ucDispT4 < 32; ucDispT4++ )
+	                {
+	                    ucDispDT = ZiMo[pZiMo++];
+	                    (*WriteData)();
+	                }
+				}
+            }
+            else
+            {
+                if ( ucCol == 56 )
+                {
+                    _vDispAddr(ucRow + 1, 64);
+                }
+				if ( AntiColor )
+				{
+	                for ( ucDispT4 = 24; ucDispT4 < 32; ucDispT4++ )
+	                {
+	                    //vI2cGetHzk();
+	                    ucDispDT = ZiMo[pZiMo++] ^ 0xFF;
+	                    (*WriteData)();
+	                }
+				}
+				else
+				{
+	                for ( ucDispT4 = 24; ucDispT4 < 32; ucDispT4++ )
+	                {
+	                    //vI2cGetHzk();
+	                    ucDispDT = ZiMo[pZiMo++];
+	                    (*WriteData)();
+	                }
+				}
+            }
+            ucCol += 16;
+        }
+    }
+    (*WriteIR)(0xaf);     // ʾ//20070913heq  //20071108heq
+    (*WriteIR)(0x2f);     // Power   //20070913heq //20071108heq
+}
+
+void vDispStr(u8 ucRow, u8 ucCol, char *szData)
+{
+	vDispStr_light(ucRow,ucCol,szData,0);
+}
+#else
+void vDispStr(u8 ucRow, u8 ucCol, char *szData,unsigned char datalen)
+{
+	u16 i;
+	u16 temHz;
+	u8 buf[16];
+	if(datalen<=0)
+	{
+		return ;
+	}		
+	for(i=0;i0;i--){	  	// 1ms
+		 	for(j=18;j>0;j--);	// 1us
+		}
+	}	
+}
+void delay_5us(unsigned short timeCnt)
+{
+	unsigned short j;
+	while(timeCnt--){
+		 	for(j=18;j>0;j--);	// 1us
+	}	
+}
+
+
+
diff --git a/bsp/delay.h b/bsp/delay.h
new file mode 100644
index 0000000..dd1216b
--- /dev/null
+++ b/bsp/delay.h
@@ -0,0 +1,9 @@
+#ifndef _DELAY_H
+#define _DELAY_H
+#include "stm32f10x.h"
+
+void delay_ms(unsigned short timeCnt);
+void delay_5us(unsigned short timeCnt);
+
+
+#endif
diff --git a/bsp/flash.c b/bsp/flash.c
new file mode 100644
index 0000000..2ac8ae6
--- /dev/null
+++ b/bsp/flash.c
@@ -0,0 +1,213 @@
+/**
+  ******************************************************************************
+  **˵2.4Güд
+  **ܣЭáдIC
+  **ߣ֣
+  **ڣ2017.08
+  ******************************************************************************
+**/ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "flash.h"
+#include "printf.h"
+
+
+// BYTE thenticated = FALSE;
+u16 StoreBuffer[STORE_DATA_NUM];
+u8 Save_Buffer[STORE_DATA_NUM*2];
+/*****************************************************************************************************
+** : Startwritedata()
+** : ʼflashд
+** ӿڲ: addr
+** ȫֱ: 
+**   壺ADDR_BASE
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ
+		addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+void Startwritedata(DWORD addr)
+{
+  FLASH_Unlock();		      //ÿβFlashʱȽ
+  FLASH_ErasePage(addr);      //ҳ
+}
+
+/*****************************************************************************************************
+** : Write_Complete()
+** : 
+** ӿڲ: 
+** ȫֱ: 
+**   壺ADDR_BASE
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ
+		addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+void Write_Complete(void)
+{ 
+ 
+  FLASH_Lock();				       //
+
+}
+
+
+
+/*****************************************************************************************************
+** : SavePara()
+** :һ Ϊ16λ
+** ӿڲ: addr,data
+** ȫֱ: 
+**   壺ADDR_BASE
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ
+		addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+void SavePara(DWORD addr,WORD data)
+{ 
+
+  FLASH_ProgramHalfWord(addr,data);//д16λ
+
+}
+
+
+
+
+/*****************************************************************************************************
+** : GetPara()
+** : 
+** ӿڲ: ȡ addr ַ
+** ȫֱ: 
+**   壺ADDR_BASE
+** ú:
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע: addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+WORD GetPara(DWORD addr)
+{ 
+   WORD data;
+   data=(WORD)(*(DWORD*)addr); //ȡӦַе16λ
+   return data;
+}
+
+/*****************************************************************************************************
+** : Savestr_to_flash()
+** : һݴ浽ָĵַ
+** ӿڲ: addr,datalen
+** ȫֱ: 
+**   壺
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ
+		addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+void Savestr_to_flash(DWORD addr,WORD *str,WORD len)
+{
+  BYTE i = 0;
+  for(i = 0;i < len;i ++)
+   {
+     SavePara(addr,str[i]);
+	 addr += 2;  
+   }
+}
+
+/*****************************************************************************************************
+** : Readstr_of_flash()
+** : ijַʼȡһַ
+** ӿڲ: addr,datalen
+** ȫֱ: 
+**   壺
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ
+		addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+void Readstr_of_flash(DWORD addr,WORD *str,WORD len)
+{
+  BYTE i = 0;
+  for(i = 0;i < len;i ++)
+   {
+    str[i] = GetPara(addr);
+	 addr += 2;  
+   }
+}
+
+/*****************************************************************************************************
+** : SavePara_to_flash()
+** : һЩ浽flash
+** ӿڲ: addr,data,len
+** ȫֱ: 
+**   壺
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ
+		addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+
+void SavePara_to_flash(void)
+{
+	BYTE i = 0;
+	WORD flash_buf[STORE_DATA_NUM] = {0}; 
+	for(i = 0;i < STORE_DATA_NUM;i ++)
+	{
+		flash_buf[i] = (WORD)StoreBuffer[i];//תҪд			
+	}
+
+	Startwritedata(PC_NUM_ADDR);
+	Savestr_to_flash(PC_NUM_ADDR,flash_buf,STORE_DATA_NUM);
+	Write_Complete(); 
+}
+
+/*****************************************************************************************************
+** : Readstr_of_flash()
+** : ijַʼȡһַ
+** ӿڲ: addr,datalen
+** ȫֱ: 
+**   壺
+**     : 
+**     : 2010.5.13
+------------------------------------------------------------------------------------------------------
+** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ
+		addrַΧADDR_BASE ~ADDR_BASE+1022
+*****************************************************************************************************/
+void Readpara_from_flash(void)
+{
+	BYTE i = 0;
+	WORD flash_buf[STORE_DATA_NUM] = {0}; //16λFLASHд
+//	BYTE Save_Buffer[STORE_DATA_NUM*2]={0}; //8λ飬16λת
+	Readstr_of_flash(PC_NUM_ADDR,flash_buf,STORE_DATA_NUM);
+
+	for(i = 0;i < STORE_DATA_NUM;i ++)
+	{
+		Save_Buffer[2*i] = (WORD)flash_buf[i];
+//		printf("Ͱλ %d=%d \r\n",i,Save_Buffer[2*i]); //ӡ16λݵĵͰλ
+
+//		Save_Buffer[2*i + 1] = (WORD)(flash_buf[i] >>=8);			
+//		printf("߰λ=%u \r\n",Save_Buffer[2*i+1]); //ӡ߰λ
+
+	}
+    
+//    printf("Ƶ = %d \r\n",Save_Buffer[2*0]); //ӡ16λݵĵͰλ
+//    printf("ù = %d \r\n",Save_Buffer[2*1]); //ӡ16λݵĵͰλ
+//    printf(" = %d \r\n",Save_Buffer[2*2]); //ӡ16λݵĵͰλ
+}
+
+
+
+
+
diff --git a/bsp/flash.h b/bsp/flash.h
new file mode 100644
index 0000000..d91a4f3
--- /dev/null
+++ b/bsp/flash.h
@@ -0,0 +1,35 @@
+#ifndef _FLASH_H_
+#define _FLASH_H_  
+
+#include "stm32f10x.h"
+
+
+
+/** ע:ÿдǰȲҪ洢λڵҳǺEEPROMIJ֮ͬFlash߱޸Ĺܣ
+        ֻȲдʱֻ֧ҳ	  */
+//flash洢ʱ16λʽ洢,
+#define  PC_NUM_ADDR         0x08030000  		//ݴ洢ʼַ 	   0X08030000-0X08030023
+
+#define  STORE_DATA_NUM         10    //еݸ
+extern  u16 StoreBuffer[STORE_DATA_NUM];//Ҫдflashе
+extern u8 Save_Buffer[STORE_DATA_NUM*2];//Ҫͨڶ
+
+typedef  unsigned char   BOOL;
+typedef  unsigned char   BYTE;
+typedef  unsigned short  WORD;
+typedef  unsigned long   DWORD;
+
+//void Startwritedata(DWORD addr);          //ڿԵַaddrʼġҳд
+//void Write_Complete(void);                    //ijҳд  	  
+//void SavePara(DWORD addr,WORD data);	  //ַָaddrдݣֽڣ
+//WORD GetPara(DWORD addr);	  		  //ȡַָaddrݣֽڣ
+//void Savestr_to_flash(DWORD addr,WORD *str,WORD len);//һݴ浽ԣaddrΪʼַ	  
+//void Readstr_of_flash(DWORD addr,WORD *str,WORD len);//ӣaddrΪʼַȡһַ	  
+
+void SavePara_to_flash(void);        //豸ڵ 
+void Readpara_from_flash(void);      //ȡϴζϵʱ豸еһЩ
+
+#endif
+
+
+
diff --git a/bsp/main.c b/bsp/main.c
new file mode 100644
index 0000000..0085843
--- /dev/null
+++ b/bsp/main.c
@@ -0,0 +1,597 @@
+/**
+  ******************************************************************************
+  **˵003Ŀд
+  **ܣ⿨д
+  **ߣBruce
+  **ڣ2017.6.8
+  ******************************************************************************
+**/ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "printf.h"
+#include "USART2.h"
+#include "LED.h"
+#include "delay.h"
+#include "nrf24L01.h"
+#include "DataProc.h"
+#include "tim.h"
+#include "flash.h"
+#include "LCD.h"
+
+
+
+/* Functions ---------------------------------------------------------*/
+void RCC_Configuration(void);
+void NVIC_Configuration(void);
+
+void IWDG_Init(u8 prer,u16 rlr);
+void IWDG_Feed(void);
+
+extern unsigned char txBuf[32];
+extern u8 protocol_config_flg;
+extern u8 first_clear_flag;
+
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+
+#define SYSCLK_FREQ_24MHz  24000000
+#else
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/** @addtogroup STM32F10x_StdPeriph_Template
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+  * @brief  Main program.
+  * @param  None
+  * @retval None
+  */
+#if 1
+#define SCAN_ADDRESS         (unsigned char*)"\x34\x43\x10\x10\x01"
+#define SCAN_SETUPVALUE      0x07
+#define SCAN_TX_ADR_WIDTH    (5)       //3???????
+#define SCAN_RX_ADR_WIDTH    (5)       //3???????
+#define SCAN_RX_PLOAD_WIDTH  (10)    //32?????????
+#define SCAN_TX_PLOAD_WIDTH  (10)      //32?????????
+#define SCAN_RF_CRC          (0x00)
+#define SCAN_RF_ENAA         (0x01)
+#define  SCAN_TX_CHNL       (40)      //??????1
+#define  SCAN_RX_CHNL       (40)      //??????2
+#define  SCAN_DYNPD         (0x01)
+#define  SCAN_FEATURE       (0x07)
+
+void NRF24L01_TELPO_RX_Mode(SPIType spiNum,unsigned char* addr,
+                             unsigned char addrlen,
+                             unsigned char rf_channel,
+                             unsigned char rf_setup,
+                             unsigned char rf_crc,
+                             unsigned char rf_enaa,  
+                             unsigned char len,
+                             unsigned char dynpd,
+                             unsigned char feature)
+{
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+SETUP_AW,addrlen - 2);//???? --3??
+    NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+RX_ADDR_P0,(u8*)addr,addrlen);//?RX???? 
+    NRF24L01_Write_Buf(spiNum,NRF_WRITE_REG+TX_ADDR,(u8*)addr,addrlen);//?TX???? 
+
+   
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_AA,rf_enaa);    //????0?????    
+
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+EN_RXADDR,0x01);//????0?????    
+
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_CH,rf_channel);        //??RF????
+                                                   
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RF_SETUP,rf_setup);//??TX????,0db??,1Mbps,???????     
+    
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+RX_PW_P0,len);//????0??????? 
+    
+
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+CONFIG, (0x3b | rf_crc));//???????????;PWR_UP,EN_CRC,16BIT_CRC,???? 
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+DYNPD,dynpd);
+
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+FEATURF,feature);  
+    NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,0x70);       //??TX_DS?MAX_RT????
+    NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff);   //??RX FIFO???  
+}  
+
+
+void NRF24L01_RX_TelPo_CONFIG1(SPIType spiNum)
+{
+	if(spiNum == SPI_PORT1){
+		SPI1_CE =0;
+	}else{
+		SPI2_CE=0;	
+	}	
+        NRF24L01_TELPO_RX_Mode(spiNum,SCAN_ADDRESS,SCAN_RX_ADR_WIDTH,SCAN_RX_CHNL,
+                         SCAN_SETUPVALUE,SCAN_RF_CRC,SCAN_RF_ENAA,
+                         SCAN_RX_PLOAD_WIDTH,SCAN_DYNPD,SCAN_FEATURE); 
+   	if(spiNum == SPI_PORT1){     //CEΪ,ģʽ
+		SPI1_CE =1;
+	}else{
+		SPI2_CE=1;	
+	}     
+}	 
+#endif
+u8 NRF24L01_RxPacket1(SPIType spiNum,u8 *rxbuf,unsigned char rxLen)
+{
+  u8 sta;                  
+    SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_16);
+  //SPI_SetSpeed(spiNum,SPI_BaudRatePrescaler_8); //spi???9Mhz(24L01???SPI???10Mhz)   
+  sta=NRF24L01_Read_Reg(spiNum,STATUS);  //?????????       
+  
+  if(sta&RX_OK)//?????
+  {
+      
+
+    NRF24L01_Read_Buf(spiNum,RD_RX_PLOAD,rxbuf,rxLen);  //????
+    NRF24L01_Write_Reg(spiNum,FLUSH_RX,0xff);  //??RX FIFO??? 
+      NRF24L01_Write_Reg(spiNum,NRF_WRITE_REG+STATUS,sta); //??TX_DS?MAX_RT????  
+    delay_5us(20);
+    return 0; 
+  }     
+  return 1;//???????
+}   
+
+
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+    //SCB->VTOR = FLASH_BASE | 0x10000; /* Vector Table Relocation in Internal FLASH. */
+
+    RCC_Configuration();    //ϵͳʱ
+    
+    NVIC_Configuration();   //ж
+    
+    IWDG_Init(4,625);   //(4*2^4)*625/40 ms = 1s Źʱ1s
+    IWDG_Feed();
+    
+    TIM3_Int_Init(9,7199);
+    
+    led_init();             //LED IO
+#if LCD
+    lcd_init();             //LCD 
+    AttenuatorConfig();     //˥
+#endif
+    
+	USART_Configuration();  //13ʼ  1Ϊ115200 3Ϊ4800
+    
+    USART2_Init(115200);    //2ʼ Ϊ115200 Debug
+    
+    NRF24L01_Init();        //24L01 IO
+    
+    IWDG_Feed();
+//    while(NRF24L01_Check(SPI_REV)){	    //NRF24L01 1Ƿ
+//		printf("The 2.4G Error!");
+//	}
+#if 1    
+    while(NRF24L01_Check(SPI_SEND)){	    //NRF24L01 2Ƿ
+		printf("The 2.4G Error!");
+	}
+#endif    
+    Data_Init();   //ݳʼ
+    
+    IWDG_Feed();
+    led0=~led0;
+    delay_ms(200);
+    led0=~led0;
+    
+    DegugPrintf("123456",6);
+    SendUSART2Str("\n");
+                        
+    IWDG_Feed();
+#if 0	
+while(1)
+{	  
+	  NRF24L01_RX_TelPo_CONFIG1(SPI_SEND);
+	  while(1)
+	  {	 
+        u8 Rx_Buffer[32] = {0};
+		
+        if (!NRF24L01_RxPacket1(SPI_SEND,Rx_Buffer,sizeof(Rx_Buffer)))
+        {
+            break;
+        }
+		
+		IWDG_Feed();        
+	  }
+	  IWDG_Feed(); 
+}
+#endif
+	printf("\nPCͨð汾V2.4-20190906\n");
+//    SendUartData("123456",6,USART2);
+//    printf("System Clock = %d\r\n",SystemCoreClock);
+
+    NRF24L01_RX_Mode(SPI_SEND);
+//    NRF24L01_RX_Mode_NOACK(SPI_SEND);
+//while(1)
+//{
+//	 RF24_CarrierTest(SPI_SEND,32);
+//	delay_ms(100);
+//	 IWDG_Feed();
+//}
+
+ #if 1
+    Readpara_from_flash();  //ݲӡ
+    protocol_config_flg = Save_Buffer[2*0];
+	switch(protocol_config_flg)
+	{
+		case 0:
+		{			
+			printf("Э\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"JIANGXI",7);
+#endif
+			break;
+		}
+		case 1:
+		{
+			printf("첨Э\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"TELPO",5);
+#endif
+			break;
+		}
+		case 2:
+		{
+			printf("Э\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"YUNNAN",6);
+#endif
+			break;
+		}
+		case 3:
+		{
+			printf("Э\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"GUIZHOU",7);
+#endif
+			break;
+		}
+		case 4:
+		{
+			printf("ĴЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"SICHUAN",7);
+#endif
+			break;
+		}
+		case 5:
+		{
+			printf("ɹЭ\r\n"); 
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"NEIMENGGU",9);
+#endif
+			break;
+		}
+		case 6:
+		{
+			printf("Э\r\n"); 
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"ANHUI",5);
+#endif
+			break;
+		}
+		case 7:
+		{
+			printf("ɽŵЭ\r\n"); 
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"SHANXI",6);
+#endif
+			break;
+		}
+		case 8:
+		{
+			printf("VCOM\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"VCOM",4);
+#endif
+			break;
+		}
+		case 9:
+		{
+			printf("\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"LIAONING.DIAN",13);
+#endif
+			break;
+		}
+		case 10:
+		{
+			printf("ƶ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"LIAONING.YI",11);
+#endif
+			break;
+		}
+		case 11:
+		{
+			printf("TpרЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"TP",2);
+#endif
+			break;
+		}
+		case 12:
+		{
+			printf("ɹƶЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"NEIMENGGU.YI",12);
+#endif
+			break;
+		}
+		case 13:
+		{
+			printf("ƶЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"GUANGXI.YI",10);
+#endif
+			break;
+		}
+		case 14:
+		{
+			printf("ĴЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"SICHUN.DIAN",11);
+#endif
+			break;
+		}
+		case 15:
+		{
+			printf("Э\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"FUJIANZHENZHUO",14);
+#endif
+			break;
+		}
+		case 16:
+		{
+			printf("ľЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"SUZHOUMULANG",10);
+#endif
+			break;
+		}
+		case 17:
+		{
+			printf("ƶЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"CHONGQIN.YI",11);
+#endif
+			break;
+		}
+		case 18:
+		{
+			printf("ɽƶЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"SHANXI.YI",9);
+#endif
+			break;
+		}
+		case 19:
+		{
+			printf("ƶЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"GANSU.YI",9);
+#endif
+			break;
+		}
+		case 20:
+		{
+			printf("ŴЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"XDF",3);
+#endif
+			break;
+		}
+		case 21:
+		{
+			printf("ºЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"DH",2);
+#endif
+			break;
+		}
+		case 22:
+		{
+			printf("յЭ\r\n");
+#if LCD
+			vDispClearLine(1);
+			vDispStr(1,1,"AHDX",4);
+#endif
+			break;
+		}		
+	}
+ #endif
+	
+#if 0
+  NRF24L01_RX_TelPo_CONFIG1(SPI_SEND);
+while(1)
+{
+   
+        u8 Rx_Buffer[32] = {0};
+        if (!NRF24L01_RxPacket(SPI_SEND,Rx_Buffer))
+        {
+            break;
+        }
+        
+}	
+	
+#endif
+	
+	
+	
+	
+  /* Infinite loop */
+    //SendConsoleByte(protocol_config_flg);   //ԣظPC
+    //NRF24L01_RX_Mode_NOACK_VCOM(SPI_SEND);
+    first_clear_flag = 1;
+    delay_ms(50);
+    while (1)
+    {
+        
+//		while(1)   //
+//        {                      
+//            if(DataProc_A4_nrf())
+//            break;
+//        }
+        DataProc_1356();        //13.56Mݴ
+ #if LCD       
+        DataProc_RecNrf24L01();
+ #endif
+        
+        DataProc_USART1();      //1ݴPCͨ
+        
+//        DataProc_Nrf24l01_SPI2();
+    }
+}
+
+
+
+void RCC_Configuration(void)
+{
+#if 0
+	ErrorStatus HSEStartUpStatus;                   //öٱʱӵ״̬
+	RCC_DeInit();                                   //RCCϵͳãDebug
+	RCC_HSEConfig(RCC_HSE_ON);                      //ʹܸʱԴHSE  
+	HSEStartUpStatus = RCC_WaitForHSEStartUp();     //ȴHSEȶ
+	if(HSEStartUpStatus == SUCCESS)
+	{	
+		RCC_HCLKConfig(RCC_SYSCLK_Div1);            // HCLK = SYSCLK
+		RCC_PCLK2Config(RCC_HCLK_Div1);             // PCLK2 = HCLK
+		RCC_PCLK1Config(RCC_HCLK_Div2);             // PCLK1 = HCLK/2
+		
+		RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
+		RCC_PLLCmd(ENABLE);
+		while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){}
+		
+		RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+		while(RCC_GetSYSCLKSource() != 0x08){}
+	}
+	RCC_APB2PeriphClockCmd( RCC_APB2Periph_USART1 |RCC_APB2Periph_GPIOA |RCC_APB2Periph_AFIO |RCC_APB2Periph_GPIOB , ENABLE);
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
+#else
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO | RCC_APB2Periph_USART1, ENABLE); 
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
+
+	/* Select AHB clock(HCLK) as SysTick clock source */
+	SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+
+	/* SysTick interrupt each 10ms with HCLK equal to 72MHz */
+	SysTick_Config(240000); 
+
+#endif
+}
+
+void NVIC_Configuration(void)
+{              
+	NVIC_InitTypeDef NVIC_InitStructure;   
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
+
+	NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;           //ô2ж
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;   //ռȼ1
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;          //ȼ2
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;             //ʹж
+	NVIC_Init(&NVIC_InitStructure);
+    
+    NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;           //ô3ж
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;   //ռȼ1
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;          //ȼ1
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;             //ʹж
+	NVIC_Init(&NVIC_InitStructure);
+    
+    NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;           //ô1ж
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;   //ռȼ0
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;          //ȼ1
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;             //ʹж
+	NVIC_Init(&NVIC_InitStructure);
+    
+    NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;             //öʱ3ȫж
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;   //ռȼ0
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;          //ȼΪ0
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;             //ʹ
+	NVIC_Init(&NVIC_InitStructure);
+    
+}
+
+/*
+*Źʼ
+*prer:Ƶ0-73λЧ
+*Ƶӣ4*2^prer256
+*rlr:װؼĴֵ11λЧ
+*Tout=((4*2^prer)*rlr)/40 (ms)
+*/
+void IWDG_Init(u8 prer,u16 rlr)
+{
+    IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); // ʹܶԼĴIWDG_PRIWDG_RLRIJ
+    IWDG_SetPrescaler(prer);    //IWDGԤƵֵ:prer
+    IWDG_SetReload(rlr);        //IWDGֵ
+    IWDG_ReloadCounter();       //ֵIWDG
+    IWDG_Enable();              //ʹIWDG
+}
+
+/**
+ * ι
+ */
+void IWDG_Feed(void)
+{
+    IWDG_ReloadCounter();    /*reload*/
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *   where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/nrf24L01.c b/bsp/nrf24L01.c
new file mode 100644
index 0000000..f85d04c
--- /dev/null
+++ b/bsp/nrf24L01.c
@@ -0,0 +1,957 @@
+#include "nrf24L01.h"
+#include "printf.h"
+#include "delay.h"
+
+const u8 TX_ADDRESS[5]={0x34,0x43,0x10,0x10,0x01}; //͵ַ
+const u8 RX_ADDRESS[5]={0x34,0x43,0x10,0x10,0x01};
+
+const u8 addr[5]={0x33,0x20,0x0D,0x54,0x79};
+const u8 Jiang_Xi[5]={0x33,0x20,0x0D,0x54,0x79};
+
+const u8 TEL_PO[5]={0x34,0x43,0x10,0x10,0x01};
+const u8 YUN_NAN[5]={0x01,0x10,0x10,0x43,0x34};
+const u8 GUI_ZHOU[5]={0x32,0x23,0xAB,0xBA,0x01};
+const u8 SI_CHUAN[5]={0x34,0x12,0xBB,0xAA,0x01};
+const u8 NEI_MENG_GU[5]={0x34,0x12,0x86,0x75,0x01};
+const u8 AN_HUI[5]={0x46,0x56,0x43,0x10,0x00};
+const u8 SHAN_XI_XIN_NUO[5]={0x34,0x6E,0x46,0x10,0x01};
+const u8 VCM[5]={0x34,0x43,0x10,0x10,0x01};
+const u8 LIAO_NING[5]={0x86,0x2c,0x95,0x01,0x01};
+const u8 NEW_LIAO_NING[5] = {0x36,0xE4,0xA7,0xBC,0x01};
+const u8 TP[5] = {0x42,0x18,0xba,0xe8,0x01};
+const u8 NEI_MENG_GU_YI_DONG[5]={0x34,0x12,0x86,0x75,0x01};
+const u8 GUANG_XI_YI_DONG[5]={0x33,0x20,0x0D,0x54,0x00};
+
+const u8 LIAO_NING_DIAN_XI[5]={0x86,0x2C,0x95,0x00,0x00};
+const u8 FU_JIAN_ZHEN_ZHUO[5]={0x5A,0x45,0x4E,0x4B,0x00};
+const u8 SU_ZHOU_MU_LANG[5]={0xAA,0xBB,0x12,0x34,0x00};
+const u8 CHONG_QIN_YI_DONG[5]={0x34,0x12,0xBB,0xAA,0x00};
+const u8 SHAN_XI_YI_DONG[5]={0x25,0x43,0x10,0x12,0x00};
+const u8 QUAN_TONG[5]={0xe7,0x7e,0xe3,0x00,0x00};
+const u8 GAN_SU_YI_DONG[5]={0x42,0x22,0xB6,0xE9,0x00};
+const u8 XDF[5]={0xC0,0x13,0xE3,0x00,0x00};
+const u8 DH[5] = {0x83,0x21,0x95,0x15,0x00};
+const u8 ANHUI_DIANXIN[5] = {0x41,0x15,0x43,0x12,0x00};
+//ʼ24L01IO
+void NRF24L01_Init(void)
+{ 	
+	GPIO_InitTypeDef GPIO_InitStructure;
+
+
+	//ʹPA,B,C˿ʱ
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE);	    	
+
+
+	GPIO_InitStructure.GPIO_Pin = SPI1_CE_Pin;				// SPI1--CE
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 //
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(SPI1_CE_Port, &GPIO_InitStructure);	//ʼָIO
+	GPIO_SetBits(SPI1_CE_Port,SPI1_CE_Pin);//
+
+	GPIO_InitStructure.GPIO_Pin = SPI1_CS_Pin;		// SPI1--CS
+ 	GPIO_Init(SPI1_CS_Port, &GPIO_InitStructure);	//ʼָIO
+ 	GPIO_SetBits(SPI1_CS_Port,SPI1_CS_Pin);//
+
+	GPIO_InitStructure.GPIO_Pin = SPI1_IRQ_Pin;			// SPI1--IRQ
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 //
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(SPI1_IRQ_Port, &GPIO_InitStructure);	//ʼָIO
+	
+	GPIO_InitStructure.GPIO_Pin = SPI2_CE_Pin;	
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 //
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(SPI2_CE_Port, &GPIO_InitStructure);	//ʼָIO
+	GPIO_SetBits(SPI2_CE_Port,SPI2_CE_Pin);//
+
+	GPIO_InitStructure.GPIO_Pin = SPI2_CS_Pin;	
+ 	GPIO_Init(SPI2_CS_Port, &GPIO_InitStructure);	//ʼָIO
+ 	GPIO_SetBits(SPI2_CS_Port,SPI2_CS_Pin);//
+
+	GPIO_InitStructure.GPIO_Pin = SPI2_IRQ_Pin;	         //SPI2--IQR
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 //
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(SPI2_IRQ_Port, &GPIO_InitStructure);	//ʼָIO
+ 	
+						 		 
+    SPI2_Init();    		//ʼSPI	
+	SPI1_Init();
+			 
+	SPI1_CE =0; 			//ʹ24L01
+	SPI1_CSN=1;			//SPIƬѡȡ
+	
+	SPI2_CE =0; 			//ʹ24L01
+	SPI2_CSN=1;			//SPIƬѡȡ
+
+    SPI_SetSpeed(SPI_REV,SPI_BaudRatePrescaler_4);
+
+}
+
+void NRF24L01_Config(SPIType spiNum)
+{
+    if(spiNum == SPI_PORT1)
+    {
+        SPI1_CE = 0;    //chip enable
+        SPI1_CSN = 1;   //SPI disable   
+    }
+    else
+    {
+        SPI2_CE = 0;    //chip enable
+        SPI2_CSN = 1;   //SPI disable
+    }
+    
+}
+
+//SPIдĴ
+//reg:ָĴַ
+//value:дֵ
+u8 NRF24L01_Write_Reg(SPIType spiNum,u8 reg,u8 value)
+{
+	u8 status;	
+	if(spiNum == SPI_PORT1){
+	   	SPI1_CSN=0;                 //ʹSPI
+	  	status =SPI_ReadWriteByte(spiNum,reg);//ͼĴ 
+	  	SPI_ReadWriteByte(spiNum,value);      //дĴֵ
+	  	SPI1_CSN=1;                 //ֹSPI
+	}else{
+		SPI2_CSN=0;                 //ʹSPI
+	  	status =SPI_ReadWriteByte(spiNum,reg);//ͼĴ 
+	  	SPI_ReadWriteByte(spiNum,value);      //дĴֵ
+	  	SPI2_CSN=1;                 //ֹSPI
+	}
+  	return(status);       			//״ֵ̬
+}
+//ȡSPIĴֵ
+//reg:ҪļĴ
+u8 NRF24L01_Read_Reg(SPIType spiNum,u8 reg)
+{
+	u8 reg_val;	
+	if(spiNum == SPI_PORT1){
+	 	SPI1_CSN = 0;          //ʹSPI		
+	  	SPI_ReadWriteByte(spiNum,reg);   //ͼĴ
+	  	reg_val=SPI_ReadWriteByte(spiNum,0XFF);//ȡĴ
+	  	SPI1_CSN = 1;          //ֹSPI
+	}else{
+		SPI2_CSN = 0;          //ʹSPI		
+	  	SPI_ReadWriteByte(spiNum,reg);   //ͼĴ
+	  	reg_val=SPI_ReadWriteByte(spiNum,0XFF);//ȡĴ
+	  	SPI2_CSN = 1;          //ֹSPI
+	}
+  	return(reg_val);           //״ֵ̬
+}	
+
+//ָλöָȵ
+//reg:Ĵ(λ)
+//*pBuf:ָ
+//len:ݳ
+//ֵ,˴ζ״̬Ĵֵ 
+u8 NRF24L01_Read_Buf(SPIType spiNum,u8 reg,u8 *pBuf,u8 len)
+{
+	u8 status,u8_ctr;	 
+	if(spiNum == SPI_PORT1){
+  		SPI1_CSN = 0;           //ʹSPI
+  		status=SPI_ReadWriteByte(spiNum,reg);//ͼĴֵ(λ),ȡ״ֵ̬   	   
+ 		for(u8_ctr=0;u8_ctr>(87ҳ~92ҳ).
+//IOڲ궨
+
+#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) 
+#define MEM_ADDR(addr)  *((volatile unsigned long  *)(addr)) 
+#define BIT_ADDR(addr, bitnum)   MEM_ADDR(BITBAND(addr, bitnum)) 
+
+
+//IOڵַӳ
+#define GPIOA_ODR_Addr    (GPIOA_BASE+12) //0x4001080C 
+#define GPIOB_ODR_Addr    (GPIOB_BASE+12) //0x40010C0C 
+#define GPIOC_ODR_Addr    (GPIOC_BASE+12) //0x4001100C 
+#define GPIOD_ODR_Addr    (GPIOD_BASE+12) //0x4001140C 
+#define GPIOE_ODR_Addr    (GPIOE_BASE+12) //0x4001180C 
+#define GPIOF_ODR_Addr    (GPIOF_BASE+12) //0x40011A0C    
+#define GPIOG_ODR_Addr    (GPIOG_BASE+12) //0x40011E0C    
+
+#define GPIOA_IDR_Addr    (GPIOA_BASE+8) //0x40010808 
+#define GPIOB_IDR_Addr    (GPIOB_BASE+8) //0x40010C08 
+#define GPIOC_IDR_Addr    (GPIOC_BASE+8) //0x40011008 
+#define GPIOD_IDR_Addr    (GPIOD_BASE+8) //0x40011408 
+#define GPIOE_IDR_Addr    (GPIOE_BASE+8) //0x40011808 
+#define GPIOF_IDR_Addr    (GPIOF_BASE+8) //0x40011A08 
+#define GPIOG_IDR_Addr    (GPIOG_BASE+8) //0x40011E08 
+
+//IOڲ,ֻԵһIO!
+//ȷnֵС16!
+
+#define PAout(n)   BIT_ADDR(GPIOA_ODR_Addr,n)  // 
+#define PAin(n)    BIT_ADDR(GPIOA_IDR_Addr,n)  // 
+
+#define PBout(n)   BIT_ADDR(GPIOB_ODR_Addr,n)  // 
+#define PBin(n)    BIT_ADDR(GPIOB_IDR_Addr,n)  // 
+
+#define PCout(n)   BIT_ADDR(GPIOC_ODR_Addr,n)  // 
+#define PCin(n)    BIT_ADDR(GPIOC_IDR_Addr,n)  // 
+
+#define PDout(n)   BIT_ADDR(GPIOD_ODR_Addr,n)  // 
+#define PDin(n)    BIT_ADDR(GPIOD_IDR_Addr,n)  // 
+
+#define PEout(n)   BIT_ADDR(GPIOE_ODR_Addr,n)  // 
+#define PEin(n)    BIT_ADDR(GPIOE_IDR_Addr,n)  //
+
+#define PFout(n)   BIT_ADDR(GPIOF_ODR_Addr,n)  // 
+#define PFin(n)    BIT_ADDR(GPIOF_IDR_Addr,n)  //
+
+#define PGout(n)   BIT_ADDR(GPIOG_ODR_Addr,n)  // 
+#define PGin(n)    BIT_ADDR(GPIOG_IDR_Addr,n)  //
+
+//--------------------------------------------------------------
+//  IO Port define
+
+#if 0
+#define	SPI1_IRQ_Port	GPIOA
+#define	SPI1_IRQ_Pin	GPIO_Pin_0
+#else
+#define	SPI1_IRQ_Port	GPIOB
+#define	SPI1_IRQ_Pin	GPIO_Pin_7
+#endif
+
+
+#define	SPI1_CS_Port	GPIOA				//PORTA
+#define	SPI1_CS_Pin		GPIO_Pin_4
+
+#define	SPI1_SCK_Port	GPIOA
+#define	SPI1_SCK_Pin	GPIO_Pin_5
+
+#define	SPI1_MISO_Port	GPIOA
+#define	SPI1_MISO_Pin	GPIO_Pin_6
+
+#define	SPI1_MOSI_Port	GPIOA
+#define	SPI1_MOSI_Pin	GPIO_Pin_7
+
+#define	SPI1_CE_Port	GPIOB				// PORTB
+#define	SPI1_CE_Pin		GPIO_Pin_6
+
+//----------------------------------------
+#define	SPI2_CS_Port	GPIOB
+#define	SPI2_CS_Pin		GPIO_Pin_12
+
+#define	SPI2_SCK_Port	GPIOB
+#define	SPI2_SCK_Pin	GPIO_Pin_13
+
+#define	SPI2_MISO_Port	GPIOB
+#define	SPI2_MISO_Pin	GPIO_Pin_14
+
+#define	SPI2_MOSI_Port	GPIOB
+#define	SPI2_MOSI_Pin	GPIO_Pin_15
+
+#define	SPI2_CE_Port	GPIOB
+#define	SPI2_CE_Pin		GPIO_Pin_9
+
+#define	SPI2_IRQ_Port	GPIOB
+#define	SPI2_IRQ_Pin	GPIO_Pin_8
+
+
+//SI24R1----SPI1 λ
+#define SPI1_CE  		PBout(6) 		//	SPI1 Ƭѡź
+#define SPI1_CSN  		PAout(4) 		//	SPIƬѡź	   
+#if 0
+#define SPI1_IRQ  		PAin(0)  		//	IRQ
+#else
+#define SPI1_IRQ  		PBin(7)  		//	IRQ
+#endif
+
+
+//SI24R1----SPI2 λ
+#define SPI2_CE  		PBout(9) 		//	SPI1 Ƭѡź
+#define SPI2_CSN  		PBout(12) 		//	SPIƬѡź	   
+#define SPI2_IRQ  		PBin(8)  		//	IRQ
+
+
+
+
+#endif
diff --git a/bsp/printf.c b/bsp/printf.c
new file mode 100644
index 0000000..2f8d421
--- /dev/null
+++ b/bsp/printf.c
@@ -0,0 +1,385 @@
+/**
+**--------------ļϢ--------------------------------------------------------------------------------
+**      : printf.C
+**
+**------------------------------------------------------------------------------------------------------*/
+/******************************************************************
+                     9600
+       Уλ               
+       λ               8
+       ֹͣλ               1
+                     
+*******************************************************************/
+
+#include "printf.h"
+
+#define PRINTF_EN
+
+volatile unsigned char UARTtoConsole_RxBuffer[100];
+volatile unsigned char UARTtoConsole_RxBufferWr = 0; 
+volatile unsigned char UARTtoConsole_RxBufferRd = 0;
+
+
+extern u8 Flag_update;
+
+/*USARTģijʼ*/
+
+/*******************************************************************************
+* Function Name  : USART_Configuration
+* Description    : USART
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_Configuration(void)
+{
+	USART_InitTypeDef USART_InitStructure;
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+    
+#if USART1_EN
+	/* Enable the USART Clock */
+	 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1| RCC_APB2Periph_GPIOA, ENABLE);
+	
+	/* Configure USARTx_Tx as alternate function push-pull */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+	
+	/* Configure USARTx_Rx as input floating */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+/************************************************************************/
+
+	USART_InitStructure.USART_BaudRate = 38400;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;
+	USART_InitStructure.USART_Parity = USART_Parity_No;
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+	USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+    
+	USART_Init(USART1, &USART_InitStructure);
+	USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);	//ʼ1ж
+
+	USART_Cmd(USART1, ENABLE);
+#endif
+
+#if USART3_EN
+    
+/* Enable the USART Clock */
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+	
+	//USART3_TX   GPIOB10
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; //PB10
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;	//
+	GPIO_Init(GPIOB, &GPIO_InitStructure);//ʼGPIOB10
+	   
+	  //USART3_RX	  GPIOB11ʼ
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;//PB11
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;//
+	GPIO_Init(GPIOB, &GPIO_InitStructure);//ʼGPIOA.3  
+/************************************************************************/
+
+	USART_InitStructure.USART_BaudRate = 4800;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;
+	USART_InitStructure.USART_Parity = USART_Parity_No;
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+	USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+	USART_Init(USART3, &USART_InitStructure);
+
+    USART_Init(USART3, &USART_InitStructure); 		//ʼ3
+	USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);	//ʼڽж
+    
+	USART_Cmd(USART3, ENABLE);
+    
+#endif
+
+	/* CPUСȱݣúãֱSend1ֽڷͲȥ
+		1ֽ޷ȷͳȥ */
+    USART_ClearFlag(USART1, USART_FLAG_TC);  
+	return;
+
+}
+
+
+/********************************************************************
+ܣ1
+ڲDatBufҪ͵ݻ	 len:Ҫ͵ݳ
+    أޡ
+    ע
+********************************************************************/
+void Usart1_SendData(u8 *DatBuf, u32 len)
+{
+  u32 i;
+  for(i=0;i>4));
+	 SendUSART2Byte(HexToAscii(temp));
+	 str++;
+  }
+}
+
+/********************************************************************
+ܣ1
+ڲDatBufҪ͵ݻ	 len:Ҫ͵ݳ
+    أޡ
+    ע
+********************************************************************/
+//void Usart1_ReceiveData()
+//{
+//	
+//	while(USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == SET);
+//	
+//}
+
+/*******************************************************************************
+* Function Name  : int fputc(int ch, FILE *f)
+* Description    : Retargets the C library printf function to the USART.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+
+
+#if EN_USART1_RX
+
+u8 USART1_RX_BUF[USART_REC_LEN];   //ջ,USART_REC_LENֽ.
+u8 USART1_TX_CNT;       //ͼ
+volatile u8 USART1_RX_CNT;       //ռ
+u16 USART1_REC_Status;  //ɱ־λ
+u16 USART_APP_RX;   //APPճȼ
+u8 USART1_RX_DAT[USART_APP_LEN] __attribute__ ((at(0X20001000)));//ջ,USART_REC_LENֽ,ʼַΪ0X20001000.
+
+#endif
+
+void USART1_IRQHandler(void)
+{
+	u8 res;
+    
+    
+    if(USART_GetITStatus(USART1,USART_IT_RXNE) != RESET)
+    {
+        USART_ClearITPendingBit(USART1,USART_IT_RXNE);			//жϱ־
+        
+		res = USART_ReceiveData(USART1);
+                
+        USART1_RX_BUF[USART1_RX_CNT] = res;
+            
+        USART1_RX_CNT ++;
+//        
+        
+//        if((USART1_REC_Status&0x8000)==0)
+//        {
+//            if(USART1_REC_Status&0x4000)    //յ0xFA
+//            {
+//                if(res != 0xFB)
+//                {
+//                    USART1_RX_BUF[USART1_RX_CNT] = res;
+//                    USART1_RX_CNT ++;
+//                    if(USART1_RX_CNT>USART_REC_LEN)
+//                        USART1_REC_Status = 0;  //
+//                }
+//                else
+//                {
+//                    USART1_RX_BUF[USART1_RX_CNT] = res;
+//                    USART1_RX_CNT ++;
+//                    USART1_REC_Status=0x8000;   //
+//                }
+//            }
+//            else
+//            {
+//                if(res == 0xFA)                 //յͷ
+//                {
+//                    USART1_RX_BUF[USART1_RX_CNT] = res;
+//                    USART1_RX_CNT ++;
+//                    USART1_REC_Status = 0x4000;//յͷ
+//                }
+//                else if(res=='u')
+//                {
+//                    USART1_RX_BUF[USART1_RX_CNT] = res;
+//                    USART1_RX_CNT ++;
+//                    NVIC_SystemReset(); //ϵͳλ
+//                }
+//                else
+//                {
+//                    USART1_REC_Status = 0;
+//                    USART1_RX_CNT = 0;       //մ
+//                    
+//                }
+//            }
+//        }
+        
+    }
+    
+    if(USART_GetFlagStatus(USART1,USART_FLAG_ORE) == SET) //
+	{
+		USART_ClearFlag(USART1,USART_FLAG_ORE); //SR
+		USART_ReceiveData(USART1); //DR
+	}
+}
+
+#if EN_USART3_RX
+    u8 USART3_RX_BUF[USART_REC_LEN];   
+    u8 USART3_TX_CNT;       //ͼ
+    u8 USART3_RX_CNT;       //ռ
+    u16 USART3_REC_Status;  //ɱ־λ
+#endif
+
+void USART3_IRQHandler(void)
+{
+    u8 res;
+    
+    if(USART_GetITStatus(USART3,USART_IT_RXNE) != RESET)
+    {
+        USART_ClearITPendingBit(USART3,USART_IT_RXNE);			//жϱ־
+        
+		res = USART_ReceiveData(USART3);
+        
+        //USART_SendData(USART2,res); //3յͨ2ӡ
+        
+        USART3_RX_BUF[USART3_RX_CNT] = res;
+		USART3_RX_CNT ++;
+		USART3_RX_CNT &= 0X0F;      //һ֡15λ
+    }
+    
+    if(USART_GetFlagStatus(USART3,USART_FLAG_ORE) == SET) //
+	{
+		USART_ClearFlag(USART3,USART_FLAG_ORE); //SR
+		USART_ReceiveData(USART3); //DR
+	}
+}
+
+#ifdef PRINTF_EN
+int fputc(int ch, FILE *f)
+{
+	/* Place your implementation of fputc here */
+	/* e.g. write a character to the USART */
+	USART1->DR = (u8)ch;
+
+	/* Loop until the end of transmission */
+	while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+
+	return ch;
+}
+#endif
diff --git a/bsp/printf.h b/bsp/printf.h
new file mode 100644
index 0000000..7f972a6
--- /dev/null
+++ b/bsp/printf.h
@@ -0,0 +1,73 @@
+/**
+**--------------ļϢ--------------------------------------------------------------------------------
+**      : printf.h
+**      : Ʒ
+**޸: 
+**        : 
+** ̼ϢV3.4.0             
+**--------------ʷ汾Ϣ----------------------------------------------------------------------------
+** : Ʒ
+**   : v0.01
+** ա: 
+** 衡: ԭʼ汾
+**
+**--------------ǰ汾Ϣ----------------------------------------------------------------------------
+** : Ʒ
+**   : v0.01
+** ա: 
+** 衡: ǰ汾
+**
+**------------------------------------------------------------------------------------------------------*/
+
+#ifndef PRINTF_H
+#define PRINTF_H
+
+#include "stm32f10x.h"
+#include "stdio.h"
+#include "printf.h"
+
+#define USART_REC_LEN  			200  	//ֽ 200
+#define USART_APP_LEN  			20*1024 //ֽ 20K
+
+#define APP 1
+#define APP1 1
+#define	CONSOLE_UART		USART1	 		//Կ
+
+void USART_Configuration(void);
+
+void Usart1_SendData(u8 *DatBuf, u32 len);
+void SendConsoleByte(char d);
+void SendConsoleStr(char *d);
+void SendConsoleData(char *d, u16 len);
+
+char SendUartData(char *s, u16 len, USART_TypeDef* Uart);
+
+void SendUSART2Byte(char d);
+void SendUSART2Str(char *d);
+unsigned char HexToAscii(unsigned char hexData);
+void DegugPrintf(unsigned char *str,unsigned char len);
+
+#define USART1_EN 1
+#define USART3_EN 1
+
+#define EN_USART1_RX 1
+#define EN_USART3_RX 1
+
+extern u8 USART3_RX_BUF[USART_REC_LEN];   
+extern u8 USART3_TX_CNT;       //ͼ
+extern u8 USART3_RX_CNT;       //ռ
+extern u16 USART3_REC_Status;  //ɱ־λ
+
+
+extern u8 USART1_RX_BUF[USART_REC_LEN];   //ջ,USART_REC_LENֽ.
+extern u8 USART1_TX_CNT;       //ͼ
+extern volatile u8 USART1_RX_CNT;       //ռ
+extern u16 USART1_REC_Status;  //ɱ־λ
+ 
+
+extern volatile unsigned char UARTtoConsole_RxBuffer[100];
+extern volatile unsigned char UARTtoConsole_RxBufferWr ; 
+extern volatile unsigned char UARTtoConsole_RxBufferRd ;
+
+#endif
+
diff --git a/bsp/spi.c b/bsp/spi.c
new file mode 100644
index 0000000..896f45d
--- /dev/null
+++ b/bsp/spi.c
@@ -0,0 +1,127 @@
+#include "spi.h"
+
+//*************************
+//   SPI1  Initation
+//
+//*************************
+void SPI1_Init()  		//SPI1ʼ
+{
+
+	GPIO_InitTypeDef  GPIO_InitStructure;
+	SPI_InitTypeDef	 SPI_InitStructure;
+
+
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_SPI1|RCC_APB2Periph_AFIO, ENABLE);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7;		//PA5 PA6 PA7	   
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 	 //
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //IOٶΪ50MHz
+	GPIO_Init(GPIOA, &GPIO_InitStructure);			     
+	GPIO_SetBits(GPIOA,GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7);  //
+	
+	SPI_InitStructure.SPI_Direction=SPI_Direction_2Lines_FullDuplex; //	SPI Ϊ˫˫ȫ˫
+	SPI_InitStructure.SPI_Mode=SPI_Mode_Master;	//SPIΪģʽ
+	SPI_InitStructure.SPI_DataSize=SPI_DataSize_8b;	//SPIݴСΪ8λ
+	SPI_InitStructure.SPI_CPOL=SPI_CPOL_Low;	//SPIĬʱΪߵƽ
+	SPI_InitStructure.SPI_CPHA=SPI_CPHA_1Edge;	//SPIݲڵڶʱ
+	SPI_InitStructure.SPI_NSS=SPI_NSS_Soft;	//SPI NSSܽ
+	SPI_InitStructure.SPI_BaudRatePrescaler=SPI_BaudRatePrescaler_16;	//SPI ԤƵֵΪ 256
+	SPI_InitStructure.SPI_FirstBit=SPI_FirstBit_MSB;	//SPI ݴӸλ
+	SPI_InitStructure.SPI_CRCPolynomial=7;	//SPI CRCֵĶʽ
+	SPI_Init(SPI1,&SPI_InitStructure);
+		
+	SPI_Cmd(SPI1,ENABLE); //ʹSPI1
+
+}
+
+//*************************
+//   SPI2
+//
+//*************************
+void SPI2_Init()  //SPI2ʼ
+{
+
+	GPIO_InitTypeDef  GPIO_InitStructure;
+	SPI_InitTypeDef	 SPI_InitStructure;
+
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);//SPI2ʱ
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB|RCC_APB2Periph_AFIO, ENABLE);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15;		//PB13 PB14 PB15	   
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 	 //
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //IOٶΪ50MHz
+	GPIO_Init(GPIOB, &GPIO_InitStructure);			     
+	GPIO_SetBits(GPIOB,GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15);  //
+	
+	SPI_InitStructure.SPI_Direction=SPI_Direction_2Lines_FullDuplex; //	SPI Ϊ˫˫ȫ˫
+	SPI_InitStructure.SPI_Mode=SPI_Mode_Master;	//SPIΪģʽ
+	SPI_InitStructure.SPI_DataSize=SPI_DataSize_8b;	//SPIݴСΪ8λ
+	SPI_InitStructure.SPI_CPOL=SPI_CPOL_Low;	//SPIĬʱΪߵƽ
+	SPI_InitStructure.SPI_CPHA=SPI_CPHA_1Edge;	//SPIݲڵڶʱ
+	SPI_InitStructure.SPI_NSS=SPI_NSS_Soft;	//SPI NSSܽ
+	SPI_InitStructure.SPI_BaudRatePrescaler=SPI_BaudRatePrescaler_16;	//SPI ԤƵֵΪ 256
+	SPI_InitStructure.SPI_FirstBit=SPI_FirstBit_MSB;	//SPI ݴӸλ
+	SPI_InitStructure.SPI_CRCPolynomial=7;	//SPI CRCֵĶʽ
+	SPI_Init(SPI2,&SPI_InitStructure);
+		
+	SPI_Cmd(SPI2,ENABLE); //ʹSPI2
+
+}
+
+//----------------------------------------------------------------
+// SPIдһֽ
+//
+u8 SPI_ReadWriteByte(SPIType spiNum,u8 dat)		 //SPI2дһֽ
+{
+	u8 t;
+	u8 temp8;
+	if(spiNum == SPI_PORT1){
+		while(SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_TXE)==RESET)	//ȴͻ
+		{
+			t++;
+			if(t>=200)return 0;	//ʱش־	
+		}
+		SPI_I2S_SendData(SPI1,dat); //
+		t=0;
+		while(SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_RXNE)==RESET)	//ȴ
+		{
+			t++;
+			if(t>=200)return 0;	//ʱش־	
+		}
+		temp8 =  SPI_I2S_ReceiveData(SPI1); //SPI1յ
+
+	}else{	
+
+		while(SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_TXE)==RESET)	//ȴͻ
+		{
+			t++;
+			if(t>=200)return 0;	//ʱش־	
+		}
+		SPI_I2S_SendData(SPI2,dat); //
+		t=0;
+		while(SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_RXNE)==RESET)	//ȴ
+		{
+			t++;
+			if(t>=200)return 0;	//ʱش־	
+		}
+		temp8 =  SPI_I2S_ReceiveData(SPI2); //SPI2յ
+	}
+	return temp8;
+}
+
+void SPI_SetSpeed(SPIType spiNum,u8 SPI_BaudRatePrescaler)	//SPI2ٶ
+{
+	assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_BaudRatePrescaler));	
+	if(spiNum == SPI_PORT1){
+		SPI1->CR1&=0XFFC7;		 //޸BR[2:0]ֵ
+		SPI1->CR1|=SPI_BaudRatePrescaler;	//SPI1ٶ 
+		SPI_Cmd(SPI2,ENABLE);	
+
+	}else{
+		SPI2->CR1&=0XFFC7;		 //޸BR[2:0]ֵ
+		SPI2->CR1|=SPI_BaudRatePrescaler;	//SPI2ٶ 
+		SPI_Cmd(SPI2,ENABLE);	
+	}
+}
+
+
diff --git a/bsp/spi.h b/bsp/spi.h
new file mode 100644
index 0000000..8fbc3fe
--- /dev/null
+++ b/bsp/spi.h
@@ -0,0 +1,19 @@
+#ifndef _SPI_H
+#define _SPI_H
+
+#include "stm32f10x.h"
+
+
+//-----------------------------------------------------------------
+//  SPI PORT define	
+typedef enum SPI_TYPE{SPI_PORT1,SPI_PORT2}SPIType;             // SPI_PORT1---->SPI1;  SPI_PORT2---->SPI2
+
+//---------------------------------------------------------------
+void SPI1_Init(void);  //SPI1ʼ
+void SPI2_Init(void);  //SPI2ʼ
+
+u8 SPI_ReadWriteByte(SPIType spiNum,u8 dat); //SPI2дһֽ
+void SPI_SetSpeed(SPIType spiNum,u8 SPI_BaudRatePrescaler);//SPI2ٶ
+
+#endif
+
diff --git a/bsp/stmflash.c b/bsp/stmflash.c
new file mode 100644
index 0000000..b6b8eee
--- /dev/null
+++ b/bsp/stmflash.c
@@ -0,0 +1,109 @@
+#include "stmflash.h"
+#include "stm32f10x_flash.h"
+
+
+u16 StoreBuffer[STORE_DATA_NUM];
+u8 Save_Buffer[STORE_DATA_NUM*2];
+
+//ȡַָİ(16λ)
+//faddr:ַ(˵ַΪ2ı!!)
+//ֵ:Ӧ.
+u16 STMFLASH_ReadHalfWord(u32 faddr)
+{
+	return *(vu16*)faddr; 
+}
+#if STM32_FLASH_WREN	//ʹд   
+//д
+//WriteAddr:ʼַ
+//pBuffer:ָ
+//NumToWrite:(16λ)   
+void STMFLASH_Write_NoCheck(u32 WriteAddr,u16 *pBuffer,u16 NumToWrite)   
+{ 			 		 
+	u16 i;
+	for(i=0;i=(STM32_FLASH_BASE+1024*STM32_FLASH_SIZE)))return;//Ƿַ
+	FLASH_Unlock();						//
+	offaddr=WriteAddr-STM32_FLASH_BASE;		//ʵƫƵַ.
+	secpos=offaddr/STM_SECTOR_SIZE;			//ַ  0~127 for STM32F103RBT6
+	secoff=(offaddr%STM_SECTOR_SIZE)/2;		//ڵƫ(2ֽΪλ.)
+	secremain=STM_SECTOR_SIZE/2-secoff;		//ʣռС   
+	if(NumToWrite<=secremain)secremain=NumToWrite;//ڸΧ
+	while(1) 
+	{	
+		STMFLASH_Read(secpos*STM_SECTOR_SIZE+STM32_FLASH_BASE,STMFLASH_BUF,STM_SECTOR_SIZE/2);//
+		for(i=0;i(STM_SECTOR_SIZE/2))secremain=STM_SECTOR_SIZE/2;//һд
+			else secremain=NumToWrite;//һд
+		}	 
+	};	
+	FLASH_Lock();//
+}
+#endif
+
+//ַָʼָȵ
+//ReadAddr:ʼַ
+//pBuffer:ָ
+//NumToWrite:(16λ)
+void STMFLASH_Read(u32 ReadAddr,u16 *pBuffer,u16 NumToRead)   	
+{
+	u16 i;
+	for(i=0;i